SCAS042B − MAY 1988 − REVISED APRIL 1996
D Designed Specifically for High-Speed
D
D
D
D
D
D, N, OR PW PACKAGE
(TOP VIEW)
Memory Decoders and Data Transmission
Systems
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Y0
A
B
C
VCC
G1
G2A
G2B
description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of
eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line
decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
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&! #" #" (" "
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•
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•
1
SCAS042B − MAY 1988 − REVISED APRIL 1996
logic symbols (alternatives)†
A
B
C
G1
15
14
13
BIN/OCT
0
1
2
1
4
2
3
&
11
4
10
EN
G2A
5
9
G2B
6
7
16
1
2
3
5
6
7
8
Y0
A
Y1
B
Y2
C
15
13
G1
11
0
G
7
2
2
3
3
&
5
4
10
6
5
9
G2B
Y6
1
1
2
G2A
Y5
16
0
14
Y3
Y4
DMUX
0
7
6
Y7
8
7
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
16
A
Y0
15
1
Y1
2
Select
Inputs
B
Y2
14
3
5
C
7
Enable
Inputs
G2B
G1
2
Data
Outputs
Y4
13
6
G2A
Y3
10
8
9
11
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•
Y5
Y6
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SCAS042B − MAY 1988 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W
N package . . . . . . . . . . . . . . . . . . . . 1.1 W
PW package . . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage
VIL
VI
VO
IOH
IOL
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
MIN
NOM
MAX
3
5
5.5
0.9
1.35
0
0
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 3 V
VCC = 4.5 V
•
•
VCC
VCC
V
V
−4
−24
VCC = 5.5 V
VCC = 3 V
−24
VCC = 4.5 V
VCC = 5.5 V
24
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V
1.65
Output voltage
Low-level output current
V
3.85
Input voltage
High-level output current
V
2.1
3.15
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
UNIT
mA
12
mA
24
0
10
ns/V
−40
85
°C
3
SCAS042B − MAY 1988 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = −50 µA
VOH
IOH = −4 mA
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
3.94
3.8
IOH = −24 mA
5.5 V
4.94
4.8
IOH = −75 mA†
5.5 V
IOL = 12 mA
IOL = 24 mA
II
ICC
TA = 25°C
TYP
MAX
4.5 V
IOL = 50 µA
VOL
MIN
IOL = 75 mA†
VI = VCC or GND
IO = 0
UNIT
V
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
VI = VCC or GND,
VI = VCC or GND
MAX
V
1.65
5.5 V
±0.1
±1
µA
5.5 V
4
40
µA
Ci
5V
3.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A, B, C
Any Y
tPLH
tPHL
G1
Any Y
G2A, G2B
Any Y
tPLH
tPHL
MIN
TA = 25°C
TYP
MAX
MIN
MAX
1.5
8.3
10.2
1.5
11.4
1.5
8.9
10.9
1.5
12.2
1.5
7.2
9.2
1.5
10.2
1.5
7.3
9.4
1.5
10.5
1.5
8.2
10.4
1.5
11.5
1.5
8.3
10.4
1.5
11.6
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
4
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A, B, C
Any Y
tPLH
tPHL
G1
Any Y
tPLH
tPHL
G2A, G2B
Any Y
•
TA = 25°C
MIN
TYP
MAX
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•
MIN
MAX
1.5
5.7
7.3
1.5
8.1
1.5
6.2
7.9
1.5
8.8
1.5
5.1
6.9
1.5
7.5
1.5
5.2
6.9
1.5
7.7
1.5
5.8
7.6
1.5
8.3
1.5
5.6
7.5
1.5
8.3
UNIT
ns
ns
ns
SCAS042B − MAY 1988 − REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
CL = 50 pF,
TYP
f = 1 MHz
51
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
VCC
Input
(see Note B)
From Output
Under Test
CL = 50 pF
(see Note A)
50% VCC
50% VCC
tPHL
500 Ω
0V
tPLH
50% VCC
Output
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
SCAS042B − MAY 1988 − REVISED APRIL 1996
APPLICATION INFORMATION
74AC11138
BIN/OCT
15
14
13
1
2
2
4
11
VCC
0
1
3
&
4
10
EN
9
5
6
7
16
1
2
3
5
6
7
8
0
1
2
3
4
5
6
7
74AC11138
BIN/OCT
15
A0
14
A1
13
A2
1
2
2
4
11
A3
0
1
3
&
4
10
A4
EN
9
5
6
7
16
1
2
3
5
6
7
8
8
9
10
11
12
13
14
15
74AC11138
BIN/OCT
15
14
13
11
0
1
1
2
2
4
3
&
4
10
9
EN
5
6
7
Figure 2. 24-Bit Decoding Scheme
6
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•
16
1
2
3
5
6
7
8
16
17
18
19
20
21
22
23
SCAS042B − MAY 1988 − REVISED APRIL 1996
APPLICATION INFORMATION
74AC11138
BIN/OCT
15
A0
14
A1
13
A2
1
1
2
2
4
11
VCC
0
3
&
4
10
A3
EN
9
A4
5
6
7
16
1
2
3
5
6
7
8
0
1
2
3
4
5
6
7
74AC11138
BIN/OCT
15
14
13
0
1
1
2
2
4
11
3
&
4
10
EN
9
5
6
7
16
1
2
3
5
6
7
8
8
9
10
11
12
13
14
15
74AC11138
BIN/OCT
15
14
13
0
1
1
2
2
4
11
3
&
4
10
EN
9
5
6
7
16
1
2
3
5
6
7
8
16
17
18
19
20
21
22
23
74AC11138
BIN/OCT
15
14
13
11
0
1
1
2
2
4
3
&
4
10
9
EN
5
6
7
16
1
2
3
5
6
7
8
24
25
26
27
28
29
30
31
Figure 3. 32-Bit Decoding Scheme
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7
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74AC11138D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC11138
Samples
74AC11138DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC11138
Samples
74AC11138N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
74AC11138N
Samples
74AC11138NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC11138
Samples
74AC11138PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AE138
Samples
74AC11138PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AE138
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of