74AC11374DBR

74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS214A − JULY 1987 − REVISED APRIL 1996 D D D D D D D D DB, DW, OR NT PACKAGE (TOP VIEW) Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE 1D 2D 3D 4D VCC VCC 5D 6D 7D 8D CLK description This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels set up at the D inputs. The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74AC11374 is characterized for operation from −40°C to 85°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L L X Q0 L H X Q0 L ↓ X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS214A − JULY 1987 − REVISED APRIL 1996 logic symbol† OE CLK 1D 2D 3D 4D 5D 6D 7D 8D † 24 13 23 22 EN C1 1 1D 2 21 3 20 4 17 9 16 10 15 11 14 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 2 24 13 23 C1 1D 1 22 C1 1D 2 21 C1 1D 3 20 C1 1D 4 17 C1 1D 9 16 C1 1D 10 15 C1 1D 11 14 C1 1D 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS214A − JULY 1987 − REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. recommended operating conditions VCC Supply voltage VCC = 3 V VIH High-level High level input voltage MIN NOM MAX 3 5 5.5 Low-level Low level input voltage V 2.1 VCC = 4.5 V 3.15 VCC = 5.5 V 3.85 VCC = 3 V VIL UNIT V 0.9 VCC = 4.5 V 1.35 VCC = 5.5 V 1.65 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 3 V IOH IOL High-level High level output current Low-level Low level output current Dt/Dv Input transition rise or fall rate TA Operating free-air temperature POST OFFICE BOX 655303 −4 VCC = 4.5 V −24 VCC = 5.5 V −24 VCC = 3 V 12 VCC = 4.5 V 24 VCC = 5.5 V 24 Data 0 10 OE 0 5 −40 85 • DALLAS, TEXAS 75265 mA mA ns/V °C 3 74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS214A − JULY 1987 − REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 50 mA VOH IOH = −4 mA IOH = −24 24 mA IOH = −75 mA{ IOL = 12 mA IOL = 24 mA IOL = 75 † TA = 25°C MIN TYP MAX mA{ MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 4.5 V 3.94 3.8 5.5 V 4.94 4.8 5.5 V IOL = 50 mA VOL VCC MAX UNIT V 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V V 1.65 IOZ VO = VCC or GND 5.5 V ±0.5 ±5 mA II VI = VCC or GND 5.5 V ±0.1 ±1 mA ICC VI = VCC or GND, 5.5 V 8 80 mA Ci VI = VCC or GND 5V 4 pF Co VO = VCC or GND 5V 10 pF IO = 0 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX 0 75 MIN MAX UNIT 0 75 MHz fclock Clock frequency tw Pulse duration 6.5 6.5 ns tsu Setup time, data before CLK↑ 2.5 2.5 ns th Hold time, data after CLK↑ 4.5 4.5 ns CLK low or high timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C 4 MIN MAX 0 95 MIN MAX UNIT 0 95 MHz fclock Clock frequency tw Pulse duration 5 5 ns tsu Setup time, data before CLK↑ 2.5 2.5 ns th Hold time, data after CLK↑ 3.5 3.5 ns CLK low or high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS214A − JULY 1987 − REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX MIN MAX fmax 75 90 tPLH 1.5 9.5 12.5 1.5 14.2 1.5 9 12.6 1.5 14 1.5 8 10.9 1.5 12.3 1.5 8 11.1 1.5 12.3 1.5 10 12.1 1.5 12.5 1.5 8 10.7 1.5 11.6 tPHL tPZH tPZL tPHZ tPLZ CLK Any Q OE Any Q OE Any Q 75 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPZH tPZL tPHZ tPLZ CLK Any Q OE Any Q OE Any Q TA = 25°C MAX MIN MAX MIN TYP 95 110 1.5 6.5 9 1.5 10.2 1.5 5.5 9.1 1.5 10.1 1.5 5.5 8 1.5 9.1 1.5 5.5 8.4 1.5 9.4 1.5 9 11 1.5 11.2 1.5 6 8.6 1.5 9.2 95 UNIT MHz ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd flip flop Power dissipation capacitance per flip-flop TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 50 pF f =1 MHz TYP 75 66 UNIT pF 5 74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS214A − JULY 1987 − REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT VCC Timing Input 50% 0V tw tsu VCC Input 50% 50% th VCC 50% 50% Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VCC Input 50% 50% 0V tPHL tPLH VOH In-Phase Output 50% VCC 50% VCC VOL VOH 50% VCC 50% VCC VOL VCC Output Waveform 2 S1 at GND (see Note B) 50% 50% 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC 20% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 74AC11374DBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI -40 to 85 74AC11374DBR OBSOLETE SSOP DB 24 TBD Call TI Call TI -40 to 85 74AC11374DW OBSOLETE SOIC DW 24 TBD Call TI Call TI -40 to 85 74AC11374DWR OBSOLETE SOIC DW 24 TBD Call TI Call TI -40 to 85 74AC11374NT OBSOLETE PDIP NT 24 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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