74AC16244DGGR

54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebust Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC t (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings 54AC16244 . . . WD PACKAGE 74AC16244 . . . DGG OR DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE description The ’AC16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE The 74AC16244 is packaged in the TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16244 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16244 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each driver) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 logic symbol† 1OE 1 48 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 25 24 EN1 EN2 EN3 EN4 47 46 1 1 3 44 5 43 6 41 8 40 1 2 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 19 29 1 4 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . 0.85 W DL package . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 recommended operating conditions (see Note 3) 54AC16244 VCC VIH Supply voltage (see Note 4) VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v Low-level input voltage NOM MAX 3 5 5.5 3 5 5.5 3.15 V V 0.9 0.9 1.35 1.35 1.65 1.65 VCC VCC 0 0 VCC VCC 0 –4 –4 –24 –24 VCC = 5.5 V VCC = 3 V –24 –24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 Input transition rise or fall rate UNIT 3.85 VCC = 3 V VCC = 4.5 V Low-level output current MAX 3.15 0 Output voltage NOM 2.1 3.85 Input voltage MIN 2.1 VCC = 4.5 V VCC = 5.5 V High-level output current 74AC16244 MIN 0 TA Operating free-air temperature –55 NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 k 4. All VCC and GND pins must be connected to the proper voltage supply. V V V mA mA 10 0 10 ns/V 125 –40 85 °C W or greater to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH IOH = –4 mA IOH = –24 24 mA VOL ICC Ci Co MIN TA = 25°C TYP MAX 54AC16244 MIN 74AC16244 MIN 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 MAX 3V 0.1 0.1 0.1 IOL = –50 µA 4.5 V 0.1 0.1 0.1 IOL = 12 mA IOL = 75 mA† VI = VCC or GND VI = VCC or GND VI = VCC or GND, VI = VCC or GND VI = VCC or GND 5.5 V 0.1 0.1 0.1 3V 0.36 0.44 0.44 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 µA 5.5 V IO = 0 UNIT V 5.5 V V 5.5 V ±0.1 5.5 V ±0.5 ±5 ±5 µA 5.5 V 8 80 80 µA 5V 4.5 5V 12 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 MAX IOH = –75 mA† IOL = 24 mA II IOZ VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF 54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y MIN TA = 25°C TYP MAX 54AC16244 74AC16244 MIN MAX MIN MAX 2 7.1 9.4 2 10.8 2 10.8 2.4 8.3 10.7 2.4 11.8 2.4 11.8 2.2 7.5 10 2.2 11.5 2.2 11.5 2.9 10.4 13 2.9 14.6 2.9 14.6 4.1 6.8 8.4 4.1 9.1 4.1 9.1 3.7 6.5 8.1 3.7 8.8 3.7 8.8 UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y TA = 25°C MIN TYP MAX 54AC16244 74AC16244 MIN MAX MIN MAX 1.6 4.6 6.3 1.6 7.1 1.6 7.1 2 5.3 7 2 7.9 2 7.9 1.7 4.8 6.7 1.7 7.5 1.7 7.5 2.2 6.1 8.1 2.2 9 2.2 9 4 6.4 7.8 4 8.4 4 8.4 3.5 5.5 7.2 3.5 7.6 3.5 7.6 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per latch TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF f = 1 MHz TYP 43 7 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT VCC 50% Input 50% 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VCC Output Waveform 2 S1 at GND (see Note B) 50% 50% 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74AC16244DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC16244 Samples 74AC16244DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC16244 Samples 74AC16244DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC16244 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of