74AC16245DLRG4

54AC16245, 74AC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS235A – MARCH 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebust Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC t (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Thin Shrink Small-Outline (DGG) Package, 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Pin Spacings 54AC16245 . . . WD PACKAGE 74AC16245 . . . DGG OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The ’AC16245 are 16-bit bus transceivers organized as dual-octal noninverting 3-state transceivers designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction control (DIR) input. The output-enable input (OE) can be used to disable the devices so that the buses are effectively isolated. The 74AC16245 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16245 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16245 is characterized for operation from –40°C to 85°C. FUNCTION TABLE CONTROL INPUTS OE OPERATION DIR L L B data to A bus L H A data to bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54AC16245, 74AC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS235A – MARCH 1990 – REVISED APRIL 1996 logic symbol† 1OE 1DIR 48 G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 47 1 1 46 3 5 43 6 41 8 40 9 38 11 37 12 36 13 4 2A3 2A4 2A5 2A6 2A7 2A8 35 1B1 2 44 1 1 2A2 2 1 5 14 33 16 32 17 30 19 29 20 27 22 26 23 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1DIR 1A1 48 2OE 1 2DIR 47 2 1B1 2A1 25 24 36 To Seven Other Transceivers 2 13 To Seven Other Transceivers POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2B1 54AC16245, 74AC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS235A – MARCH 1990 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . 0.85 W DL package . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. recommended operating conditions (see Note 3) 54AC16245 VCC Supply voltage (see Note 4) VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V NOM MAX MIN NOM MAX 3 5 5.5 3 5 5.5 2.1 2.1 3.15 3.15 3.85 3.85 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate 74AC16245 MIN VCC = 4.5 V VCC = 5.5 V 0.9 0.9 1.35 1.65 VCC = 3 V VCC = 4.5 V V 1.65 0 0 VCC VCC –4 –4 –24 –24 VCC = 5.5 V VCC = 3 V –24 –24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 0 V V 1.35 VCC VCC UNIT V V mA mA 24 10 0 10 ns/V TA Operating free-air temperature –55 125 NOTES: 3. All unused pins (input and I/O) must be held high or low to prevent them from floating. 4. All VCC and GND pins must be connected to the proper voltage power supply. –40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54AC16245, 74AC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS235A – MARCH 1990 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH IOH = –4 mA IOH = –24 24 mA VOL TA = 25°C TYP MAX 54AC16245 74AC16245 VCC MIN 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 MIN MAX MIN 5.5 V 5.4 5.4 5.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 MAX V IOH = –75 mA† 5.5 V 3V 0.1 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 IOL = 12 mA IOL = 24 mA UNIT 3V 0.36 0.44 0.44 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 V IOL = 75 mA† 5.5 V 1.65 1.65 II IOZ VI = VCC or GND VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA 5.5 V ±0.5 ±5 ±5 µA ICC Ci VI = VCC or GND, VI = VCC or GND 8 80 80 µA IO = 0 5.5 V 5V 4.5 pF Co VI = VCC or GND 5V 16 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B TA = 25°C MIN TYP MAX 54AC16245 MIN 74AC16245 MAX MIN MAX 2.5 7.6 10.4 2.5 11.9 2.5 11.9 3.1 9 12.3 3.1 13.5 3.1 13.5 2.8 8.6 11.8 2.8 13.2 2.8 13.2 3.9 12 16.2 3.9 18 3.9 18 5.3 8.4 10.4 5.3 11.2 5.3 11.2 4.4 7.7 9.7 4.4 10.3 4.4 10.3 UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B MIN TA = 25°C TYP MAX POST OFFICE BOX 655303 74AC16245 MIN MAX MIN MAX 2 4.6 6.9 2 7.9 2 7.9 2.5 5.2 7.9 2.5 8.9 2.5 8.9 2.3 4.9 7.5 2.3 8.6 2.3 8.6 3 6.2 9.5 3 10.7 3 10.7 5 7.2 9.1 5 9.8 5 9.8 4.2 6.2 8.1 4.2 8.7 4.2 8.7 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 54AC16245 • DALLAS, TEXAS 75265 UNIT ns ns ns 54AC16245, 74AC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS235A – MARCH 1990 – REVISED APRIL 1996 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance per latch Outputs disabled pF CL = 50 pF, TYP 43 f = 1 MHz 8 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND LOAD CIRCUIT Output Control (low-level enabling) VCC 50% 50% 0V tPLH tPHL VOH Output S1 Open 2 × VCC GND 50% 50% 500 Ω CL = 50 pF (see Note A) Input TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC 50% VCC VOL VCC 0V tPZL Output Waveform 2 S1 at GND (see Note B) [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74AC16245DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC16245 Samples 74AC16245DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC16245 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of