74ACT11004DW

74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 D D D D D D DB, DW, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages and Standard Plastic (N) 300-mil DIPs 1Y 2Y 3Y GND GND GND GND 4Y 5Y 6Y 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1A 2A 3A NC VCC VCC NC 4A 5A 6A NC – No internal connection description This device contains six independent inverters. It performs the Boolean function Y = A. The 74ACT11004 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic symbol† 1A 2A 3A 4A 5A 6A 20 1 1 19 2 18 3 13 8 12 9 11 10 1Y 2Y 3Y 4Y 5Y 6Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 logic diagram (positive logic) 1A 20 1 19 2 2A 2Y 18 3 3A 4A 5A 6A 1Y 3Y 13 8 12 9 11 10 4Y 5Y 6Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions 2 MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v Low-level output current TA Operating free-air temperature High-level input voltage 2 High-level output current Input transition rise or fall rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V VCC VCC V –24 mA V 24 mA 0 10 ns/V –40 85 °C 74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 50 mA VOH 24 mA IOH = –24 IOH = –75 mA† II ICC ∆ICC‡ Ci TA = 25°C TYP MAX 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 IOL = 75 mA† VI = VCC or GND 0.1 V 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V 1.65 mA ±0.1 ±1 5.5 V 4 40 mA 5.5 V 0.9 1 mA 5.5 V IO = 0 Other inputs at GND or VCC UNIT 4.8 5.5 V VI = VCC or GND, One input at 3.4 V, MAX 3.85 4.5 V IOL = 24 mA MIN 4.5 V 5.5 V IOL = 50 mA VOL MIN VI = VCC or GND 5V 3.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ns. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y TA = 25°C MIN TYP MAX MIN MAX 1.5 5.3 9 1.5 9.7 1.5 6.4 8.7 1.5 9.6 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per inverter POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 1 MHz TYP 32 UNIT pF 3 74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 PARAMETER MEASUREMENT INFORMATION Input (see Note B) From Output Under Test CL = 50 pF (see Note A) 3V 1.5 V 1.5 V 0V tPHL 500 Ω 50% VCC Output LOAD CIRCUIT tPLH VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74ACT11004DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT11004 Samples 74ACT11004N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 85 74ACT11004N Samples 74ACT11004PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AT004 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of