74ACT11074DRE4

74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 D D D D D D, DB, OR N PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1CLK 1D 1CLR VCC 2CLR 2D 2CLK description This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The 74ACT11074 is characterized for operation from –40°C to 85°C. FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK D Q L H X X H Q L H L X X L H L L X X H{ H{ H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 1 S 14 13 12 2 1Q 3 1Q 6 2Q 5 2Q C1 1D R 7 8 9 10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB package . . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions 2 MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL Dt/Dv Low-level output current TA Operating free-air temperature High-level input voltage 2 High-level output current Input transition rise or fall rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V VCC VCC V –24 mA V 24 mA 0 10 ns/V –40 85 °C 74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 mA VOH 24 mA IOH = –24 IOH = –75 mA† II ICC DICC‡ TA = 25°C TYP MAX 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 IOL = 75 mA† VI = VCC or GND MAX UNIT V 4.8 3.85 4.5 V IOL = 24 mA MIN 4.4 5.5 V IOL = 50 mA VOL MIN 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V V 1.65 5.5 V ±0.1 ±1 mA VI = VCC or GND, IO = 0 5.5 V 4 40 mA One input at 3.4 V, Other inputs at GND or VCC 5.5 V 0.9 1 mA Ci VI = VCC or GND 5V 3.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF timing requirements over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time after CLK↑ 0 MIN MAX UNIT 0 100 MHz 100 PRE or CLR low 5 5 CLK low or high 5 5 Data high or low 4.5 4.5 2 2 0 0 PRE or CLR inactive ns ns ns switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q MIN TA = 25°C TYP MAX MIN MAX 100 125 1.5 5.7 8.9 100 1.5 9.6 1.5 6.6 11.3 1.5 12.5 1.5 6 8.5 1.5 9.4 1.5 5.7 8 1.5 8.8 UNIT MHz ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 1 MHz TYP 30 UNIT pF 3 74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) 3V 500 Ω Input 1.5 V 1.5 V 0V LOAD CIRCUIT VOLTAGE WAVEFORMS 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH 3V Timing Input (see Note B) 1.5 V In-Phase Output 50% VCC 0V th tsu Data Input tPLH tPHL 3V 1.5 V 1.5 V 0V Out-of-Phase Output VOLTAGE WAVEFORMS VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74ACT11074D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT11074 Samples 74ACT11074DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AT074 Samples 74ACT11074N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 74ACT11074N Samples 74ACT11074NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT11074 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of