54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
description
The ’ACT16652 are 16-bit bus transceivers
consisting of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. The devices can be used as two
8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and
OEBA) inputs are provided to control the
transceiver functions. Select-control (SAB and
SBA) inputs are provided to select whether
real-time or stored data is transferred. A low input
level selects real-time data, and a high input level
selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
’ACT16652.
54ACT16652 . . . WD PACAGE
74ACT16652 . . . DL PACKAGE
(TOP VIEW)
1OEAB
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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1
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
The 74ACT16652 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
DATA I/O†
INPUTS
OEAB
OEBA
CLKAB
CLKBA
L
H
L
L
H
↑
X
H
↑
L
H
H
↑
L
X
L
L
L
L
L
OPERATION OR FUNCTION
SAB
SBA
A1–A8
B1–B8
L
X
X
Input
Input
Isolation
↑
X
X
Input
Input
Store A and B data
X
Input
Unspecified‡
Store A, hold B
↑
X
X‡
X
Input
Output
Store A in both registers
↑
X
Unspecified‡
Input
Hold A, store B
↑
↑
X
X
X‡
Output
Input
Store B in both registers
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
L
X
H
X
Input
Output
Stored A data to B bus
H
L
L
L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
2
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• DALLAS, TEXAS 75265
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
OEAB OEBA
L
L
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCAS128C – MARCH 1990 – REVISED APRIL 1996
SBA
L
OEAB OEBA
H
H
OEBA
H
X
H
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
SAB
L
X
X
X
SBA
X
BUS B
BUS A
BUS A
OEAB
X
L
L
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
OEAB
H
OEBA
L
CLKAB
CLKBA
SAB
SBA
L
L
H
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
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3
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
logic symbol†
56
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
1A1
1
55
54
2
EN1 [BA]
EN2 [AB]
C3
G4
C5
3
29
28
30
31
27
26
G6
EN7 [BA]
EN8 [AB]
C9
G10
C11
G12
≥1
5
3D
4
1
52
1B1
4 1
5D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
6
1
6
≥1
2
6
51
8
49
9
48
10
47
12
45
13
44
14
43
≥1
15
10
7
9D
42
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
10 1
11D 12
≥1
8
2A2
2A3
2A4
2A5
2A6
2A7
2A8
16
1 12
40
19
38
20
37
21
36
23
34
24
33
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
41
17
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2B2
2B3
2B4
2B5
2B6
2B7
2B8
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
C1
TG
1A1
1D
5
TG
C1
TG
1D
52
TG
1B1
To Seven Other Channels
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
29
28
30
31
27
26
C1
TG
2A1
1D
15
TG
C1
TG
1D
42
TG
2B1
To Seven Other Channels
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5
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16652
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
2
2
0.8
Input transition rise or fall rate
0
TA
Operating free-air temperature
–55
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
74ACT16652
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
VCC
VCC
0
0
V
10
0
10
ns/V
125
–40
85
°C
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
4.5 V
IOH = –50
50 µA
VOH
24 mA
IOH = –24
IOH = –75 mA†
II
IOZ‡
A or B ports
ICC
Control inputs
54ACT16652
MIN
IO = 0
VI = VCC or GND
VO = VCC or GND
MAX
74ACT16652
MIN
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
5.5 V
4.94
4.8
4.8
3.85
3.85
0.1
0.1
MAX
UNIT
V
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
±1
±1
µA
5.5 V
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
Ci
IOL = 75 mA†
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
TA = 25°C
TYP
MAX
4.5 V
IOL = 24 mA
Control inputs
MIN
5.5 V
IOL = 50 µA
VOL
VCC
V
5.5 V
±0.1
5.5 V
±0.5
±5
±5
µA
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
5V
4
pF
Cio
A or B ports
5V
12
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
0
MIN
MAX
0
90
74ACT16652
MIN
MAX
0
90
UNIT
fclock
tw
Clock frequency
Pulse duration, CLKAB or CLKBA high or low
5.5
5.5
5.5
ns
tsu
th
Setup time, A before CLKAB↑ or B before CLKBA↑
4.5
4.5
4.5
ns
1
1
1
ns
Hold time, A after CLKAB↑ or B after CLKBA↑
90
54ACT16652
MHz
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
90
A or B
B or A
CLKBA or CLKAB
A or B
SBA or SAB
(with A or B high)
A or B
SBA or SAB
(with A or B low)
A or B
OEBA
A
OEBA
A
OEAB
B
OEAB
B
54ACT16652
MIN
74ACT16652
MAX
MIN
90
MAX
90
UNIT
MHz
3.7
7.2
9.4
3.7
10.5
3.7
10.5
3
8.1
10.5
3
11.6
3
11.6
4.5
8.7
11.2
4.5
12.3
4.5
12.3
4.9
8.9
11.3
4.9
12.3
4.9
12.3
4.9
10.4
14.1
4.9
16
4.9
16
4.6
8.4
10.6
4.6
11.7
4.6
11.7
3.9
7.8
10
3.9
11.2
3.9
11.2
5.6
12.3
14.9
5.6
16.9
5.6
16.9
3
8.1
10.5
3
11.7
3
11.7
3.9
9.4
12
3.9
13.4
3.9
13.4
5.3
7.4
8.9
5.3
9.5
5.3
9.5
4.8
6.8
8.6
4.8
9.2
4.8
9.2
4.1
7.7
9.8
4.1
10.8
4.1
10.8
5
9
11
5
12.4
5
12.4
4.4
8.1
10.1
4.4
10.5
4.4
10.5
4.3
7.7
9.7
4.3
9.9
4.3
9.9
ns
ns
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
pF
CL = 50 pF,
f = 1 MHz
TYP
57
13
UNIT
pF
54ACT16652, 74ACT16652
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS128C – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
CL = 50 pF
(see Note A)
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
1.5 V
Input
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
50% VCC
0V
tPZL
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note B)
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
3V
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74ACT16652DL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT16652
Samples
74ACT16652DLR
ACTIVE
SSOP
DL
56
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT16652
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of