74AHC1G126MDCKTEP

SN74AHC1G126-EP www.ti.com SCLS731 – DECEMBER 2013 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT Check for Samples: SN74AHC1G126-EP FEATURES 1 • • • • • Operating Range of 2 V to 5.5 V Max tpd of 6 ns at 5 V Low Power Consumption, 10-μA Max ICC ±8-mA Output Drive at 5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 DCK PACKAGE (TOP VIEW) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • OE 1 A 2 GND 3 5 VCC 4 Y Controlled Baseline One Assembly and Test Site One Fabrication Site Available in Military (–55°C to 125°C) Temperature Range Extended Product Life Cycle Extended Product-Change Notification Product Traceability DESCRIPTION The SN74AHC1G126 is a single bus buffer gate and line driver with 3-state output. The output is disabled when the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION (1) TJ –55°C to 125°C (1) (2) PACKAGE (2) SOT (SC-70) – DCK Reel of 250 ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER 74AHC1G126MDCKTEP SLI V62/14605-01XE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE INPUTS OUTPUT OE A Y H H H H L L L X Z 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated SN74AHC1G126-EP SCLS731 – DECEMBER 2013 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) 1 OE 2 A 4 Y ABSOLUTE MAXIMUM RATINGS (1) over operating junction temperature range (unless otherwise noted) −0.5 V to 7 V VCC Supply voltage range VI Input voltage range (2) VO Output voltage range (2) IIK Input clamp current VI < 0 -20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA −0.5 V to 7 V −0.5 V to VCC + 0.5 V Continuous current through VCC or GND ±50 mA TJ Junction temperature range −55°C to 150°C Tstg Storage temperature range −65°C to 150°C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. THERMAL INFORMATION SN74AHC1G126-EP THERMAL METRIC (1) DCK UNITS 5 PINS θJA Junction-to-ambient thermal resistance (2) 282.8 θJCtop Junction-to-case (top) thermal resistance (3) 91.1 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) 59.2 (7) N/A θJCbot (1) (2) (3) (4) (5) (6) (7) 2 Junction-to-case (bottom) thermal resistance 60.1 1.6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74AHC1G126-EP SN74AHC1G126-EP www.ti.com SCLS731 – DECEMBER 2013 RECOMMENDED OPERATING CONDITIONS (1) MIN VCC Supply voltage VIH MAX 2 High-level input voltage VCC = 2 V 1.5 VCC = 3 V 2.1 VCC = 5.5 V UNIT 5.5 V V 3.85 VCC = 2 V 0.5 VCC = 3 V 0.9 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V -50 µA IOH High-level output current VCC = 5.5 V 1.65 VCC = 2 V VCC = 3.3 V ±0.3 V -4 VCC = 5 V ±0.5 V -8 VCC = 2 V IOL Low-level output current Input transition rise/fall time TJ Operating junction temperature range (1) mA -50 VCC = 3.3 V ±0.3 V 4 VCC = 5 V ±0.5 V 8 VCC = 3.3 V ±0.3 V Δt/Δv V µA mA 100 VCC = 5 V ±0.5 V ns/V 20 –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 μA VOH IOH = −4 mA IOH = −8 mA VCC MIN 2V 1.9 3V 2.9 4.5 V 4.4 3V 2.48 4.5 3.8 MAX V 2V 0.1 3V 0.1 4.5 V 0.1 IOH = 4 mA 3V 0.44 IOH = 8 mA 4.5 0.44 IOH = 50 μA VOL II VI = 5.5 V or GND 0 V to 5.5 V UNIT V ±1 µA IOZ VO = VCC or GND 5.5 V ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 10 µA Ci VI = VCC or GND 5V 10 pF Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74AHC1G126-EP 3 SN74AHC1G126-EP SCLS731 – DECEMBER 2013 www.ti.com SWITCHING CHARACTERISTICS over recommended operating junction temperature range, VCC = 3.3 V ±0.3 V (unless otherwise noted) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 50 pF OE Y OE Y MIN MAX 1 13 ns 1 13 ns 1 13 ns 1 13 ns 1 15 ns 1 15 ns CL = 50 pF CL = 50 pF UNIT SWITCHING CHARACTERISTICS over recommended operating junction temperature range, VCC = 5 V ±0.5 V (unless otherwise noted) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 50 pF OE Y CL = 50 pF OE Y MIN MAX 1 8.5 ns 1 8.5 ns 1 8 ns 1 8 ns 1 10 ns 1 10 ns CL = 50 pF UNIT OPERATING CHARACTERISTICS VCC = 5 V, TJ = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz Submit Documentation Feedback TYP 14 UNIT pF Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74AHC1G126-EP SN74AHC1G126-EP www.ti.com SCLS731 – DECEMBER 2013 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 Open VCC GND VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw VCC Input 50% VCC 50% VCC 0V th tsu VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control VOL + 0.3 V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74AHC1G126-EP 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74AHC1G126MDCKTEP ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SLI V62/14605-01XE ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SLI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of