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74ALVC164245ZRDR

74ALVC164245ZRDR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    JRBGA54

  • 描述:

    IC TRANSCVR TRI-ST 16BIT 54BGA

  • 数据手册
  • 价格&库存
74ALVC164245ZRDR 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 SN74ALVC164245 16-Bit 2.5-V to 3.3-V or 3.3-V to 5-V Level-Shifting Transceiver With 3State Outputs 1 Features 3 Description • This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa. 1 • • • • Member of the Texas Instruments Widebus™ Family Maximum tpd of 5.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage Latch-Up Performance Exceeds 250 mA Per JESD 17 The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA. 2 Applications • • • • • To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. Electronic Points of Sale Printers and Other Peripherals Motor Drives Wireless and Telecom Infrastructures Wearable Health and Fitness Devices The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. Device Information(1) PART NUMBER SN74ALVC164245 PACKAGE BODY SIZE (NOM) TSSOP (48) 12.50 mm × 6.10 mm SSOP (48) 15.88 mm × 7.49 mm BGA MICROSTAR JUNIOR (56) 7.00 mm × 4.50 mm BGA MICROSTAR JUNIOR (54) 8.00 mm × 5.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 To Seven Other Channels 24 2OE 36 13 1B1 2B1 To Seven Other Channels Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 7 6.1 Absolute Maximum Ratings ..................................... 7 6.2 ESD Ratings.............................................................. 7 6.3 Recommended Operating Conditions: VCCB at 3.3 V................................................................................. 7 6.4 Recommended Operating Conditions: VCCA at 2.5 V ................................................................................... 8 6.5 Thermal Information .................................................. 8 6.6 Electrical Characteristics: VCCA = 2.7 V to 3.6 V ...... 9 6.7 Electrical Characteristics: VCCA = 2.3 V to 2.7 V .... 10 6.8 Switching Characteristics ........................................ 10 6.9 Operating Characteristics........................................ 10 6.10 Typical Characteristics .......................................... 11 7 Parameter Measurement Information ................ 12 7.1 7.2 7.3 7.4 VCCA = 2.5 V ± 0.2 V to VCCB = 3.3 V ± 0.3 V ........ 12 VCCB = 3.3 V ± 0.3 V to VCCA = 2.5 V ± 0.2 V ........ 13 VCCA = 3.3 V ± 0.3 V to VCCB = 5 V ± 0.5 V ........... 14 VCCB = 5 V ± 0.5 V to VCCA = 2.7 V and 3.3 V ± 0.3 V............................................................................... 15 8 Detailed Description ............................................ 16 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 16 16 Application and Implementation ........................ 17 9.1 Application Information............................................ 17 9.2 Typical Application ................................................. 17 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 19 11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History Changes from Revision P (November 2005) to Revision Q Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1 • Changed values in the Thermal Information table to align with JEDEC standards................................................................ 8 2 Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 5 Pin Configuration and Functions DGG and DL Packages 48-Pin TSSOP and BGA MICROSTAR JUINIOR Top View 1DIR 1B1 1B2 GND 1B3 1B4 (3.3 V, 5 V) VCCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 (3.3 V, 5 V) VCCB 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCCA (2.5 V, 3.3 V) 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCCA (2.5 V, 3.3 V) 2A5 2A6 GND 2A7 2A8 2OE Pin Functions PIN NO. NAME I/O DESCRIPTION 1 1DIR — Direction Pin 1 2 1B1 I/O 1B1 input or output 3 1B2 I/O 1B2 input or output 4 GND — Ground pin 5 1B3 I/O 1B3 input or output 6 1B4 I/O 1B4 input or output 7 VCCB (3.3 V, 5 V) — Power pin 8 1B5 I/O 1B5 input or output 9 1B6 I/O 1B6 input or output 10 GND — Ground pin 11 1B7 I/O 1B7 input or output 12 1B8 I/O 1B8 input or output 13 2B1 I/O 2B1 input or output 14 2B2 I/O 2B2 input or output 15 GND — Ground pin 16 2B3 I/O 2B3 input or output Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 3 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION 17 2B4 I/O 2B4 input or output 18 VCCB (3.3 V, 5 V) — Power pin 19 2B5 I/O 2B5 input or output 20 2B6 I/O 2B6 input or output 21 GND — Ground pin 22 2B7 I/O 2B7 input or output 23 2B8 I/O 2B8 input or output 24 2DIR — Direction pin 2 25 2OE I 26 2A8 I/O 2A8 input or output 27 2A7 I/O 2A7 input or output 28 GND — Ground pin 29 2A6 I/O 2A6 input or output 30 2A5 I/O 2A5 input or output 31 VCCA (2.5 V, 3.3 V) — Power pin 32 2A4 I/O 2A4 input or output 33 2A3 I/O 2A3 input or output 34 GND — Ground pin 35 2A2 I/O 2A2 input or output 36 2A1 I/O 2A1 input or output 37 1A8 I/O 1A8 input or output 38 1A7 I/O 1A7 input or output 39 GND — Ground pin 40 1A6 I/O 1A6 input or output 41 1A5 I/O 1A5 input or output 42 VCCA (2.5 V, 3.3 V) — Power pin 43 1A4 I/O 1A4 input or output 44 1A3 I/O 1A3 input or output 45 GND — Ground pin 46 1A2 I/O 1A2 input or output 47 1A1 I/O 1A1 input or output 48 1OE I 4 Output Enable 2 Output Enable 1 Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 1 2 3 4 5 6 A B C D E F G H J K Table 1. Pin Assignments (1) (56-Ball GQL or ZQL Package) (1) 1 2 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCCB VCCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 — — 1A7 1A8 F 2B1 2B2 — — 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 VCCB VCCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE NC – No internal connection Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 5 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 1 2 3 4 5 6 A B C D E F G H J Table 2. Pin Assignments (1) (54-Ball GRD or ZRD Package) (1) 6 1 2 3 4 5 6 A 1B1 NC 1DIR 1OE NC 1A1 B 1B3 1B2 NC NC 1A2 1A3 C 1B5 1B4 VCCB VCCA 1A4 1A5 D 1B7 1B6 GND GND 1A6 1A7 E 2B1 1B8 GND GND 1A8 2A1 F 2B3 2B2 GND GND 2A2 2A3 G 2B5 2B4 VCCB VCCA 2A4 2A5 H 2B7 2B6 NC NC 2A6 2A7 J 2B8 NC 2DIR 2OE NC 2A8 NC – No internal connection Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range for VCCB at 5 V and VCCA at 3.3 V (unless otherwise noted) (1) VCC Supply voltage VI Input voltage MIN MAX VCCA –0.5 4.6 VCCB –0.5 6 Except I/O ports (2) –0.5 6 I/O port A (3) –0.5 VCCA + 0.5 (2) –0.5 VCCB + 0.5 I/O port B UNIT V V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through each VCC or GND ±100 mA 150 °C Tstg (1) (2) (3) Storage temperature –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This value is limited to 6 V maximum. This value is limited to 4.6 V maximum. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions: VCCB at 3.3 V for VCCB at 3.3 V and 5 V (1) MIN MAX 5.5 VCCB Supply voltage 3 VIH High-level input voltage 2 UNIT V V VCCB = 3 V to 3.6 V 0.7 VCCB = 4.5 V to 5.5 V 0.8 VIL Low-level input voltage VIB Input voltage 0 VCCB VOB Output voltage 0 VCCB V IOH High-level output current –24 mA IOL Low-level output current 24 mA Δt/Δv Input transition rise or fall rate 10 ns/V TA Operating free-air temperature 85 °C (1) –40 V V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. see the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 7 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 6.4 Recommended Operating Conditions: VCCA at 2.5 V for VCCA at 2.5 V and 3.3 V (1) VCCA Supply voltage VCCA = 2.3 V to 2.7 V MIN MAX 2.3 3.6 1.7 UNIT V VIH High-level input voltage VIL Low-level input voltage VIA Input voltage 0 VCCA V VOA Output voltage 0 VCCA V IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) VCCA = 3 V to 3.6 V V 2 VCCA = 2.3 V to 2.7 V 0.7 VCCA = 3 V to 3.6 V 0.8 VCCA = 2.3 V –18 VCCA = 3 V –24 VCCA = 2.3 V 18 VCCA = 3 V 24 –40 V mA mA 10 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, (SCBA004). 6.5 Thermal Information SN74ALVC164245 THERMAL METRIC (1) DGG (TSSOP) DL (SSOP) ZQL (BGA MICROSTAR JUNIOR) ZRD (BGA MICROSTAR JUNIOR) 48 PINS 48 PINS 56 PINS 54 PINS UNIT RθJA Junction-to-ambient thermal resistance 60.7 63.6 54.5 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 14.3 30.1 19.1 17.9 °C/W RθJB Junction-to-board thermal resistance 27.7 36.2 21.7 20.2 °C/W ψJT Junction-to-top characterization parameter 0.5 8.1 0.5 0.5 °C/W ψJB Junction-to-board characterization parameter 27.6 35.6 21.7 19.9 °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 6.6 Electrical Characteristics: VCCA = 2.7 V to 3.6 V over recommended operating free-air temperature range for VCCA = 2.7 V to 3.6 V and VCCB = 4.5 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA B to A IOH = –12 mA 2.2 2.4 3V 2 IOH = –24 mA A to B Control inputs II IOZ (2) MAX 4.5 V 4.3 5.5 V 5.3 4.5 V 3.7 5.5 V 4.7 2.7 V to 3.6 V 0.2 IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 IOL = 100 µA 4.5 V to 5.5 V 0.2 IOL = 24 mA 4.5 V to 5.5 V 0.55 VI = VCCA/VCCB or GND A or B port VO = VCCA/VCCB or GND VI = VCCA/VCCB or GND, IO = 0 ΔICC (3) One input at VCCA/VCCB – 0.6 V, Other inputs at VCCA/VCCB or GND Ci Control inputs Cio A or B port VO = VCCA/VCCB or GND VI = VCCA/VCCB or GND UNIT V IOL = 100 µA ICC (1) (2) (3) TYP (1) VCC – 0.2 3V A to B VOL MIN 2.7 V IOH = –100 µA B to A VCCB 2.7 V to 3.6 V IOH = –24 mA VOH VCCA V 3.6 V 5.5 V ±5 µA 3.6 V 5.5 V ±10 µA 3.6 V 5.5 V 40 µA 3 V to 3.6 V 4.5 V to 5.5 V 750 µA 3.3 V 5V 6.5 pF 3.3 V 3.3 V 8.5 pF Typical values are measured at VCCA = 3.3 V and VCCB = 5 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the supply current increase for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated VCC. Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 9 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 6.7 Electrical Characteristics: VCCA = 2.3 V to 2.7 V over recommended operating free-air temperature range for VCCA = 2.3 V to 2.7 V and VCCB = 3 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB 2.3 V to 2.7 V 3 V to 3.6 V VCCA – 0.2 IOH = –8 mA 2.3 V 3 V to 3.6 V 1.7 IOH = –12 mA 2.7 V 3 V to 3.6 V 1.8 IOH = –100 µA 2.3 V to 2.7 V 3 V to 3.6 V VCCB – 0.2 IOH = –18 mA 2.3 V to 2.7 V 3V IOL = 100 µA 2.3 V to 2.7 V 3 V to 3.6 V 0.2 IOL = 12 mA 2.3 V 3 V to 3.6 V 0.6 IOL = 100 µA 2.3 V to 2.7 V 3 V to 3.6 V 0.2 IOL = 18 mA 2.3 V 3V 0.55 IOH = –100 µA B to A VOH A to B B to A VOL A to B MIN MAX UNIT V 2.2 V II Control inputs VI = VCCA/VCCB or GND 2.3 V to 2.7 V 3 V to 3.6 V ±5 µA IOZ (1) A or B port VO = VCCA/VCCB or GND 2.3 V to 2.7 V 3 V to 3.6 V ±10 µA VI = VCCA/VCCB or GND, IO = 0 2.3 V to 2.7 V 3 V to 3.6 V 20 µA One input at VCCA/VCCB – 0.6 V, Other inputs at VCCA/VCCB or GND 2.3 V to 2.7 V 3 V to 3.6 V 750 µA ICC ΔICC (1) (2) (2) For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated VCC. 6.8 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5) VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V FROM (INPUT) TO (OUTPUT) MAX MIN MAX A B 7.6 5.9 1 5.8 B A 7.6 6.7 1.2 5.8 ten OE B 11.5 9.3 1 8.9 ns tdis OE B 10.5 9.2 2.1 9.5 ns ten OE A 12.3 10.2 2 9.1 ns tdis OE A 9.3 9 2.9 8.6 ns PARAMETER VCCA = 2.5 V ± 0.2 V MIN tpd VCCA = 3.3 V ± 0.3 V VCCA = 2.7 V MAX MIN UNIT ns 6.9 Operating Characteristics TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled (B) Cpd Power dissipation capacitance Outputs disabled (B) Outputs enabled (A) Outputs disabled (A) 10 CL = 50 pF, f = 10 MHz CL = 50 pF, f = 10 MHz Submit Documentation Feedback VCCB = 3.3 V VCCB = 5 V VCCA = 2.5 V VCCA = 3.3 V TYP TYP 55 56 27 6 118 56 58 6 UNIT pF Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 6.10 Typical Characteristics 2.85 2.7 VOH (V) 2.55 2.4 2.25 2.1 1.95 -24 -20 -16 -12 IOH (mA) -8 -4 0 D001 Figure 1. VOH vs IOH Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 11 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 7 Parameter Measurement Information 7.1 VCCA = 2.5 V ± 0.2 V to VCCB = 3.3 V ± 0.3 V VCCB = 6 V 500 W From Output Under Test S1 Open GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VCCB = 6 V GND 500 W LOAD CIRCUIT VCCA Output Control (low-level enabling) VCCA/2 0V tPZL VCCA Input VCCA/2 VCCA/2 0V tPLH tPHL VOHB Output 1.5 V 1.5 V VOLB tPLZ VCCB Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VCCA/2 1.5 V VOL + 0.3 V VOLB tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHZ 1.5 V VOH − 0.3 V VOHB 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 W, t r ≤2 ns, t f ≤2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as t dis. F. t PZL and tPZH are the same as t en. G. tPLH and tPHL are the same as t pd. Figure 2. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 7.2 VCCB = 3.3 V ± 0.3 V to VCCA = 2.5 V ± 0.2 V 2 × VCCA S1 500 W From Output Under Test Open GND CL = 30 pF (see Note A) 500 W TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCA GND LOAD CIRCUIT Output Control (low-level enabling) 2.7 V 1.5 V 0V tPLZ tPZL 2.7 V 1.5 V Input 1.5 V 0V tPLH VCCA/2 VCCA VCCA/2 VCCA/2 VOLA Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOLA tPHZ tPZH VOHA Output Output Waveform 1 S1 at 2 × VCCA (see Note B) tPHL 1.5 V VCCA/2 VOHA VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 W, tr ≤2 ns, t f ≤2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 13 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 7.3 VCCA = 3.3 V ± 0.3 V to VCCB = 5 V ± 0.5 V 2 ´ VCCB S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 ´ VCCB GND 500 Ω 2.7 V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPLZ tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH 50% VCCB ≈VCCB 50% VCCB 50% VCCB VOL 20% VCCB VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 2 ´ VCCB (see Note B) tPHL 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 50% VCCB 80% VCCB VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, t f ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 14 Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 7.4 VCCB = 5 V ± 0.5 V to VCCA = 2.7 V and 3.3 V ± 0.3 V S1 500 Ω From Output Under Test VCCA = 6 V TEST S1 Open tpd tPLZ/tPZL tPHZ/tPZH Open VCCA = 6 V GND GND CL = 50 pF (see Note A) 500 Ω 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V ≈3 V 1.5 V 1.5 V VOLA tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOLA tPZH VOHA Output Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V VOH − 0.3 V VOHA 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 15 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The SN74ALVC16245 device is designed for asynchronous communication between data buses. The controlfunction implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment. 8.2 Functional Block Diagram 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels Copyright © 2016, Texas Instruments Incorporated Figure 6. Logic Diagram (Positive Logic) 8.3 Feature Description The SN74ALVC164245 can output 24 mA drive at 3.3V VCC. This device allows down voltage translations and accepts input voltages to VCC + 0.5V. This device is useful for high-speed applications because of the low tpd. 8.4 Device Functional Modes Table 3 lists the functions of the device. Table 3. Function Table (1) (Each 8-Bit Section) CONTROL INPUTS OE (1) 16 OUTPUT CIRCUITS B PORT OPERATION DIR A PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os always are active. Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74ALVC16245 device is a 16-bit bidirectional transceiver. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. This allows it to be used in multi-power systems and for down translation as well. 9.2 Typical Application Regulated 3.6 V OE VCC DIR A1 uC or System Logic A8 B1 B8 uC System Logic LEDs GND Figure 7. Typical Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads; therefore, routing and load conditions must be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs: See (Δt/ΔV) in Recommended Operating Conditions: VCCB at 3.3 V. – Specified high and low levels: See (VIH and VIL) in Recommended Operating Conditions: VCCB at 3.3 V. 2. Recommend Output Conditions – Load currents should not exceed 50 mA per output and 100 mA total for the part. – Outputs should not be pulled above VCC. Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 17 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com Typical Application (continued) 9.2.3 Application Curve 0.55 0.5 VOL (V) 0.45 0.4 0.35 0.3 0.25 0.2 1 PA 5mA 10 mA 15 mA 20 mA IOL 24 mA D001 Figure 8. VOH vs IOH 18 Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 SN74ALVC164245 www.ti.com SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 10 Power Supply Recommendations TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence must always be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems: 1. Connect ground before any supply voltage is applied. 2. Power up the control side of the device (VCCA for all four of these devices). 3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, keep DIR low. For more information, see the TI application report, Texas Instruments Voltage-Level-Translation Devices (SCEA021). 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in the Figure 9 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 11.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 9. Layout Diagram Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 19 SN74ALVC164245 SCAS416Q – MARCH 1994 – REVISED SEPTEMBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments Voltage-Level-Translation Devices (SCEA021) • Implications of Slow or Floating CMOS Inputs (SCBA004) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks Widebus, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 1994–2016, Texas Instruments Incorporated Product Folder Links: SN74ALVC164245 PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) 74ALVC164245DGGRE4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 74ALVC164245DGGRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 74ALVC164245DGGTE4 ACTIVE TSSOP DGG 48 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 74ALVC164245DGGTG4 ACTIVE TSSOP DGG 48 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 74ALVC164245DLG4 ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 74ALVC164245DLRG4 ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 SN74ALVC164245DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-1-260C-UNLIM SN74ALVC164245DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 SN74ALVC164245DGGT ACTIVE TSSOP DGG 48 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 SN74ALVC164245DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 SN74ALVC164245DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC164245 ALVC164245 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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