74ALVCH16282DBBRG4

SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 D D D D D D DBB PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Thin Very Small-Outline Package VCC GND 2B9 1B9 2B8 GND 1B8 2B7 1B7 VCC 2B6 1B6 2B5 1B5 GND 2B4 1B4 2B3 1B3 VCC GND 2B2 1B2 2B1 1B1 VCC A1 A2 A3 GND A4 A5 A6 VCC A7 A8 A9 GND CLK SEL NOTE: For tape and reel order entry: The DBBR package is abbreviated to GR. description The SN74ALVCH16282 is an 18-bit to 36-bit registered bus exchanger designed for 1.65-V to 3.6-V VCC operation. This device is intended for use in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. It is designed specifically for low-voltage (3.3-V) VCC operation. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input. For data transfer in the B-to-A direction, the select (SEL) input selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the 1B path, with a single storage register in the 2B path. Data flow is controlled by the active-low output enable (OE) and the DIR input. The DIR control pin is registered to synchronize the bus direction changes with the clock. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 33 48 34 47 35 46 36 45 37 44 38 43 39 42 40 41 VCC GND 1B10 2B10 1B11 GND 2B11 1B12 2B12 VCC 1B13 2B13 1B14 2B14 GND 1B15 2B15 1B16 2B16 VCC GND 1B17 2B17 1B18 2B18 VCC A18 A17 A16 GND A15 A14 A13 VCC A12 A11 A10 GND OE DIR The SN74ALVCH16282 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments. Copyright  2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 Function Tables A-TO-B STORAGE (OE = L, DIR = H) OUTPUTS INPUTS SEL CLK A H X X L ↑ L 1B 1B0† 2B 2B0† L‡ H‡ X L ↑ H X † Output level before indicated steady-state input conditions were established ‡ Two CLK edges are needed to propagate the data. B-TO-A STORAGE (OE = L, DIR = L) INPUTS OUTPUT A CLK SEL 1B 2B ↑ H X L ↑ H X H ↑ L L X L ↑ L H X H L§ H§ § Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and propagates to the second register when SEL is high. OUTPUT ENABLE INPUTS 2 OUTPUTS CLK OE DIR A ↑ H X Z Z ↑ L H Z Active ↑ L L Active Z POST OFFICE BOX 655303 1B, 2B • DALLAS, TEXAS 75265 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 logic diagram (positive logic) CLK SEL OE 39 40 42 CE C1 DIR 41 1D 25 1 of 18 Channels 1B1 G1 CE C1 A1 27 C1 1 1D 1D 1 24 2B1 CE C1 C1 1D 1D CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH Low-level input voltage MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 0 0 IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V V 0.8 Output voltage VCC = 2.7 V VCC = 3 V V 1.7 Input voltage High level output current High-level V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V VCC = 2.3 V UNIT VCC VCC V V –4 –12 –12 mA –24 4 12 12 mA 24 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA IOL = 4 mA IOL = 6 mA VOL IOZ§ ICC ∆ICC Ci 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 UNIT V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V ±5 VI = 0.58 V VI = 1.07 V 1.65 V 25 1.65 V –25 VI = 0.7 V VI = 1.7 V 2.3 V 45 2.3 V –45 VI = 0.8 V VI = 2 V 3V 75 3V –75 V µA µA VI = 0 to 3.6 V‡ 3.6 V ±500 VO = VCC or GND VI = VCC or GND, 3.6 V ±10 µA 3.6 V 40 µA 750 µA One input at VCC – 0.6 V, Control inputs MAX VCC–0.2 1.2 1.65 V IOL = 24 mA VI = VCC or GND II(hold) ( ) TYP† 1.65 V to 3.6 V IOL = 12 mA II MIN IO = 0 Other inputs at VCC or GND 3 V to 3.6 V VI = VCC or GND VO = VCC or GND 3.3 V 4 pF Cio A or B ports 3.3 V 8.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw Clock frequency Setup time th Hold time MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 A data before CLK↑ † 2.4 2.3 2 B data before CLK↑ † 2.2 2.2 1.8 DIR before CLK↑ † 2.2 2.1 1.7 SEL before CLK↑ † 2 2 1.8 A data after CLK↑ † 0.5 0.5 0.7 B data after CLK↑ † 0.5 0.5 0.6 DIR after CLK↑ † 0.5 0.5 0.5 † 0.7 0.7 0.8 SEL after CLK↑ † This information was not available at the time of publication. UNIT MAX 150 † Pulse duration, CLK high or low tsu MAX † VCC = 2.5 V ± 0.2 V MHz ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d CLK ten OE tdis di OE VCC = 1.8 V MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz A † 1 6.1 5.5 1.4 5 B † 1.2 6.3 5.7 1.6 5.3 A † 1.3 6.9 6.3 1.2 5.7 B † 2.3 8.7 8.1 2.3 7.4 A † 1.5 7 5.6 1.8 5.7 B † 2.1 7.9 6.4 2.3 6.4 ns ns ns † This information was not available at the time of publication. operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0 0, VCC = 1.8 V TYP † f = 10 MHz † This information was not available at the time of publication. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 † VCC = 2.5 V TYP VCC = 3.3 V TYP 282 310 208 228 UNIT pF SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036D – JULY 1995 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V tPZH tPHL 1.5 V VOL 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MECHANICAL DATA MTSS005D – JANUARY 1995 – REVISED MARCH 2002 DBB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 80 PINS SHOWN 0,23 0,13 0,40 80 0,07 M 41 6,20 6,00 8,30 7,90 0,20 0,09 1 Gage Plane 40 A 0,25 0°–ā8° 0,75 0,45 Seating Plane 1,20 MAX 0,15 0,05 PINS** 0,08 80 100 A MAX 17,10 20,90 A MIN 16,90 20,70 DIM 4040212 / E 03/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC : 80 Pin – MO-153 Variation FF 100 Pin – MO-194 Variation BB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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