SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
•
•
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
UBE™ (Universal Bus Exchanger) Allows
Synchronous Data Exchange
Operates From 1.65 V to 3.6 V
Max tpd of 5.1 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
PRE
SEL0
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
SEL1
SEL2
DESCRIPTION/ORDERING INFORMATION
This 9-bit, 4-port universal bus exchanger is designed
for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16409 allows synchronous data
exchange between four different buses. Data flow is
controlled by the select (SEL0–SEL4) inputs. A
data-flow state is stored on the rising edge of the
clock (CLK) input if the select-enable (SELEN) input
is low. Once a data-flow state has been established,
data is stored in the flip-flop on the rising edge of
CLK if SELEN is high.
The data-flow control logic is designed to allow
glitch-free data transmission.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
SELEN
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
SEL4
SEL3
When preset (PRE) transitions high, the outputs are
disabled immediately, without waiting for a clock
pulse. To leave the high-impedance state, both PRE
and SELEN must be low, and a clock pulse must be
applied.
To ensure the high-impedance state during power up or power down, PRE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
PACKAGE (1)
TA
-40°C to 85°C
SSOP - DL
TSSOP - DGG
(1)
ORDERABLE PART NUMBER
Tube
SN74ALVCH16409DL
Tape and reel
SN74ALVCH16409DLR
Tape and reel
SN74ALVCH16409DGGR
TOP-SIDE MARKING
ALVCH16409
ALVCH16409
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBE are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
FUNCTION TABLES
INPUTS
(1)
CLK
SEND PORT
OUTPUT
RECEIVE PORT
X
X
B0 (1)
X
L
L
X
H
H
↑
L
L
↑
H
H
H
X
B0 (1)
L
X
B0 (1)
Output level before the indicated steady-state input conditions were
established
DATA-FLOW CONTROL
INPUTS
PRE
2
DATA FLOW
SELEN
CLK
SEL0
SEL1
SEL2
SEL3
SEL4
H
X
X
X
X
X
X
X
All outputs disabled
L
H
↑
X
X
X
X
X
No change
L
L
↑
0
0
0
0
0
None, all I/Os off
L
L
↑
0
0
0
0
1
Not used
L
L
↑
0
0
0
1
0
Not used
L
L
↑
0
0
0
1
1
Not used
L
L
↑
0
0
1
0
0
Not used
L
L
↑
0
0
1
0
1
Not used
L
L
↑
0
0
1
1
0
Not used
L
L
↑
0
0
1
1
1
Not used
L
L
↑
0
1
0
0
0
2A to 1A and 1B to 2B
L
L
↑
0
1
0
0
1
2A to 1A
L
L
↑
0
1
0
1
0
2B to 1B
L
L
↑
0
1
0
1
1
2A to 1A and 2B to 1B
L
L
↑
0
1
1
0
0
1A to 2A and 1B to 2B
L
L
↑
0
1
1
0
1
1A to 2A
L
L
↑
0
1
1
1
0
1B to 2B
L
L
↑
0
1
1
1
1
1A to 2A and 2B to 1B
L
L
↑
1
0
0
0
0
1A to 1B and 2B to 2A
L
L
↑
1
0
0
0
1
1A to 1B
L
L
↑
1
0
0
1
0
2A to 2B
L
L
↑
1
0
0
1
1
1A to 1B and 2A to 2B
L
L
↑
1
0
1
0
0
1B to 1A and 2A to 2B
L
L
↑
1
0
1
0
1
1B to 1A
L
L
↑
1
0
1
1
0
2B to 2A
L
L
↑
1
0
1
1
1
1B to 1A and 2B to 2A
L
L
↑
1
1
0
0
0
2B to 1A and 2A to 1B
L
L
↑
1
1
0
0
1
1B to 2A
L
L
↑
1
1
0
1
0
2B to 1A
L
L
↑
1
1
0
1
1
2B to 1A and 1B to 2A
L
L
↑
1
1
1
0
0
1A to 2B and 1B to 2A
L
L
↑
1
1
1
0
1
1A to 2B
L
L
↑
1
1
1
1
0
2A to 1B
L
L
↑
1
1
1
1
1
1A to 2B and 2A to 1B
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK
SELEN
56
1
PRE
55
28
SEL2
2
29
SEL0
SEL1
SEL3
Flow and Storage Control
27
30
SEL4
3
3
2Ax 1Ax
CLK
D
1A
1Ax
CLK
D
2A
CLK
D
1Bx 2Ax
2Bx 2Bx
3
1B
3
1Ax
1Ax
1Bx
2Bx
2Ax
1Bx
2Ax
1Bx
CLK
D
2B
2Bx
One of Nine Channels
3
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
-0.5
4.6
Except I/O ports (2)
-0.5
4.6
I/O ports (2) (3)
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
DGG package
64
DL package
56
-65
150
V
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2.7 V to 3.6 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
0.8
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
V
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
IOL = 24 mA
II(hold)
1.2
IOL = 4 mA
IOL = 12 mA
2.7 V
0.4
3V
0.55
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 2 V
UNIT
VCC - 0.2
1.65 V
IOH = -12 mA
II
1.65 V to 3.6 V
MIN TYP (1) MAX
IOH = -4 mA
VOH
VOL
VCC
V
µA
µA
3.6 V
±500
IOZ (3)
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND, IO = 0
3.6 V
40
µA
∆ICC
One input at VCC - 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
750
µA
VI = 0 to 3.6
V (2)
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
8
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
5
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
MIN
Clock frequency
tw
Pulse duration, CLK high or low
th
(1)
MAX
MIN
Setup time
Hold time
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
(1)
fclock
tsu
VCC = 2.5 V
± 0.2 V
MIN
MAX
120
MIN
120
120
(1)
4.2
4.2
3
A or B before CLK↑
(1)
1.9
1.9
1.4
SEL before CLK↑
(1)
5.1
4.2
3.5
SELEN before CLK↑
(1)
2.5
2.5
1.8
PRE before CLK↑
(1)
1
1
0.7
A or B after CLK↑
(1)
0.8
0.8
1
SEL after CLK↑
(1)
0
0
0
SELEN after CLK↑
(1)
0.5
0.5
0.8
UNIT
MAX
MHz
ns
ns
ns
This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.8 V
TYP
(1)
fmax
MIN
MAX
120
VCC = 2.7 V
MIN
MAX
120
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
120
MHz
tpd
CLK
A or B
(1)
1.5
6
5.7
1.5
5.1
ns
ten
CLK
A or B
(1)
2.4
6.9
6.3
2
5.7
ns
(1)
2.3
7.1
6
2
5.7
(1)
2.8
7.5
6.5
2.5
6.1
CLK
tdis
(1)
MIN
VCC = 2.5 V
± 0.2 V
PRE
A or B
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
6
Power dissipation
capacitance
per exchanger
TEST CONDITIONS
All outputs enabled
All outputs disabled
CL = 50 pF,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
60
60
(1)
60
60
UNIT
pF
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
TIMING DIAGRAM
CLK
tsu
th
SELEN
tsu
SEL(0−4)
th
tsu
Selected
Input Port
Selected
Output Port
th
tpd
CLK to Output
7
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G – JULY 1995 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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