www.ti.com
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
FEATURES
•
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Checks Parity
Able to Cascade With a Second
SN74ALVCH16903
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
This 12-bit universal bus driver is designed for 2.3-V
to 3.6-V VCC operation.
The SN74ALVCH16903 has dual outputs and can
operate as a buffer or an edge-triggered register. In
both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies.
The YERR output, which is produced one cycle after
APAR, is open drain.
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OE
1Y1
1Y2
GND
2Y1
2Y2
VCC
3Y1
3Y2
4Y1
GND
4Y2
5Y1
5Y2
6Y1
6Y2
7Y1
GND
7Y2
8Y1
8Y2
VCC
9Y1
9Y2
GND
10Y1
10Y2
PAROE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
1A
11A/YERREN
GND
11Y1
11Y2
VCC
2A
3A
4A
GND
12A
12Y1
12Y2
5A
6A
7A
GND
APAR
8A
YERR
VCC
9A
MODE
GND
10A
PARI/O
CLKEN
MODE selects one of the two data paths. When
MODE is low, the device operates as an
edge-triggered register. On the positive transition of
the clock (CLK) input and when the clock-enable
(CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of
CLK and when CLKEN is high, only data set up at the 9A–12A inputs is stored in their internal registers. When
MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs.
11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into
the YERR output register.
When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output
(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and
PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used
in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.
A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operation of the device. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
DESCRIPTION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16903 is characterized for operation from 0°C to 70°C.
FUNCTION TABLES
FUNCTION
INPUTS
(1)
OUTPUTS
OE
MODE
CLKEN
CLK
A
1Yn (1)–8Yn (1)
9Yn (1)–12Yn (1)
L
L
L
↑
H
H
H
L
L
L
↑
L
L
L
L
L
H
↑
H
Y0
H
L
L
H
↑
L
Y0
L
L
H
X
X
H
H
H
L
H
X
X
L
L
L
H
X
X
X
X
Z
Z
n = 1 or 2
PARITY FUNCTION
INPUTS
OE
(1)
(2)
PAROE
(1)
11A/YERREN (2)
PARI/O
Σ OF INPUTS
1A–10A = H
APAR
OUTPUT
YERR
0, 2, 4, 6, 8, 10
L
H
L
L
H
L
L
L
H
L
L
1, 3, 5, 7, 9
L
L
H
L
L
0, 2, 4, 6, 8, 10
H
L
L
H
L
L
1, 3, 5, 7, 9
H
H
L
H
L
H
0, 2, 4, 6, 8, 10
L
L
L
H
L
H
1, 3, 5, 7, 9
L
H
L
H
L
H
0, 2, 4, 6, 8, 10
H
H
L
H
L
H
1, 3, 5, 7, 9
H
L
H
X
X
X
X
X
H
L
X
H
X
X
X
H
When used as a single device, PAROE must be tied high.
Valid after appropriate number of clock pulses have set internal register
PARI/O FUNCTION (1)
INPUTS
(1)
2
PAROE
Σ OF INPUTS
1A–10A = H
APAR
OUTPUT
PARI/O
L
0, 2, 4, 6, 8, 10
L
L
L
1, 3, 5, 7, 9
L
H
L
0, 2, 4, 6, 8, 10
H
H
L
1, 3, 5, 7, 9
H
L
H
X
X
Z
This table applies to the first device of a cascaded pair of
SN74ALVCH16903 devices.
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
MODE
CLK
1
33
13
1A−12A,
APAR
(1A−12A)
12
13
1Y2−12Y2
13
CLKEN
1Y1−12Y1
12
56
29
(1A−8A)
8
13
12
(1A−11A/YERREN, APAR)
D
11A/YERREN
Q
Flip-Flop
11
5
(9A−12A, APAR)
APAR
5
APAR
Flip-Flop
D
Q
D
Q
10
(1A−10A)
Parity
Check
36
XOR
D
Q
YERR
30
PARI/O
PAROE
28
3
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
4.6
V
VI
Input voltage range (2)
-0.5
4.6
V
VO
Output voltage range (2) (3)
-0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
(1)
(2)
(3)
(4)
mA
-50
mA
±50
mA
±100
mA
DGG package
81
DGV package
86
DL package
74
Storage temperature range
-65
V
-50
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS (1)
MIN
MAX
2.3
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
IOH
High-level output current
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 2.7 V
VCC = 3 V
VCC = 2.3 V
VCC = 2.7 V
IOL
V
VCC = 2.3 V to 2.7 V
VCC = 2.3 V
Low-level output current
VCC = 3 V
V
V
-12
Y port
-12
PARI/O
-12
Y port
-24
mA
12
Y port
12
PARI/O
12
Y port
24
YERR output
mA
24
∆t/∆v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
0
70
°C
(1)
4
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
IOH = -6 mA,
Y port
VOH
PARI/O
IOH = -12 mA
2.3 V
2
VIH = 1.7 V
2.3 V
1.7
2.7 V
2.2
VIH = 2 V
3V
2.4
VIH = 2 V
3V
2
IOH = -12 mA,
VIH = 2 V
3V
2
IOL = 12 mA
2.3 V to 3.6 V
0.2
VIL = 0.7 V
2.3 V
0.4
VIL = 0.7 V
2.3 V
0.7
VIL = 0.8 V
2.7 V
0.4
VIL = 0.8 V
3V
0.55
PARI/O
IOL = 12 mA,
VIL = 0.8 V
3V
0.55
YERR output
IOL = 24 mA
3V
0.5
II(hold)
3.6 V
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
VI = 2 V
3V
-75
VO = VCC
IOZ (3)
VO = VCC or GND
ICC
VI = VCC or GND,
∆ICC
One input at VCC - 0.6 V, Other inputs at VCC or GND
Ci
Co
Cio
(1)
(2)
(3)
Control inputs
Data inputs
YERR output
Data outputs
PARI/O
±5
VI = VCC or GND
VI = 0 to 3.6 V (2)
YERR output
UNIT
V
IOL = 24 mA,
II
IOH
MAX
2.3 V to 3.6 V VCC - 0.2
IOH = -24 mA,
IOL = 6 mA,
VOL
MIN TYP (1)
VIH = 1.7 V
IOL = 100 µA
Y port
VCC
IO = 0
V
µA
µA
3.6 V
±500
0 to 3.6 V
±10
µA
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
5.5
5.5
5
6
7
pF
pF
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
5
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1 and
Figure 4)
VCC = 2.5 V
± 0.2 V
MIN
fclock
Clock frequency
tw
Pulse duration, CLK↑
tsu
Setup time
MIN
125
MAX
MIN
125
3
3
Register mode
1.7
1.9
1.45
1A–10A before CLK↑
Buffer mode
5.9
5.2
4.4
Register mode
1.2
1.5
1.3
Buffer mode
4.6
3.6
3.1
PARI/O before CLK↑
Both modes
2.4
2
1.7
11A/YERREN before CLK↑
Buffer mode
2
1.9
1.6
CLKEN before CLK↑
Register mode
2.5
2.6
2.2
1A–12A after CLK↑
Register mode
1A–10A after CLK↑
Buffer mode
APAR before CLK↑
Hold time
PARI/O after CLK↑
0.4
0.25
0.55
0.25
0.25
0.25
0.7
0.4
0.7
Buffer mode
0.25
0.25
0.25
Register mode
0.25
0.25
0.4
Register mode
UNIT
MAX
125
3
1A–12A before CLK↑
APAR after CLK↑
th
MAX
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
Buffer mode
0.25
0.25
0.5
11A/YERREN after CLK↑
Buffer mode
0.25
0.25
0.4
CLKEN after CLK↑
Register mode
0.25
0.5
0.4
MHz
ns
ns
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 4)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
Buffer mode
A
Y
1
4.4
4.2
1.1
3.8
Both modes
CLK
YERR
1
5.7
4.9
1.4
4.4
PARI/O
1.2
8.6
7.9
1.7
6.6
tpd (1)
Both modes
CLK
PARI/O
1
6.8
5.2
1.3
4.5
ns
tpd
Both modes
MODE
Y
1
5.9
5.8
1.3
4.9
ns
CLK
Y
1
6.1
5.5
1.2
4.8
1
5.9
4.9
1.2
4.6
OE
Y
1.1
6.5
6.4
1.4
5.4
PAROE
PARI/O
1
5.6
6
1
4.8
PARAMETER
fmax
tPHL
Register mode
ten
Both modes
tdis
Both modes
tPLH
tPHL
(1)
6
MAX
125
tpd
tPLH
MIN
Both modes
MIN
MAX
125
MIN
UNIT
MAX
125
MHz
OE
Y
1
6.4
5.2
1.7
5
PAROE
PARI/O
1
3.2
3.8
1.2
3.8
OE
YERR
1
3.6
4.2
1.9
4
1.2
5.1
4.9
1.5
4.2
See Figure 2 and Figure 5 for the load specification.
ns
ns
ns
ns
ns
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
SIMULTANEOUS SWITCHING CHARACTERISTICS (1)
(see Figure 3 and Figure 6)
PARAMETER
tPLH
tPHL
(1)
Register mode
FROM
(INPUT)
TO
(OUTPUT)
CLK
Y
VCC = 2.5 V
± 0.2 V
MIN
MAX
1.8
1.4
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
6.5
6.1
1.8
5
5.9
5.1
1.7
4.5
ns
All outputs switching
OPERATING CHARACTERISTICS FOR BUFFER MODE
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
f = 10 MHz
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
57.5
65
15
17.5
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
57
87.5
16.5
34
UNIT
pF
OPERATING CHARACTERISTICS FOR REGISTER MODE
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
f = 10 MHz
UNIT
pF
7
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
YERR
S1
tPHL (see Note H)
tPLH (see Note I)
LOAD CIRCUIT
2 × VCC
2 × VCC
tw
VCC
Timing
Input
VCC/2
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
0V
th
VCC
Data
Input
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. tPHL is measured at VCC/2.
I. tPLH is measured at VOL + 0.15 V.
Figure 1. Load Circuit and Voltage Waveforms
8
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
From Output
Under Test
PARI/O
Test
Point
PARI/O of
Second
ALVCH16903
ZO = 52 Ω
td = 63 ps
CL = 0.6 pF
(see Note A)
CL = 0.6 pF
(see Note A)
LOAD CIRCUIT
VCC
Input
VCC/2
VCC/2
0V
tPLH
tPHL
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
VCC
From Output
Under Test
RL = 10 Ω
Test
Point
Input
VCC/2
VCC/2
0V
tPLH
CL = 30 pF
(see Note A)
tPHL
VOH
Output
VCC/2
VCC/2
VOL
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
Figure 3. Load Circuit and Voltage Waveforms
9
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
500 Ω
YERR
S1
tPHL (see Note H)
tPLH (see Note I)
6V
6V
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
Input
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
Output
Waveform 2
S1 at GND
(see Nte B)
tPHZ
1.5 V
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. tPHL is measured at 1.5 V.
I. tPLH is measured at VOL + 0.3 V.
Figure 4. Load Circuit and Voltage Waveforms
10
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
www.ti.com
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
From Output
Under Test
PARI/O
Test
Point
PARI/O of
Second
ALVCH16903
ZO = 52 Ω
td = 63 ps
CL = 0.6 pF
(see Note A)
CL = 0.6 pF
(see Note A)
LOAD CIRCUIT
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
2.7 V
From Output
Under Test
RL = 10 Ω
Test
Point
Input
1.5 V
1.5 V
0V
tPLH
CL = 50 pF
(see Note A)
tPHL
VOH
Output
1.5 V
1.5 V
VOL
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
Figure 6. Load Circuit and Voltage Waveforms
11
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
74ALVCH16903DGGRE4
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
74ALVCH16903DGGRG4
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
74ALVCH16903DGVRE4
ACTIVE
TVSOP
DGV
56
TBD
Call TI
Call TI
74ALVCH16903DGVRG4
ACTIVE
TVSOP
DGV
56
TBD
Call TI
Call TI
Purchase Samples
74ALVCH16903DLG4
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
SN74ALVCH16903DGGR
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
SN74ALVCH16903DGVR
ACTIVE
TVSOP
DGV
56
SN74ALVCH16903DL
ACTIVE
SSOP
DL
56
TBD
20
Green (RoHS
& no Sb/Br)
Call TI
Purchase Samples
Call TI
Purchase Samples
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2010
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74ALVCH16903DGGR TSSOP
DGG
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALVCH16903DGGR
TSSOP
DGG
56
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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