SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
D
D
D
D
D
D
D
D
D
D
D
D
D
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V VCC )
Typical VOLP (Output Ground Bounce)
VCC
h High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
VIK
VOH
VCC = 3 V,
VCC = 3 V to 3.6 V,
II = –18 mA
IOH = –100 µA
VCC = 3 V
IOH = –24 mA
IOH = –32 mA
VCC = 3 V to 3.6 V,
VOL
VCC = 3 V
VRST‡
Control inputs
Ioff
IBHL§
IBHH¶
IBHLO#
IBHHO||
IEXk
IOZ(PU/PD)h
ICC
2
IOL = 100 µA
IOL = 16 mA
0.2
IOL = 24 mA
IOL = 32 mA
0.5
IOL = 48 mA
IOL = 64 mA
0.55
0.5
VCC = 3.6 V
VI = 0
VI or VO = 0 to 4.5 V
–5
VI = 0.8 V
VI = 2 V
VI = 0 to VCC
VI = 0 to VCC
0.55
0.55
±1
±1
10
10
10
10
1
1
µA
–75
–75
µA
500
500
µA
Outputs low
Outputs disabled
VI = 3.3 V or 0
VO = 3.3 V or 0
µA
–500
0.06
VCC = 3.3 V,
VCC = 3.3 V,
µA
75
Outputs high
Ci
µA
75
–500
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
V
–5
±100
VO = 5.5 V
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
∆ICC◊
Cio
V
0.55
VI = 5.5 V
VI = VCC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
0.2
0.4
VI = VCC or GND
VI = 5.5 V
VCC = 3.6 V,
VCC = 3 V,
V
V
VCC = 3.6 V,
VCC = 0 or 3.6 V,
VCC = 3 V,
VCC = 3.6 V,
–1.2
UNIT
VCC–0.2
VCC = 3.6 V
VCC = 0,
VCC = 3 V,
SN74ALVTH16601
MIN TYP†
MAX
–1.2
VCC–0.2
2
IO = 1 mA,
VI = VCC or GND
II
A or B ports
SN54ALVTH16601
MIN TYP†
MAX
TEST CONDITIONS
125
125
µA
±100
±100
µA
0.1
0.06
0.1
3.5
5
3.5
5
0.06
0.1
0.06
0.1
0.4
0.4
3
3
7
7
mA
mA
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Data must not be loaded into the flip-flops/latches after applying power.
§ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
¶ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
# An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k Current into an output in the high state when VO > VCC
h High-impedance state during power up or power down
◊ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH16601
MIN
fclock
tw
Clock frequency
Pulse duration
150
CLK high or low
2.3
2.3
A or B before LE↓
A or B after CLK↑
Hold time
A or B after LE↓
CLKEN after CLK↑
MAX
150
1.8
CLKEN before CLK↑
th
MIN
1.8
Data high
Setup time
SN74ALVTH16601
LE high
A or B before CLK↑
tsu
MAX
4
4
Data low
5.2
5.2
CLK high
0.7
0.7
CLK low
0.9
0.9
Data high
1.7
1.7
Data low
2.3
2.3
Data high
0.5
0.5
Data low
0.5
0.5
CLK high
2.3
2.3
CLK low
2.4
2.4
Data high
0.5
0.5
Data low
0.5
0.5
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
SN54ALVTH16601
MIN
fclock
tw
Clock frequency
Pulse duration
Setup time
150
CLK high or low
2.3
2.3
Data high
2.4
2.4
Data low
3.8
3.8
1
1
CLK low
0.6
0.6
Data high
1.4
1.4
Data low
1.9
1.9
Data high
0.5
0.5
Data low
0.5
0.5
CLK high
A or B before LE↓
CLK high
A or B after LE↓
CLKEN after CLK↑
2
2
CLK low
2.3
2.3
Data high
0.6
0.6
Data low
0.5
0.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
150
1.8
A or B after CLK↑
Hold time
MIN
1.8
CLKEN before CLK↑
th
SN74ALVTH16601
LE high
A or B before CLK↑
tsu
MAX
UNIT
MHz
ns
ns
ns
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
SN54ALVTH16601
MIN
MAX
150
B or A
A or B
LEBA or LEAB
A or B
CLKBA or CLKAB
A or B
OEBA or OEAB
A or B
OEBA or OEAB
A or B
SN74ALVTH16601
MIN
MAX
150
UNIT
MHz
1.1
4.1
1.1
4.1
1.6
4.8
1.6
4.8
2.1
5
2.1
5
2.4
5.4
2.4
5.4
2
5
2
5
2.5
5.9
2.5
5.9
1.2
4.8
1.2
4.8
1
4.6
1
4.6
1.2
5.2
1.2
5.2
1
3.9
1
3.9
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
SN54ALVTH16601
MIN
MAX
150
B or A
A or B
LEBA or LEAB
A or B
CLKBA or CLKAB
A or B
OEBA or OEAB
A or B
OEBA or OEAB
A or B
SN74ALVTH16601
MIN
MAX
150
UNIT
MHz
1.4
3.9
1.4
3.9
1.1
3.9
1.1
3.9
2
4.6
2
4.6
2.1
4.6
2.1
4.6
1.9
4.5
1.9
4.5
2.2
4.6
2.2
4.6
1
4.2
1
4.2
1
4.4
1
4.4
1.8
5.3
1.8
5.3
1.7
4.6
1.7
4.6
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
3V
3V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
th
3V
1.5 V
3V
1.5 V
0V
0V
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
3V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
1.5 V
tPLZ
tPZL
1.5 V
tPLH
1.5 V
0V
3V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
0V
0V
tsu
Data
Input
1.5 V
Input
1.5 V
VOH
VOH – 0.3 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74ALVTH16601DL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVTH16601
Samples
SN74ALVTH16601DLR
ACTIVE
SSOP
DL
56
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVTH16601
Samples
SN74ALVTH16601GR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVTH16601
Samples
SN74ALVTH16601VR
ACTIVE
TVSOP
DGV
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VT601
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of