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SN74AUP1G125
SCES595N – JULY 2004 – REVISED JULY 2017
SN74AUP1G125 Low-Power Single Bus Buffer Gate With 3-State Output
1 Features
3 Description
•
The SN74AUP1G125 bus buffer gate is a single line
driver with a 3-state output. The output is disabled
when the output-enable (OE) input is high. This
device has the input-disable feature, which allows
floating input signals.
1
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(Cpd = 4 pF Typical at 3.3 V)
Low Input Capacitance (CI = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
< 10% of VCC
Input-Disable Feature Allows Floating Input
Conditions
Ioff Supports Partial-Power-Down Mode Operation
Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at Input
Wide Operating VCC Range of 0.8 V to 3.6 V
3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
tpd = 4.6 ns Maximum at 3.3 V
2 Applications
•
•
•
•
•
•
•
•
Audio Dock: Portable
BluRay™ Players and Home Theaters
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid-State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablet: Enterprise
Wireless Headsets, Keyboards, and Mice
To ensure the high-impedance state during power up
or power down, OE must be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUP1G125DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUP1G125DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74AUP1G125DRL
SOT (5)
1.60 mm × 1.20 mm
SN74AUP1G125DRY
SN74AUP1G125DSF
SON (6)
1.45 mm × 1.00 mm
1.00 mm × 1.00 mm
SN74AUP1G125YFP
DSBGA (6)
0.76 mm × 1.16 mm
SN74AUP1G125YZP
DSBGA (5)
0.89 mm × 1.39 mm
SN74AUP1G125YZT
DSBGA (5)
0.89 mm × 1.39 mm
SN74AUP1G125DPW
X2SON (5)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
OE
A
1
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74AUP1G125
SCES595N – JULY 2004 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics, TA = 25°C ........................ 6
Electrical Characteristics, TA = –40°C to +85°C ....... 7
Switching Characteristics, CL = 5 pF ........................ 8
Switching Characteristics, CL = 10 pF ...................... 9
Switching Characteristics, CL = 15 pF .................... 10
Switching Characteristics, CL = 30 pF .................. 11
Operating Characteristics...................................... 12
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 13
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (December 2015) to Revision N
Page
•
Added DPW (X2SON) package.............................................................................................................................................. 1
•
Deleted Device Comparison table, see Mechanical, Packaging, and Orderable Information section at the end of the
data sheet ............................................................................................................................................................................... 1
•
Changed Simplified Schematic with a new schematic ........................................................................................................... 1
•
Added column for X2SON (DPW) package and separated columns for DSBGA packages in Pin Functions table .............. 3
•
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
•
Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), and Over-voltage Tolerant Inputs ................................................................................................................................. 15
•
Added Trace Example and revised Layout Guidelines ........................................................................................................ 18
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 20
Changes from Revision L (February 2013) to Revision M
•
Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Changes from Revision K (November 2012) to Revision L
•
2
Page
Page
Changed Y to Y for pin 4 in DSF Package pin out ................................................................................................................ 3
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Product Folder Links: SN74AUP1G125
SN74AUP1G125
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SCES595N – JULY 2004 – REVISED JULY 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OE
1
A
2
GND
3
DSF Package
6-Pin SON
Top View
OE
1
6
VCC
A
2
5
N.C.
GND
3
4
Y
VCC
5
Y
4
DRY Package
6-Pin SON
Top View
DRL Package
5-Pin SOT
Top View
OE
1
A
2
GND
3
5
VCC
4
Y
OE
1
6
VCC
A
2
5
N.C.
GND
3
4
Y
YFP Package
6-Pin DSBGA
Bottom View
YZP or YZT Package
5-Pin DSBGA
Bottom View
1
2
C
GND
Y
B
A
A
OE
1
2
C
GND
Y
B
A
DNU
A
OE
VCC
Not to scale
VCC
DPW Package
5-Pin X2SON
Top View
Not to scale
DCK Package
5-Pin SC70
Top View
OE
1
A
2
GND
3
5
VCC
4
Y
Pin Functions
PIN
NAME
SOT-23 (DBV), SC70
(DCK), SOT (DRL),
X2SON (DPW)
SON (DRY
or DSF)
DSBGA (YZP
or YZT)
DSBGA
(YFP)
I/O
DESCRIPTION
A
2
2
B1
B1
I
DNU
—
—
—
B2
—
Input
Do not use
GND
3
3
C1
C1
—
Ground
N.C.
—
5
—
—
—
No connection
OE
1
1
A1
A1
I
VCC
5
6
A2
A2
—
Positive supply
Y
4
4
C2
C2
O
Output
Output enable (active low)
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SCES595N – JULY 2004 – REVISED JULY 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
(2)
VI
Input voltage
–0.5
4.6
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCES595N – JULY 2004 – REVISED JULY 2017
6.3 Recommended Operating Conditions
See
(1)
VCC
MIN
MAX
Supply voltage
0.8
3.6
VCC
3.6
0.65 × VCC
3.6
1.6
3.6
2
3.6
VCC = 1.1 V to 1.95 V
0
0.35 × VCC
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 3 V to 3.6 V
0
0.9
Active state
0
VCC
3-state
0
3.6
VCC = 0.8 V
VIH
VCC = 1.1 V to 1.95 V
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 0.8 V
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current
Low-level output current
VCC = 0.8 V
–20
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
V
µA
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
V
0
VCC = 3 V
IOL
UNIT
µA
mA
4
VCC = 0.8 V to 3.6 V
200
ns/V
85
°C
–40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow of Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74AUP1G125
THERMAL METRIC
(1)
DCK
(SC70)
DBV
(SOT-23)
DRL
(SOT)
DRY
(SON)
DSF
(SON)
YFP
(DSBGA)
YZP
(DSBGA)
DPW
(X2SON)
UNIT
5 PINS
5 PINS
5 PINS
6 PINS
6 PINS
6 PINS
5 PINS
5 PINS
Junction-toambient thermal
resistance
303.6
230.5
295.1
342.1
377.1
125.4
146.2
504.3
°C/W
Junction-to-case
(top) thermal
resistance
203.8
172.7
131.0
233.1
187.7
1.9
1.4
234.9
°C/W
RθJB
Junction-to-board
thermal resistance
100.9
62.2
143.9
206.7
236.6
37.2
39.3
370.3
°C/W
ψθJt
Junction-to-top
characterization
parameter
76.1
49.3
14.7
63.4
29.0
0.5
0.7
44.5
°C/W
Junction-to-board
characterization
parameter
99.3
61.6
144.4
206.7
236.3
37.5
39.8
369.7
°C/W
Junction-to-case
(bottom) thermal
resistance
N/A
N/A
N/A
N/A
N/A
N/A
N/A
165.2
°C/W
RθJA
RθJC(top)
ψθJB
RθJC(bot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics, TA = 25°C
PARAMETER
VOH
TEST CONDITIONS
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
IOH = –1.7 mA
1.4 V
1.11
IOH = –1.9 mA
1.65 V
1.32
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
MAX
1.9
2.72
2.6
IOL = 1.1 mA
1.1 V
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
IOL = 1.9 mA
1.65 V
0.31
0.1
0.31
2.3 V
IOL = 2.7 mA
VI = GND to 3.6 V
V
0.44
0.31
3V
IOL = 4 mA
UNIT
V
2.05
0.8 V to 3.6 V
IOL = 3.1 mA
A or OE
input
TYP
IOL = 20 µA
IOL = 2.3 mA
II
MIN
0.8 V to 3.6 V
IOH = –2.3 mA
VOL
VCC
IOH = –20 µA
0.44
0 V to 3.6 V
0.1
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
µA
IOZ
VO = VCC or GND
3.6 V
0.1
µA
ICC
VI = GND or (VCC to 3.6 V),
OE = GND, IO = 0
0.8 V to 3.6 V
0.5
µA
A input
ΔICC
OE input
All inputs
VI = VCC – 0.6 V (1),
IO = 0
3.3 V
VI = GND to 3.6 V,
OE = VCC (2)
0.8 V to 3.6 V
CI
VI = VCC or GND
Co
VO = VCC or GND
(1)
(2)
6
40
110
µA
0
0V
1.5
3.6 V
1.5
3.6 V
3
pF
pF
One input at VCC – 0.6 V, other input at VCC or GND
To show ICC is very low when the input-disable feature is enabled
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SCES595N – JULY 2004 – REVISED JULY 2017
6.6 Electrical Characteristics, TA = –40°C to +85°C
PARAMETER
VOH
TEST CONDITIONS
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.03
IOH = –1.9 mA
1.65 V
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
MAX
1.3
1.85
2.67
2.55
IOL = 1.1 mA
1.1 V
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.37
IOL = 1.9 mA
1.65 V
0.35
2.3 V
IOL = 2.7 mA
3V
IOL = 4 mA
VI = GND to 3.6 V
UNIT
V
1.97
0.8 V to 3.6 V
IOL = 3.1 mA
A or OE
input
TYP
IOL = 20 µA
IOL = 2.3 mA
II
MIN
0.8 V to 3.6 V
IOH = –2.3 mA
VOL
VCC
IOH = –20 µA
0.1
0.33
V
0.45
0.33
0.45
0 V to 3.6 V
0.5
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.6
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.6
µA
IOZ
VO = VCC or GND
3.6 V
0.5
µA
ICC
VI = GND or (VCC to 3.6 V),
OE = GND, IO = 0
0.8 V to 3.6 V
0.9
µA
A input
ΔICC
OE input
All inputs
(1)
(2)
VI = VCC – 0.6 V (1),
IO = 0
3.3 V
VI = GND to 3.6 V,
OE = VCC (2)
0.8 V to 3.6 V
50
120
µA
0
One input at VCC – 0.6 V, other input at VCC or GND
To show ICC is very low when the input-disable feature is enabled
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6.7 Switching Characteristics, CL = 5 pF
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 2 and Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA
0.8 V
TA = 25°C
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tpd
A
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
ten
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tdis
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
8
MIN
4.3
TA = –40°C to +85°C
2.7
TA = 25°C
3.3
2.6
TA = –40°C to +85°C
1.3
2
TA = –40°C to +85°C
1.1
TA = 25°C
1.7
TA = –40°C to +85°C
5.1
TA = –40°C to +85°C
3.6
TA = 25°C
4.1
TA = –40°C to +85°C
2.5
TA = 25°C
3.2
TA = –40°C to +85°C
2.1
TA = 25°C
2.5
TA = –40°C to +85°C
1.6
TA = 25°C
2.1
TA = –40°C to +85°C
1.4
TA = 25°C
TA = 25°C
2.4
2.2
TA = 25°C
1.8
TA = –40°C to +85°C
1.7
TA = –40°C to +85°C
1
8.5
10.2
4.1
6.8
ns
8.3
2.9
4.7
5.8
2.4
3.8
4.6
9.3
15.9
19.2
6.6
10.5
12.7
5.3
8.7
ns
10.3
3.8
6
7.2
3.2
4.9
5.9
4.1
1
TA = –40°C to +85°C
1.1
4.5
5.1
2.9
4.3
ns
4.7
1.8
1
1.2
6.9
7.7
2.9
1.5
TA = 25°C
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5.2
12.1
TA = –40°C to +85°C
TA = 25°C
12.6
19.1
TA = 25°C
TA = –40°C to +85°C
UNIT
15.3
1
TA = 25°C
TA = 25°C
7.4
1
TA = 25°C
TA = 25°C
MAX
18.1
TA = 25°C
TA = –40°C to +85°C
TYP
2.7
3.3
2.2
3.2
4
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SCES595N – JULY 2004 – REVISED JULY 2017
6.8 Switching Characteristics, CL = 10 pF
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 2 and Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA
0.8 V
TA = 25°C
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tpd
A or B
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
ten
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tdis
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
TYP
MAX
20.5
TA = 25°C
4.6
TA = –40°C to +85°C
3.6
TA = 25°C
3.5
TA = –40°C to +85°C
2.4
TA = 25°C
3.9
TA = –40°C to +85°C
1.3
TA = 25°C
2.3
TA = –40°C to +85°C
1.6
TA = 25°C
2.1
TA = –40°C to +85°C
1.4
TA = 25°C
8.4
13.7
16.6
5.9
9.3
11.1
4.7
7.5
4.9
TA = –40°C to +85°C
4.4
TA = 25°C
3.9
TA = –40°C to +85°C
3.3
TA = 25°C
3.4
TA = –40°C to +85°C
2.7
TA = 25°C
2.5
TA = –40°C to +85°C
2.1
TA = 25°C
2.1
TA = –40°C to +85°C
1.9
TA = 25°C
9.1
3.4
5.3
6.4
2.8
4.3
5.2
10.2
16.8
20.2
7.3
11.2
13.5
5.8
9.2
ns
11
4.3
6.4
7.8
3.7
5.4
6.4
13
TA = 25°C
3.8
TA = –40°C to +85°C
1.2
TA = 25°C
2.2
TA = –40°C to +85°C
1.3
TA = 25°C
2.4
TA = –40°C to +85°C
2.2
TA = 25°C
1.3
TA = –40°C to +85°C
1.2
TA = 25°C
1.9
TA = –40°C to +85°C
1.9
6.6
11.7
4.7
7.9
14
9.3
4.4
6.4
ns
7.5
3.1
4.9
5.4
3.4
5
5.6
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21.8
TA = 25°C
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UNIT
9
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6.9 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2 and Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA
0.8 V
TA = 25°C
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tpd
A or B
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
ten
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tdis
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
10
MIN
5.8
TA = –40°C to +85°C
4.3
TA = 25°C
4.4
3.5
TA = –40°C to +85°C
2.3
TA = 25°C
2.7
TA = –40°C to +85°C
1.9
TA = 25°C
2.4
TA = –40°C to +85°C
1.8
TA = 25°C
UNIT
15.1
17.9
6.6
10.2
12.1
5.3
8.3
ns
9.9
3.9
5.8
3.2
4.7
7
5.7
25.2
7
TA = –40°C to +85°C
5.4
TA = 25°C
5.5
TA = –40°C to +85°C
4.1
TA = 25°C
4.3
TA = –40°C to +85°C
3.3
TA = 25°C
3.4
TA = –40°C to +85°C
2.6
TA = 25°C
2.9
TA = –40°C to +85°C
2.3
TA = 25°C
11.3
18.1
21.4
8.1
12.2
14.5
6.5
10.1
ns
12
4.8
7.1
8.4
4.1
5.9
6.9
14
TA = 25°C
3.7
TA = –40°C to +85°C
3.3
TA = 25°C
5.5
TA = –40°C to +85°C
2.1
TA = 25°C
3.3
TA = –40°C to +85°C
2.9
TA = 25°C
2.3
TA = –40°C to +85°C
1.8
TA = 25°C
2.4
TA = –40°C to +85°C
3.1
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9.3
3
TA = 25°C
TA = 25°C
MAX
22.5
TA = 25°C
TA = –40°C to +85°C
TYP
5.8
8.2
3.9
5.9
4.5
6.6
11
8
ns
7.4
3.2
4.3
5.1
4.8
6.2
6.7
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6.10 Switching Characteristics, CL = 30 pF
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 2 and Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA
0.8 V
TA = 25°C
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tpd
A or B
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
ten
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
tdis
OE
Y
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
TYP
MAX
29
TA = 25°C
7.4
TA = –40°C to +85°C
6.6
TA = 25°C
5.7
TA = –40°C to +85°C
4.9
TA = 25°C
4.8
TA = –40°C to +85°C
3.1
TA = 25°C
3.9
TA = –40°C to +85°C
3.3
TA = 25°C
3.5
TA = –40°C to +85°C
12
18.7
21.4
8.6
12.5
14.7
6.9
10.1
5.1
7.2
8.7
4.8
6
7
33.4
TA = 25°C
8.8
TA = –40°C to +85°C
7.4
TA = 25°C
6.9
TA = –40°C to +85°C
5.6
TA = 25°C
5.6
TA = –40°C to +85°C
4.7
TA = 25°C
4.3
TA = –40°C to +85°C
3.8
TA = 25°C
3.7
TA = –40°C to +85°C
3.4
TA = 25°C
14.1
21.8
25.5
10.1
14.6
17.4
8.1
12
ns
14.1
6.1
8.5
10
5.2
7.1
8.3
17.7
TA = 25°C
5.8
TA = –40°C to +85°C
3.7
TA = 25°C
5.7
TA = –40°C to +85°C
10
16
7.7
10.9
16
1
TA = 25°C
4.5
TA = –40°C to +85°C
4.4
TA = 25°C
3.9
TA = –40°C to +85°C
3.2
TA = 25°C
3.3
TA = –40°C to +85°C
6.6
10.7
7.7
9.8
ns
12.5
5.6
7.4
8.4
10.7
9
10.8
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12
3
TA = 25°C
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UNIT
11
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6.11 Operating Characteristics
TA = 25°c
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
f = 10 MHz
Power dissipation capacitance
Outputs disabled
f = 10 MHz
VCC
TYP
0.8 V
3.8
1.2 V ± 0.1 V
3.8
1.5 V ± 0.1 V
3.7
1.8 V ± 0.15 V
3.8
2.5 V ± 0.2 V
3.9
3.3 V ± 0.3 V
4
0.8 V
0
1.2 V ± 0.1 V
0
1.5 V ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
UNIT
pF
6.12 Typical Characteristics
30
CL = 5pF
CL = 10pF
CL = 15pF
CL = 30pF
27.5
25
22.5
TPD (ns)
20
17.5
15
12.5
10
7.5
5
2.5
0
0.75
1.25
1.75
2.25
VCC (V)
2.75
3.25
D001
Figure 1. Propagation Delay vs. Supply Voltage and Load Capacitance
12
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7 Parameter Measurement Information
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
VM
Output
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL + V∆
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms (Enable and Disable Times)
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8 Detailed Description
8.1 Overview
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family of devices is specified for low static and dynamic power consumption across the entire
VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal
integrity (see Figure 2 and Figure 3).
The SN74AUP1G125 device contains one buffer gate device with output enable control and performs the
Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device,
which prevents damage to the device.
To assure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
OE
A
1
2
4
Y
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings table
must be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics, TA = 25°C table. The worst case resistance is calculated with
the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage
current, given in the Electrical Characteristics, TA = 25°C table, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating
Conditions table to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device
with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
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Feature Description (continued)
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 4. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics, TA = 25°C table.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings table.
8.4 Device Functional Modes
Table 1 lists the functional modes for SN74AUP1G125.
Table 1. Function Table
INPUTS
16
OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Hi-Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AUP1G125 device is a high-drive CMOS device that is used as a output enabled buffer with a high
output drive, such as an LED application. The device can produce 24 mA of drive current at 3.3 V, which is ideal
for driving multiple outputs and good for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant,
allowing it to translate down to VCC.
9.2 Typical Application
Basic LED Driver
Buffer Function
VCC
VCC
uC or Logic
uC or Logic
Wired OR
uC or Logic
uC or Logic
AUP1G125
uC or Logic
AUP1G125
Figure 5. Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads so
routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
9.2.3 Application Curve
3.5
3
Voltage − V
2.5
2
1.5
1
Input
Output
0.5
0
−0.5
0
10
5
15
20 25 30
Time − ns
35
40
45
Figure 6. Switching Characteristics at 25 MHz
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. TI recommends to use a 0.1-µF
capacitor for this device. It is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF
and 1-µF capacitors are commonly used in parallel. Install the bypass capacitor as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent the inputs from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. The inputs should be tied to GND
or VCC, whichever makes more sense or is more convenient.
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 8 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
VCC
Input
Unused Input
Output
Output
Unused Input
Input
Figure 7. Proper Multi-Gate Input Termination Diagram
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Layout Example (continued)
BETTER
BEST
2W
WORST
1W min.
W
Figure 8. Trace Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
BluRay is a trademark of Blu-ray Disc Association (BDA).
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74AUP1G125DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HM5
SN74AUP1G125DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H25R
SN74AUP1G125DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H25R
SN74AUP1G125DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HM5, HMF, HMK, HM
R)
SN74AUP1G125DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HM5, HMR)
SN74AUP1G125DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
B1
SN74AUP1G125DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(HM7, HMR)
SN74AUP1G125DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HM
SN74AUP1G125DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HM
SN74AUP1G125YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
SN74AUP1G125YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
HMN
-40 to 85
HMN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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