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SN74AVCH2T45
SCES582H – JULY 2004 – REVISED APRIL 2015
SN74AVCH2T45 2-Bit, 2-Supply, Bus Transceiver with Configurable Level-Shifting and
Translation and 3-State Outputs
1 Features
3 Description
•
This 2-bit non-inverting bus transceiver uses two
separate configurable power-supply rails. The A ports
are designed to track VCCA and accepts any supply
voltage from 1.2 V to 3.6 V. The B ports are designed
to track VCCB and accepts any supply voltage from
1.2 V to 3.6 V. This allows for universal low-voltage
bidirectional translation and level-shifting between
any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V
voltage nodes.
1
•
•
•
•
•
•
•
•
Available in the Texas Instruments NanoFree™
Package
VCC Isolation
2-Rail Design
I/Os are 4.6 V Tolerant
Partial Power-Down-Mode Operation
Bus Hold on Data Inputs
Maximum Data Rates
– 500 Mbps (1.8 V to 3.3 V)
– 320 Mbps (< 1.8 V to 3.3 V)
– 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)
– 280 Mbps (Level-Shifting to 1.5 V)
– 240 Mbps (Level-Shifting to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2 Applications
•
•
•
•
The SN74AVCH2T45 is designed for asynchronous
communication between two data buses. The logic
levels of the direction-control (DIR pin) input activate
either the B-port outputs or the A-port outputs. The
device transmits data from the A bus to the B bus
when the B-port outputs are activated and from the B
bus to the A bus when the A-port outputs are
activated. The SN74AVCH2T45 features active bushold circuitry, which holds unused or un-driven inputs
at a valid logic state. TI does not recommend using
pull-up or pull-down resistors with the bus-hold
circuitry.
Device Information(1)
Smartphone
Servers
Desktop PCs and Notebooks
Other Portable Devices
PART NUMBER
PACKAGE
SN74AVCH2T45
BODY SIZE (NOM)
SSOP (8)
2.95 mm × 2.80 mm
VSSOP (8)
2.30 mm × 2.00 mm
DSBGA (8)
1.89 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
VCCB
VCCA
8
1
VCCB
VCCA
DIR
A1
5
2
7
A2
B1
3
6
B2
VCCB
VCCA
4 GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AVCH2T45
SCES582H – JULY 2004 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
2
1
1
1
3
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions ...................... 6
Thermal Information .................................................. 7
Electrical Characteristics .......................................... 7
Switching Characteristics: VCCA = 1.2 V ................... 8
Switching Characteristics: VCCA = 1.5 V .................. 9
Switching Characteristics: VCCA = 1.8 V ................. 10
Switching Characteristics: VCCA = 2.5 V ................. 10
Switching Characteristics: VCCA = 3.3 V ............... 11
Operating Characteristics...................................... 11
Typical Characteristics .......................................... 12
8
9
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
15
10 Application and Implementation........................ 16
10.1 Application Information.......................................... 16
10.2 Typical Applications .............................................. 16
11 Power Supply Recommendations ..................... 20
12 Layout................................................................... 20
12.1 Layout Guidelines ................................................. 20
12.2 Layout Example .................................................... 20
13 Device and Documentation Support ................. 21
13.1
13.2
13.3
13.4
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
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SCES582H – JULY 2004 – REVISED APRIL 2015
4 Revision History
Changes from Revision G (April 2015) to Revision H
Page
•
Added additional applications................................................................................................................................................. 1
•
Updated Overview section. .................................................................................................................................................. 14
•
Updated Layout Guidelines section. .................................................................................................................................... 20
Changes from Revision F (November 2007) to Revision G
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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5 Description (Continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. The VCC isolation feature
ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold
circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is
a major breakthrough in IC packaging concepts, using the die as the package.
6 Pin Configurations and Functions
DCT and DCU Packages
8-Pin SSOP and VSSOP
Top View
VCCA
A1
A2
GND
1
8
2
7
3
6
4
5
VCCB
B1
B2
DIR
YZP Package
8-Pin DSBGA
Bottom View
GND
D1
4 5
D2
DIR
A2
C1
3 6
C2
B2
A1
B1
2 7
B2
B1
VCCA
A1
1 8
A2
VCCB
Pin Functions
PIN
DESCRIPTION
SSOP,
VSSOP
DSBGA
VCCA
1
A1
Supply Voltage A
VCCB
8
A2
Supply Voltage B
GND
4
D1
Ground
A1
2
B1
Output or input depending on state of DIR. Output level depends on VCCA.
A2
3
C1
Output or input depending on state of DIR. Output level depends on VCCA.
B1
7
B2
Output or input depending on state of DIR. Output level depends on VCCB.
B2
6
C2
Output or input depending on state of DIR. Output level depends on VCCB.
DIR
5
D2
Direction Pin, Connect to GND or to VCCA.
NAME
4
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SCES582H – JULY 2004 – REVISED APRIL 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
4.6
V
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
VCCA
VCCB
Supply voltage
VI
Input voltage (2)
VO
Voltage range applied to any output
in the high-impedance or power-off state (2)
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA, VCCB, or GND
±100
mA
V
V
V
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model (MM), Per JEDEC specification JESD22-A115-A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
VCCI (4)
VCCO (5)
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
High-level
input
voltage
VIH
Low-level
input
voltage
VIL
High-level
input
voltage
VIH
Low-level
input
voltage
VIL
VI
Data inputs (2)
Data inputs (2)
Output
voltage
IOH
DIR
(referenced to
VCCA) (3)
DIR
(referenced to
VCCA) (3)
1.6
2.7 V to 3.6 V
2
V
1.2 V to 1.95 V
VCCI (4) × 0.35
1.95 V to 2.7 V
0.7
VCCA × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
V
1.2 V to 1.95 V
VCCA × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
0
3.6
0
VCCO (5)
3-state
0
3.6
Low-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
V
0.8
1.2 V to 1.95 V
Active state
Δt/Δv
6
1.95 V to 2.7 V
2.7 V to 3.6 V
High-level output current
IOL
(2)
(3)
(4)
(5)
VCCI (4) × 0.65
Input voltage
VO
(1)
1.2 V to 1.95 V
1.2 V
–3
1.4 V to 1.6 V
–6
1.65 V to 1.95
V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95
V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
–40
V
V
V
mA
mA
5
ns/V
85
°C
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
VCCI is the voltage associated with the input port supply VCCA or VCCB.
VCCO is the voltage associated with the output port supply VCCA or VCCB.
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7.4 Thermal Information
SN74AVCH2T45
THERMAL METRIC (1)
DCT (SSOP)
DCU (VSSOP) YZP (DSBGA)
8 PINS
8 PINS
8 PINS
105.8
RθJA
Junction-to-ambient thermal resistance
194.4
199.3
RθJC(top)
Junction-to-case (top) thermal resistance
124.7
76.2
1.6
RθJB
Junction-to-board thermal resistance
106.8
80.6
10.8
ψJT
Junction-to-top characterization parameter
49.8
7.1
3.1
ψJB
Junction-to-board characterization parameter
105.8
80.1
10.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VCCA
VCCB
1.2 V to 3.6 V
1.2 V to 3.6 V
1.2 V
1.2 V
IOH = –3 mA
IOH = –6 mA
VOH (3)
IBHH (5)
IBHLO (6)
(1)
(2)
(3)
(4)
(5)
(6)
TYP
MAX
VCCO – 0.2
1.05
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
IOH = –12 mA
3V
3V
2.3
IOL = 100 μA
1.2 V to 3.6 V
1.2 V to 3.6 V
1.2 V
1.2 V
V
0.2
0.15
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
1.2 V to 3.6 V
1.2 V to 3.6 V
1.2 V
1.2 V
IOL = 8 mA
VI = VCCA or GND
VI = VIL
V
0.7
±0.025
±0.25
±1
μA
25
VI = 0.49 V
1.4 V
1.4 V
15
VI = 0.58 V
1.65 V
1.65 V
25
VI = 0.7 V
2.3 V
2.3 V
45
VI = 0.8 V
3.3 V
3.3 V
VI = 0.78 V
1.2 V
1.2 V
μA
100
–25
VI = 0.91 V
1.4 V
1.4 V
–15
VI = 1.07 V
1.65 V
1.65 V
–25
VI = 1.6 V
2.3 V
2.3 V
–45
VI = 2 V
3.3 V
3.3 V
1.2 V
1.2 V
VI = 0 to VCC
UNIT
0.95
1.4 V
VI = 0.42 V
IBHL (4)
MIN
1.65 V
IOL = 6 mA
DIR input
–40°C to 85°C
MAX
1.4 V
VI = VIH
IOL = 3 mA
II (3)
TYP
1.65 V
IOH = –8 mA
VOL (3)
TA = 25°C
MIN
μA
–100
50
1.6 V
1.6 V
125
1.95 V
1.95 V
200
2.7 V
2.7 V
300
3.6 V
3.6 V
500
μA
VCCO is the voltage associated with the output port supply VCCA or VCCB.
VCCI is the voltage associated with the input port supply VCCA or VCCB.
VOH: Output High Voltage; VOL: Output Low Voltage; II: Control Input Current.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL maximum. IBHL should be measured after lowering VIN to
GND and then raising it to VIL maximum.
The bus-hold circuit can source at least the minimum high sustaining current at VIH mininum. IBHH should be measured after raising VIN
to VCC and then lowering it to VIH minimum.
An external driver must source at least IBHLO to switch this node from low to high.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER
IBHHO (7)
TEST CONDITIONS
VI = 0 to VCC
A port
Ioff (8)
B port
B port
IOZ (8)
A port
ICCA (8)
VI or VO = 0 to 3.6 V
VO = VCCO or GND,
VI = VCCI or GND
VI = VCCI or GND, IO = 0
ICCB (8)
VI = VCCI or GND, IO = 0
ICCA + ICCB
VI = VCCI or GND, IO = 0
TA = 25°C
–40°C to 85°C
VCCA
VCCB
1.2 V
1.2 V
1.6 V
1.6 V
–125
1.95 V
1.95 V
–200
2.7 V
2.7 V
–300
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
–50
μA
3.6 V
3.6 V
0V
0 V to 3.6 V
±0.1
±1
–500
±5
0 V to 3.6 V
0V
±0.1
±1
±5
0V
3.6 V
±0.5
±2.5
±5
3.6 V
0V
±0.5
±2.5
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
–2
3.6 V
0V
10
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
10
3.6 V
0V
–2
1.2 V to 3.6 V
1.2 V to 3.6 V
20
μA
μA
μA
μA
μA
Ci
Control
inputs
VI = 3.3 V or GND
3.3 V
3.3 V
2.5
pF
Cio
A or B port VI = 3.3 V or GND
3.3 V
3.3 V
6
pF
(7)
(8)
An external driver must sink at least IBHHO to switch this node from high to low.
Ioff: Partial Power Down Output current; IOZ: Hi-Z Output Current; ICCA: Supply A Current; ICCB: Supply B Current.
7.6 Switching Characteristics: VCCA = 1.2 V
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 7)
PARAMETER
tPLH (1)
tPHL (1)
tPLH (1)
tPHL
(1)
tPHZ (1)
tPLZ (1)
tPHZ (1)
tPLZ
(1)
tPZH (1) (2)
tPZL (1) (2)
tPZH (1) (2)
tPZL (1) (2)
(1)
(2)
8
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3.1
2.6
2.4
2.2
2.2
3.1
2.6
2.4
2.2
2.2
3.4
3.1
3
2.9
2.9
3.4
3.1
3
2.9
2.9
5.2
5.2
5.1
5
4.8
5.2
5.2
5.1
5
4.8
5
4
3.8
2.8
3.2
5
4
3.8
2.8
3.2
8.4
7.1
6.8
5.7
6.1
8.4
7.1
6.8
5.7
6.1
8.3
7.8
7.5
7.2
7
8.3
7.8
7.5
7.2
7
UNIT
ns
ns
ns
ns
ns
ns
tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
The enable time is a calculated value derived using the formula shown in the Enable Times section.
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7.7 Switching Characteristics: VCCA = 1.5 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 7)
PARAMETER
tPLH (1)
tPHL (1)
tPLH (1)
tPHL (1)
tPHZ (1)
tPLZ
(1)
tPHZ (1)
tPLZ (1)
tPZH (1) (2)
tPZL
(1) (2)
tPZH (1) (2)
tPZL (1) (2)
(1)
(2)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
0.7
5.4
0.5
4.6
0.4
3.7
0.3
3.5
2.8
0.7
5.4
0.5
4.6
0.4
3.7
0.3
3.5
2.7
0.8
5.4
0.7
5.2
0.6
4.9
0.5
4.7
2.7
0.8
5.4
0.7
5.2
0.6
4.9
0.5
4.7
3.9
1.3
8.5
1.3
7.8
1.1
7.7
1.4
7.6
3.9
1.3
8.5
1.3
7.8
1.1
7.7
1.4
7.6
4.7
1.1
7
1.4
6.9
1.2
6.9
1.7
7.1
4.7
1.1
7
1.4
6.9
1.2
6.9
1.7
7.1
7.4
12.4
12.1
11.8
11.8
7.4
12.4
12.1
11.8
11.8
6.7
13.9
12.4
11.4
11.1
6.7
13.9
12.4
11.4
11.1
UNIT
ns
ns
ns
ns
ns
ns
tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
The enable time is a calculated value derived using the formula shown in the Enable Times section.
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7.8 Switching Characteristics: VCCA = 1.8 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 7)
PARAMETER
tPLH (1)
tPHL (1)
tPLH (1)
tPHL (1)
tPHZ (1)
tPLZ
(1)
tPHZ (1)
tPLZ (1)
tPZH (1) (2)
tPZL
(1) (2)
tPZH (1) (2)
tPZL (1) (2)
(1)
(2)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.7
0.5
5.2
0.4
4.3
0.2
3.4
0.2
3.1
2.7
0.5
5.2
0.4
4.3
0.2
3.4
0.2
3.1
2.4
0.7
4.7
0.5
4.4
0.5
4
0.4
3.8
2.4
0.7
4.7
0.5
4.4
0.5
4
0.4
3.8
3.7
1.3
8.1
0.7
6.9
1.4
5.3
1.1
5.2
3.7
1.3
8.1
0.7
6.9
1.4
5.3
1.1
5.2
4.4
1.3
5.8
1.3
5.9
0.8
5.7
1.5
5.9
4.4
1.3
5.8
1.3
5.9
0.8
5.7
1.5
5.9
6.8
10.5
10.3
9.7
9.7
6.8
10.5
10.3
9.7
9.7
6.4
13.3
11.2
8.7
8.3
6.4
13.3
11.2
8.7
8.3
UNIT
ns
ns
ns
ns
ns
ns
tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
The enable time is a calculated value derived using the formula shown in the Enable Times section.
7.9 Switching Characteristics: VCCA = 2.5 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 7)
PARAMETER
tPLH (1)
tPHL (1)
tPLH (1)
tPHL (1)
tPHZ (1)
tPLZ
(1)
tPHZ (1)
tPLZ (1)
tPZH (1) (2)
tPZL
(1) (2)
tPZH (1) (2)
tPZL (1) (2)
(1)
(2)
10
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.4
4.9
0.2
4
0.2
3
0.2
2.6
2.6
0.4
4.9
0.2
4
0.2
3
0.2
2.6
2.1
0.6
3.8
0.5
3.4
0.4
3
0.3
2.8
2.1
0.6
3.8
0.5
3.4
0.4
3
0.3
2.8
2.4
0.7
7.9
0.8
6.4
0.8
5
0.5
4.3
2.4
0.7
7.9
0.8
6.4
0.8
5
0.5
4.3
3.8
1
4.3
0.6
4.3
0.5
4.2
1.1
4.1
3.8
1
4.3
0.6
4.3
0.5
4.2
1.1
4.1
5.9
8.5
7.7
7.2
6.9
5.9
8.5
7.7
7.2
6.9
5
12.8
10.4
8
6.9
5
12.8
10.4
8
6.9
UNIT
ns
ns
ns
ns
ns
ns
tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
The enable time is a calculated value derived using the formula shown in the Enable Times section.
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7.10 Switching Characteristics: VCCA = 3.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 7)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
tPLH (1)
tPHL (1)
tPLH (1)
tPHL (1)
tPHZ (1)
tPLZ
(1)
tPHZ (1)
tPLZ (1)
tPZH (1) (2)
tPZL
(1) (2)
tPZH (1) (2)
tPZL (1) (2)
(1)
(2)
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.5
0.3
4.7
0.2
3.8
0.2
2.8
0.2
2.4
2.5
0.3
4.7
0.2
3.8
0.2
2.8
0.2
2.4
2.1
0.6
3.6
0.4
3.1
0.3
2.6
0.3
2.4
2.1
0.6
3.6
0.4
3.1
0.3
2.6
0.3
2.4
2.9
1.1
8
1
6.5
1.3
4.7
1.2
4
2.9
1.1
8
1
6.5
1.3
4.7
1.2
4
3.4
0.5
6.6
0.3
5.6
0.3
4.6
1.1
4.2
3.4
0.5
6.6
0.3
5.6
0.3
4.6
1.1
4.2
5.5
10.2
8.7
7.2
6.6
5.5
10.2
8.7
7.2
6.6
5.4
12.7
10.3
7.5
6.4
5.4
12.7
10.3
7.5
6.4
UNIT
ns
ns
ns
ns
ns
ns
tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
The enable time is a calculated value derived using the formula shown in the Enable Times section.
7.11 Operating Characteristics
TA = 25°C
PARAMETER
CpdA
CpdB
(1)
(2)
(1)
A-port input,
B-port output
B-port input,
A-port output
(1)
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0,
f = 10 MHz,
(2)
tr = tf (2) = 1 ns
CL = 0,
f = 10 MHz,
(2)
tr = tf (2) = 1 ns
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3
3
3
3
4
13
13
14
15
15
13
13
14
15
15
3
3
3
3
4
UNIT
pF
pF
Power dissipation capacitance per transceiver
tr: Rise time; tf: Fall time
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7.12 Typical Characteristics
6
6
5
5
4
4
tPHL (ns)
tPLH (ns)
7.12.1 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 1.8 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
0
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
0
10
20
30
40
VCCB = 1.8 V
1
VCCB = 2.5 V
50
60
0
10
20
CL (pF)
Figure 1. Typical A-to-B Propagation Delay, Low to High
30
CL (pF)
40
50
60
Figure 2. Typical A-to-B Propagation Delay, High to Low
7.12.2 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 2.5 V
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
tPHL (ns)
tPLH (ns)
4
3
3
2
2
1
1
0
0
0
10
20
30
40
50
60
0
10
20
CL (pF)
Figure 3. Typical A-to-B Propagation Delay, Low to High
30
CL (pF)
40
50
60
Figure 4. Typical A-to-B Propagation Delay, High to Low
7.12.3 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 3.3 V
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 3.3 V
4
tPHL - ns
tPLH - ns
4
3
3
2
2
1
1
0
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 3.3 V
0
10
20
30
40
50
60
0
0
CL - pF
Figure 5. Typical A-to-B Propagation Delay, Low to High
12
10
20
30
CL - pF
40
50
60
Figure 6. Typical A-to-B Propagation Delay, High to Low
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8 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH - VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 7. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
This dual-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB
and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation
and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits
data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when
the A-port outputs are activated.
The SN74AVCH2T45 features active bus-hold circuitry.
The DIR input is powered by supply voltage from VCCA.
This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance
state. This will prevent a false high or low logic being presented at the output.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
9.2 Functional Block Diagram
VCCB
VCCA
8
1
VCCB
VCCA
DIR
A1
5
2
7
A2
B1
3
6
B2
VCCB
VCCA
4 GND
14
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9.3 Feature Description
9.3.1 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance
state (IOZ shown in the Functional Block Diagram). This prevents false logic levels from being presented to either
bus.
9.3.2 2-Rail Design
Fully configurable 2-rail design allows each port to operate over the full 1.2 V to 3.6 V power-supply range.
9.3.3 IO Ports are 4.6 V Tolerant
The IO ports are up to 4.6 V tolerant
9.3.4 Partial Power Down Mode
This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
9.3.5 Bus Hold on Data Inputs
Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. TI does not recommend using
pull-up or pull-down resistors with the bus-hold circuitry.
9.4 Device Functional Modes
Table 1. Function Table (Each Transceiver)
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AVCH2T45 is used to shift IO voltage levels from one voltage domain to another. Each bus (bus A and
bus B) have independent power supplies, and a direction pin is used to control the direction of data flow.
10.2 Typical Applications
10.2.1 Unidirectional Logic Level-Shifting Application
Figure 8 is an example of the SN74AVCH2T45 circuit used in a unidirectional logic level-shifting application.
VCCA
VCCB
VCCA
VCCB
VCCA
A2
A1
GND
1
8
2
7
3
6
4
5
VCCB
B1
B2
VCCB
DIR
VCCA
SYSTEM-1
SYSTEM-2
Figure 8. Unidirectional Logic Level-Shifting Application
10.2.1.1 Design Requirements
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the
intended flow of data and take care not to violate any of the high or low logic levels. Active bus-hold circuitry
holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down
resistors with the bus-hold circuitry.
10.2.1.2 Detailed Design Procedure
Table 2 lists the pins and pin descriptions of the SN74AVCH2T45 connections with SYSTEM-1 and SYSTEM-2.
16
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Typical Applications (continued)
Table 2. SN74AVCH2T45 Pin Connections With SYSTEM-1 and SYSTEM-2
PIN
NAME
1
VCCA
DESCRIPTION
2
A1
Output level depends on VCCA.
3
A2
Output level depends on VCCA.
4
GND
Device GND
5
DIR
The GND (low-level) determines B-port to A-port direction.
6
B2
Input threshold value depends on VCCB.
7
B1
Input threshold value depends on VCCB.
8
VCCB
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
10.2.1.3 Application Curve
3.5
Input
Output
3
Magnitude (V)
2.5
2
1.5
1
0.5
0
-0.5
D002
Figure 9. 3.3- to 1.8-V Level-Shifting With 1-MHz Square Wave
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10.2.2 Bidirectional Logic Level-Shifting Application
Figure 10 shows the SN74AVCH2T45 used in a bidirectional logic level-shifting application. Because the
SN74AVCH2T45 does not have an output-enable (OE) pin, system designers should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCCA
VCCA
IO-1
VCCB
Pull-up/Pull-down
or Bus Hold
VCCB
Pull-up/Pull-down
or Bus Hold
VCCA
A2
A1
GND
1
8
2
7
3
6
4
5
IO-2
VCCB
B1
B2
DIR
DIR CTRL
SYSTEM-1
SYSTEM-2
Figure 10. Bidirectional Logic Level-Shifting Application
10.2.2.1 Design Requirements
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the
intended flow of data and take care not to violate any of the high or low logic levels. Active bus-hold circuitry
holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down
resistors with the bus-hold circuitry.
10.2.2.2 Detailed Design Procedure
Table 3 lists a sequence that shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2
to SYSTEM-1.
Table 3. Data Transmission Sequence
(1)
18
STATE
DIR CTRL
IO-1
IO-2
1
H
Output
Input
SYSTEM-1 data to SYSTEM-2
DESCRIPTION
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. IO-1 and IO-2 are
disabled.
The bus-line state depends on pull-up or pull-down. (1)
3
L
Hi-Z
Hi-Z
DIR bit is flipped. IO-1 and IO-2 still are disabled.
The bus-line state depends on pull-up or pull-down. (1)
4
L
Input
Output
SYSTEM-2 data to SYSTEM-1
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
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10.2.2.2.1 Enable Times
Calculate the enable times for the SN74AVCH2T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
(1)
(2)
(3)
(4)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH2T45 initially is transmitting from A to B, the
DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port
has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
10.2.2.3 Application Curve
Refer to Figure 9.
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11 Power Supply Recommendations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 4. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
< 0.5
< 0.5
< 0.5
< 0.5
< 0.5
1.2 V
< 0.5