www.ti.com
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
Output Voltage Translation Tracks VCC
Supports Mixed-Mode Signal Operation on All
Data I/O Ports
– 5-V Input Down to 3.3-V Output Level Shift
With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output Level
Shift With 2.5-V VCC
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron) Characteristics
(ron = 5 Ω Typ)
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 9 pF Typ)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 70 µA Max)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0-V to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Digital Applications: Level
Translation, PCI Interface, USB Interface,
Memory Interleaving, and Bus Isolation
Ideal for Low-Power Portable Equipment
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
DGG OR DGV PACKAGE
(TOP VIEW)
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
VCC
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
DESCRIPTION/ORDERING INFORMATION
The SN74CB3T16212 is a high-speed TTL-compatible FET bus-exchange switch, with low ON-state resistance
(ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data
I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16212 supports systems using 5-V TTL,
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
VCC
5.5 V
VCC
IN
VCC − 1 V
OUT
VCC
VCC − 1 V
CB3T
0V
0V
Input Voltages
Output Voltages
NOTE: If the input high-voltage (VIH) level is greater than or equal to VCC − 1 V and less than or equal to 5.5 V, the
output high-voltage (VOH) level is equal to approximately the VCC voltage level.
Figure 1. Typical DC Voltage Translation Characteristics
The SN74CB3T16212 operates as a 24-bit bus switch or as a 12-bit bus exchange that provides data
exchanging between four signal ports. The select (S0, S1, S2) inputs control the data path of the bus-exchange
switch. When the bus-exchange switch is ON, the A port is connected to the B port, allowing bidirectional data
flow between ports. When the bus-exchange switch is OFF, a high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, each select input should be tied to GND
through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
2
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP – DGG
Tape and reel
SN74CB3T16212DGGR
CB3T16212
TVSOP – DGV
Tape and reel
SN74CB3T16212DGVR
KR212
VFBGA – GQL
Tape and reel
SN74CB3T16212GQLR
VFBGA – ZQL (Pb-free)
Tape and reel
SN74CB3T16212ZQLR
KR212
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS
1
2
3
A
1A2
1A1
S0
B
3A1
2A2
2A1
C
4A1
GND
3A2
D
5A2
4A2
5A1
E
6A2
6A1
F
7A1
7A2
G
VCC
GND
8A1
H
8A2
9A1
9A2
J
10A1
10A2
K
11A2
12A1
4
5
6
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B2
4B1
5B1
5B2
6B1
7B1
6B2
8B1
GND
7B2
9B2
9B1
8B2
11A1
11B1
10B2
10B1
12A2
12B2
12B1
11B2
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
S2
S1
S0
L
L
L
L
L
H
L
L
H
H
H
L
H
FUNCTION
A1
A2
L
Z
Z
Disconnect
H
B1 port
Z
A1 port = B1 port
B2 port
Z
A1 port = B2 port
Z
B1 port
A2 port = B1 port
L
Z
B2 port
A2 port = B2 port
L
H
Z
Z
Disconnect
H
H
L
B1 port
B2 port
A1 port = B1 port
A2 port = B2 port
H
H
H
B2 port
B1 port
A1 port = B2 port
A2 port = B1 port
3
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1A1
2
54
SW
1B1
SW
SW
3
53
12A1
1B2
SW
1A2
27
30
SW
12B1
SW
SW
28
12A2
1
S0
56
S1
55
S2
4
29
SW
12B2
www.ti.com
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
B
VG (see Note A)
Control
Circuit
EN
(see Note B)
A.
Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON and VI > VCC + VT.
B.
EN is the internal enable signal applied to the switch.
ABSOLUTE MAXIMUM RATINGS (1)
over free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range (2)
–0.5
7
V
VIN
Control input voltage range (2) (3)
–0.5
7
V
VI/O
Switch I/O voltage range (2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±128
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (6)
Tstg
Storage temperature range
DGG package
64
DGV package
48
GQL/ZQL package
(1)
(2)
(3)
(4)
(5)
(6)
UNIT
°C/W
42
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output volrage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
MIN
MAX
UNIT
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS (1)
PARAMETER
TEST CONDITIONS
VIK
VCC = 3 V, II = –18 mA
VOH
See Figures 3 and 4
Control
inputs
IIN
TYP (2)
MIN
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
MAX
UNIT
–1.2
V
±10
µA
VI = VCC – 0.7 V to 5.5 V
±20
VI = 0.7 V to VCC – 0.7 V
–40
II
VCC = 3.6 V, VIN = VCC or GND, Switch ON
IOZ (3)
VCC = 3.6 V, VI = 0, VIN = VCC or GND, VO = 0 to 5.5 V, Switch OFF
Ioff
VCC = 0, VI = 0, VO = 0 to 5.5 V
±5
VI = 0 to 0.7 V
VCC = 3.6 V, VIN = VCC or GND, II/O = 0,
Switch ON or OFF
ICC
70
Cin
Control
inputs
VCC = 3.3 V, VIN = VCC or GND
VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0
rON (5)
VCC = 3 V, VI = 0
(1)
(2)
(3)
(4)
(5)
300
VCC = 3.3 V, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF
VCC = 3.3 V, VIN = VCC or GND, Switch ON
µA
VI = 5.5 V
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
Cio(ON)
µA
10
70
Control
inputs
Cio(OFF)
±10
VI = VCC or GND
∆ICC (4)
µA
VI/O = 5.5 V or 3.3 V
µA
µA
4
pF
9
pF
8
pF
VI/O = GND
23
IO = 24 mA
5
9.5
IO = 16 mA
5
9.5
IO = 64 mA
5
8.5
IO = 32 mA
5
8.5
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current throught the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (see Figure 2)
(1)
6
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
tpd(s)
S
A
1
15.5
1
ten
S
B
1
15
tdis
S
B
1
12
PARAMETER
MIN
MAX
MIN
0.15
UNIT
MAX
0.25
ns
11.5
ns
1
12
ns
1
10.5
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capaitance, when driven by an ideal voltage source (zero output impedance).
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
50 Ω
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
VOL + V∆
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
GND
CL
(see Note A)
50 Ω
VG2
S1
RL
VO
VI
Output
Waveform 2
S1 at Open
(see Note B)
tPHZ
VOH
VCC/2
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
7
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs INPUT VOLTAGE
OUTPUT VOLTAGE vs INPUT VOLTAGE
4.0
VCC = 2.3 V
IO = 1 µA
TA = 25°C
3.0
V − Output Voltage − V
O
V − Output Voltage − V
O
4.0
2.0
1.0
0.0
VCC = 3 V
IO = 1 µA
TA = 25°C
3.0
2.0
1.0
0.0
0.0
1.0
2.0
4.0
3.0
VI − Input Voltage − V
6.0
5.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VI − Input Voltage − V
Figure 3. Data Output Voltage vs Data Input Voltage
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
3.5
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 85°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
3.5
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 25°C
8 mA
16 mA
24 mA
3.0
2.5
2.0
2.5
2.7
2.9
3.1
3.3
VCC − Supply Voltage − V
3.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
VCC − Supply Voltage − V
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
V
− Output Voltage High − V
OH
4.0
3.5
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = -40°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
3.3
2.7
2.9
3.1
VCC − Supply Voltage − V
Figure 4. VOH Values
8
100 µA
1.5
1.5
2.3
V
− Output Voltage High − V
OH
V
− Output Voltage High − V
OH
4.0
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4.0
3.5
3.7
3.5
3.7
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74CB3T16212DGGR
ACTIVE
TSSOP
DGG
56
SN74CB3T16212ZQLR
OBSOLETE
BGA
MICROSTAR
JUNIOR
ZQL
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
TBD
Call TI
Call TI
-40 to 85
CB3T16212
KR212
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of