74CBTLV16211CZRDR

        

 SCDS204 − JULY 2005 D Member of the Texas Instruments D D D D Latch-Up Performance Exceeds 250 mA Per Widebus Family 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation D JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) description/ordering information The SN74CBTLV16211C provides 24 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as dual 12-bit bus switches with separate output-enable (OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA VFBGA − GRD Tape and reel 74CBTLV16211CGRDR VFBGA − ZRD (Pb-free) Tape and reel 74CBTLV16211CZRDR TOP-SIDE MARKING CN211 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated     !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
        

 SCDS204 − JULY 2005 GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A 1A2 1A1 NC 2OE 1B1 1B2 B B 1A4 1A3 1A7 1OE 1B3 1B4 C C 1A6 1A5 GND 1B7 1B5 1B6 D D 1A10 1A9 1A8 1B8 1B9 1B10 E E 1A12 1A11 2A1 2B1 1B11 1B12 F 2A4 2A3 2A2 2B2 2B3 2B4 G 2A6 2A5 GND 2B5 2B6 2B9 2B7 2B8 2B10 2B11 2B12 F G H J H 2A8 2A7 VCC 2A9 J 2A12 2A11 2A10 NC − No internal connection FUNCTION TABLE (each 12-bit bus switch) INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 1A1 SW 1B1 1A12 SW 1B12 2A1 SW 2B1 2A12 SW 2B12 1OE 2OE 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
        

 SCDS204 − JULY 2005 simplified schematic, each FET switch B A (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): GRD/ZRD package . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 UNIT V 1.7 V 2 0.7 0.8 V TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
        

 SCDS204 − JULY 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 3 V, VCC = 3.6 V, II = −18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VCC = 3.6 V, VI = 3.3 V or 0 One input at 3 V, VO = 3.3 V or 0, OE = VCC ∆ICC‡ Control inputs Ci Control inputs Cio(OFF) MIN TYP† VI = VCC or GND Other inputs at VCC or GND MAX UNIT −1.2 V ±1 µA 10 µA 10 µA 300 µA 4.5 VCC = 2.3 V, TYP at VCC = 2.5 V ron§ VCC = 3 V pF 6.5 pF 5 8 VI = 0 II = 64 mA II = 24 mA 5 8 VI = 1.7 V, II = 15 mA 27 40 5 7 VI = 0 II = 64 mA II = 24 mA 5 7 Ω VI = 2.4 V, II = 15 mA 10 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A ten OE A or B PARAMETER VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V MAX MIN 0.15 0.5 6 0.5 UNIT MAX 0.25 ns 5.2 ns tdis OE A or B 0.5 6.2 0.5 6.7 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
        

 SCDS204 − JULY 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ±0.2 V 3.3 V ±0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V t Output PZL Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL VCC Output Control tPLZ VCC VCC/2 VOL + V∆ VOL tPHZ tPZH VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 13-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) 74CBTLV16211CGRDR ACTIVE BGA MI CROSTA R JUNI OR GRD 54 1000 74CBTLV16211CZRDR ACTIVE BGA MI CROSTA R JUNI OR ZRD 54 1000 Green (RoHS & no Sb/Br) Package Type Package Drawing Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish MSL Peak Temp (3) SNPB Level-1-240C-UNLIM SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74CBTLV16211CGRDR BGA MI CROSTA R JUNI OR GRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 74CBTLV16211CZRDR BGA MI CROSTA R JUNI OR ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74CBTLV16211CGRDR BGA MICROSTAR JUNIOR GRD 54 1000 333.2 345.9 28.6 74CBTLV16211CZRDR BGA MICROSTAR JUNIOR ZRD 54 1000 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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