74GTLPH16927VRE4

SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • • • • DGG OR DGV PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels GTLP Buffered SYSCLK Signal (SSCLK) for Source-Synchronous Applications LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DIR OE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLKOUT CKOE 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 FSTA BIAS VCC B1 GND B2 B3 VREF B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 CMS B16 B17 GND B18 SSCLK SYSCLK DESCRIPTION/ORDERING INFORMATION The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer. Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous and clock-synchronous applications. Source-synchronous applications require the skew between the clock output and data output to be minimized for optimum maximum-frequency system performance. In order to reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the device. ORDERING INFORMATION TA –40°C to 85°C (1) PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLPH16927GR GTLPH16927 TVSOP – DGV Tape and reel SN74GTLPH16927VR GL927 VFBGA – GQL Tape and reel SN74GTLPH16927KR GL927 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, TI-OPC, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2005, Texas Instruments Incorporated SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The system clock (SYSCLK) and CLKOUT pins are LVTTL compatible, while the source-synchronous I/O is GTLP compatible. The benefits include compensation for output-to-output skew coming from the driver itself, and compensation for process skew if more than one driver is used. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (