SN74LVC1G3157
SCES424M – JANUARY 2003 – REVISED AUGUST 2022
SN74LVC1G3157 Single-Pole Double-Throw Analog Switch
1 Features
3 Description
•
This single channel single-pole double-throw (SPDT)
analog switch is designed for 1.65-V to 5.5-V VCC
operation.
•
•
•
•
•
•
•
•
ESD protection exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
1.65-V to 5.5-V VCC operation
Qualified for 125°C operation
Specified break-before-make switching
Rail-to-rail signal handling
Operating frequency typically 340 MHz at room
temperature
High speed, typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
Low ON-state resistance, typically ≉6 Ω
(VCC = 4.5 V)
Latch-up performance exceeds 100 mA Per JESD
78, class II
The SN74LVC1G3157 device can handle both analog
and digital signals. The SN74LVC1G3157 device
permits signals with amplitudes of up to VCC (peak)
to be transmitted in either direction.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-analog
conversion systems.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
•
•
•
•
Wearables and mobile devices
Portable computing
Internet of things (IoT)
Audio signal routing
Remote radio unit
Portable medical equipment
Surveillance
Home automation
I2C/SPI/UART bus multiplexing
Wireless charging
SN74LVC1G3157
(1)
PACKAGE
BODY SIZE (NOM)
SOT-23 (DBV) (6)
2.90 mm × 1.60 mm
SC70 (DCK) (6)
2.00 mm × 1.25 mm
SOT (DRL) (6)
1.60 mm × 1.20 mm
SON (DRY) (6)
1.45 mm × 1.00 mm
DSBGA (YZP) (6)
1.41 mm × 0.91 mm
SON (DSF) (6)
1.00 mm × 1.00 mm
X2SON (DTB) (6)
0.80 mm × 1.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1
B2
4
6
S
B1
A
3
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G3157
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SCES424M – JANUARY 2003 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Analog Switch Characteristics.................................... 9
6.7 Switching Characteristics 85°C.................................10
6.8 Switching Characteristics 125°C...............................10
6.9 Typical Characteristics.............................................. 10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................16
9 Application and Implementation.................................. 17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................19
11 Layout........................................................................... 19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Documentation Support.......................................... 20
12.2 Receiving Notification of Documentation Updates..20
12.3 Support Resources................................................. 20
12.4 Trademarks............................................................. 20
12.5 Electrostatic Discharge Caution..............................20
12.6 Glossary..................................................................20
13 Mechanical, Packaging, and Orderable
Information.................................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (May 2017) to Revision M (August 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Pin Configuration and Functions section........................................................................................4
• Updated the equation in the Detailed Design Procedure section..................................................................... 18
Changes from Revision K (January 2017) to Revision L (May 2017)
Page
• Deleted Feature "Useful for Both Analog and Digital Applications" ................................................................... 1
• Deleted Feature "High Degree of Linearity" .......................................................................................................1
• Changed the first sentence of the Description From: "This single-pole double-throw (SPDT)..." To: "This single
channel single pole double-throw (SPDT)..." ..................................................................................................... 1
• Added the X2SON (DTB) package to the Device Information ........................................................................... 1
• Added the X2SON (DTB) Package, to the Pin Configuration and Functions .................................................... 4
• Changed II/O To: II/OK for I/O port diode current in the Absolute Maximum Ratings ...........................................6
• Added the DTB (X2SON) package to the Thermal Information table................................................................. 7
• Changed Note 1 and Note 2 n the Analog Switch Characteristics table.............................................................9
• Deleted Note 3 "Specified by design" from the Analog Switch Characteristics tables........................................9
• Deleted Note 4 "Specified by design" from the Switch Characteristics 85°C tables.........................................10
• Deleted Note 4 "Specified by design" from the Switch Characteristics 125°C tables.......................................10
• Changed Figure 7-2, From: SW1 = VIL to SW1 = VIH, From: SW2 = VIH to: SW2 = VIL .................................. 11
• Changed Figure 7-5 ......................................................................................................................................... 11
• Added a series 50-Ω resistor on B1 in Figure 7-6 ............................................................................................11
• Changed Figure 7-7 ......................................................................................................................................... 11
Changes from Revision J (June 2016) to Revision K (January 2017)
Page
• Added new applications to Applications section ................................................................................................ 1
• Added Operating free-air temperature, TA for BGA and all other packages in Recommended Operating
Conditions ..........................................................................................................................................................7
• Added 125°C data to Electrical Characteristics table. ....................................................................................... 8
• Added 85°C to title to differentiate from new 125°C Switching Characteristics section. ..................................10
2
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•
SN74LVC1G3157
SCES424M – JANUARY 2003 – REVISED AUGUST 2022
Added 125°C Switching Characteristics section and data. ..............................................................................10
Changes from Revision I (June 2015) to Revision J (June 2016)
Page
• Deleted 200-V Machine Model (A115-A) from Features ....................................................................................1
• Changed Feature From: "Operating Frequency Typically 300 MHz at Room Temperature" To: "Operating
Frequency Typically 340 MHz at Room Temperature"........................................................................................1
• Updated Device Information table...................................................................................................................... 1
• Updated pinout images for all Packages............................................................................................................ 4
• Added temperature ranges for Storage temperature, Tstg and Junction temperature, TJ in Absolute Maximum
Ratings ...............................................................................................................................................................6
• Changed MAX value ±1 to ±0.1 for Ioff and IIN in Electrical Characteristics table............................................... 8
• Added Receiving Notification of Documentation Updates section....................................................................20
Changes from Revision H (May 2012) to Revision I (June 2015)
Page
• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................1
• Updated Features............................................................................................................................................... 1
Changes from Revision G (September 2011) to Revision H (May 2012)
Page
• Changed YZP with correct pin labels. ................................................................................................................4
• Added Thermal Information table....................................................................................................................... 7
• Changed to correct Pin Label "S"....................................................................................................................... 8
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5 Pin Configuration and Functions
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
Not to scale
Not to scale
Figure 5-1. DBV Package, 6-Pin SOT-23 (Top View)
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
Figure 5-2. DCK Package, 6-Pin SC70 (Top View)
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
Not to scale
Figure 5-4. DRL Package, 6-Pin SOT (Top View)
Not to scale
Figure 5-3. DRY Package, 6-Pin SON (Top View)
B2
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
1
2
GND
B1
Not to scale
Figure 5-5. DSF Package, 6-Pin SON (Top View)
6
3
5
S
VCC
4
A
Figure 5-6. DTB Package, 6-Pin X2SON (Top View)
Table 5-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
B2
1
I/O
GND
2
P
B1
3
I/O
Switch I/O. Set S low to enable.
A
4
I/O
Common terminal
VCC
5
P
Power supply
S
6
I
Select
(1)
4
SOT-23, SC70, SON,
X2SON, or SOT
Switch I/O. Set S high to enable.
Ground
I = input, O = output, P = power
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1
2
C
B1
A
B
GND
A
B2
V
CC
S
Not to scale
Figure 5-7. YZP Package, 6-Pin DSBGA (Bottom View)
Legend
Input
Input or Output
Power
Table 5-2. Pin Functions
PIN
NO.
NAME
A1
B2
TYPE(1)
I/O
DESCRIPTION
Switch I/O. Set S high to enable.
A2
S
I
Select
B1
GND
P
Ground
B2
VCC
P
Power supply
C1
B1
I/O
Switch I/O. Set S low to enable.
C2
A
I/O
Common terminal
(1)
I = input, O = output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage(2)
VCC
voltage(2) (3)
MIN
MAX
UNIT
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
VIN
Control input
VI/O
Switch I/O voltage(2) (3) (4) (5)
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port diode current
VI/O < 0 or VI/O > VCC
±50
mA
II/O
On-state switch
current(6)
VI/O = 0 to VCC
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
(6)
–65
±128
mA
±100
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
II, IO, IA, and IBn are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±2000
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VCC
Supply voltage
VI/O
Switch input or output voltage
VIN
Control input voltage
VIH
High-level input voltage, control input
VIL
Low-level input voltage, control input
Δt/Δv
TA
(1)
VCC = 1.65 V to 1.95 V
5.5
V
0
VCC
V
0
5.5
V
V
VCC × 0.7
VCC = 1.65 V to 1.95 V
VCC × 0.25
VCC = 2.3 V to 5.5 V
Operating free-air temperature
UNIT
1.65
VCC × 0.75
VCC = 2.3 V to 5.5 V
Input transition rise or fall rate
MAX
VCC × 0.3
VCC = 1.65 V to 1.95 V
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
VC C = 4.5 V to 5.5 V
10
V
ns/V
BGA package (YZP)
–40
85
°C
All other packages (DBV, DCK,
DRL, DRY, DSF)
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LVC1G3157
THERMAL METRIC(1)
DBV (SOT-23)
DCK (SC70)
DRL (SOT)
DRY (SON)
DTB
(X2SON)
YZP
(DSBGA)
UNIT
6 PINS
6 PINS
6 PINS
6 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
234.9
269.5
244.1
284.2
324.5
129.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
150.4
189.5
112.5
138.6
150.5
1.9
°C/W
RθJB
Junction-to-board thermal resistance
86.4
84.7
109.9
170.9
239.0
40.0
°C/W
ψJT
Junction-to-top characterization
parameter
60.8
62.7
9.3
13.7
17.2
0.6
°C/W
ψJB
Junction-to-board characterization
parameter
86.1
84.0
109.3
167.9
238.3
40.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
n/a
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
rrange
Δron
ron(flat)
See Figure 6-1
and Figure 7-1
ON-state switch resistance(2)
ON-state switch resistance over
signal range(2) (3)
Difference of ON-state
resistance between switches(2) (4) (5)
ON resistance flatness(2) (4) (6)
VI = 0 V
IO = 4 mA
VI = 1.65 V
IO = –4 mA
VI = 0 V
IO = 8 mA
VI = 2.3 V
IO = –8 mA
VI = 0 V
IO = 24 mA
VI = 3 V
IO = –24 mA
VI = 0 V
IO = 30 mA
VI = 2.4 V
IO = –30 mA
VI = 4.5 V
IO = –30 mA
0 ≤ VBn ≤ VCC
(see Figure 6-1 and Figure 7-1)
See Figure 7-1
VCC
1.65 V
2.3 V
3V
4.5 V
TA = -40 to 85°C
MIN
TYP(1)
TA = -40 to 125°C
MAX
MIN
TYP(1)
11
20
11
20
15
50
15
50
8
12
8
12
11
30
11
30
7
9
7
9
9
20
9
20
6
7
6
7
7
12
7
12
15
7
7
1.65 V
140
140
IA = –8 mA
2.3 V
45
45
IA = –24 mA
3V
18
18
IA = –30 mA
4.5 V
IA = –4 mA
1.65 V
0.5
0.5
VBn = 1.6 V
IA = –8 mA
2.3 V
0.1
0.3
VBn = 2.1 V
IA = –24 mA
3V
0.1
0.3
VBn = 3.15 V
IA = –30 mA
4.5 V
0.1
0.2
IA = –4 mA
1.65 V
110
110
IA = –8 mA
2.3 V
26
40
IA = –24 mA
3V
9
10
IA = –30 mA
4.5 V
4
Ω
Ω
10
Ω
Ω
5
±1
±1
OFF-state switch leakage current
0 ≤ VI, VO ≤ VCC
(see Figure 7-2 )
IS(on)
ON-state switch leakage current
VI = VCC or GND, VO = Open
(see Figure 7-3)
IIN
Control input current
0 ≤ VIN ≤ VCC
ICC
Supply current
S = VCC or GND
5.5 V
ΔICC
Supply-current change
S = VCC – 0.6 V
5.5 V
Ci
Control input capacitance
S
5V
2.7
2.7
pF
Cio(off)
Switch input/output
capacitance
Bn
5V
5.2
5.2
pF
Cio(on)
Switch input/output
capacitance
17.3
17.3
17.3
17.3
(3)
(4)
(5)
(6)
(7)
Bn
A
1.65 V to
5.5 V
10
UNIT
15
IA = –4 mA
VBn = 1.15 V
0 ≤ VBn ≤ VCC
MAX
Ioff (7)
(1)
(2)
8
TEST CONDITIONS
±0.05
5.5 V
0 V to 5.5
V
5V
±0.1(1)
±0.05
±1
±1
±0.1(1)
±0.1(1)
±1
±0.05
1
±0.1
±0.1(1)
±1
±0.05
±0.1
µA
µA
µA
10
35
µA
500
500
µA
pF
TA = 25°C
Measured by the voltage drop between I/O pins at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages on the two (A or B) ports.
Specified by design
Δron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels
This parameter is characterized, but not production tested.
Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of
conditions.
Ioff is the same as IS(off) (off-state switch leakage current).
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6.6 Analog Switch Characteristics
TA = 25°C
PARAMETER
Frequency
(switch on)
response(1)
Crosstalk(2)
(between switches)
Feed through
attenuation(2)
(switch off)
Charge injection
Total harmonic distortion
(1)
(2)
FROM
(INPUT)
A or Bn
B1 or B2
A or Bn
S
A or Bn
TO
(OUTPUT)
Bn or A
B2 or B1
Bn or A
A
Bn or A
TEST CONDITIONS
RL = 50 Ω, fin = sine wave
(see Figure 7-5)
RL = 50 Ω, fin = 10 MHz (sine wave)
(see Figure 7-6)
CL = 5 pF, RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 7-7)
CL = 0.1 nF, RL = 1 MΩ
(see Figure 7-8)
VI = 0.5 Vp-p, RL = 600 Ω,
fin = 600 Hz to 20 kHz (sine wave)
(see Figure 7-9)
VCC
TYP
1.65 V
340
2.3 V
340
3V
340
4.5 V
340
1.65 V
–54
2.3 V
–54
3V
–54
4.5 V
–54
1.65 V
–57
2.3 V
–57
3V
–57
4.5 V
–57
3.3 V
3
5V
7
1.65 V
0.1%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
UNIT
MHz
dB
dB
pC
Set fin to 0 dBm and provide a bias of 0.4 V. Increase fin frequency until the gain is 3 dB below the insertion loss.
Set fin to 0 dBm and provide a bias of 0.4 V.
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6.7 Switching Characteristics 85°C
TA = –40 to +85°C (see Figure 7-4 and )Figure 7-10
PARAMETER
tpd (1)
ten
FROM
(INPUT)
TO
(OUTPUT)
A or Bn
Bn or A
S
Bn
VCC = 2.5 V
± 0.2 V
MAX
MIN
VCC = 3.3 V
± 0.3 V
MAX
2
tB-M
(2)
(3)
MIN
(2)
tdis (3)
(1)
VCC = 1.8 V
± 0.15 V
MIN
VCC = 5 V
± 0.5 V
MAX
1.2
MIN
0.8
UNIT
MAX
0.3
7
24
3.5
14
2.5
7.6
1.7
5.7
3
13
2
7.5
1.5
5.3
0.8
3.8
0.5
0.5
0.5
0.5
ns
ns
ns
tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical ON-state resistance of the switch
and the specified load capacitance when driven by an ideal voltage source (zero output impedance).
ten is the slower of tPZL or tPZH.
tdis is the slower of tPLZ or tPHZ.
6.8 Switching Characteristics 125°C
TA = –40 to +125°C (see Figure 7-4 and Figure 7-10)
PARAMETER
tpd (1)
ten (2)
tdis (3)
FROM
(INPUT)
TO
(OUTPUT)
A or Bn
Bn or A
S
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
1
2.5
tB-M
MAX
24.5
1
14.5
2.5
8
1.7
6
13.5
2
8
1.5
5.5
0.8
4
1.2
MIN
UNIT
MAX
0.5
MIN
VCC = 5 V
± 0.5 V
MIN
2
Bn
VCC = 3.3 V
± 0.3 V
0.8
0.5
0.5
MAX
0.5
0.5
ns
ns
ns
6.9 Typical Characteristics
120
VCC = 1.65 V
100
ron
80
60
40
VCC = 2.3 V
20
VCC = 3 V
VCC = 4.5 V
0
0
1
2
3
4
5
VI - V
Figure 6-1. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
10
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7 Parameter Measurement Information
ron =
VI – V O
Ω
IO
Figure 7-1. ON-State Resistance Test Circuit
VCC
VCC
SW
S
1
VIH
2
VIL
S
VIL or VIH
1
B1
SW
VO
B2
2
VI
A
A
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 7-2. OFF-State Switch Leakage-Current Test Circuit
VCC
VIL or VIH
S
VCC
B1
VI
A
S
1
VIL
2
VIH
1
SW
B2
SW
2
VO
VO = Open
A
GND
VI = VCC or GND
Figure 7-3. ON-State Switch Leakage-Current Test Circuit
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VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
50 pF
50 pF
50 pF
50 pF
500 W
500 W
500 W
500 W
0.3 V
0.3 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-4. Load Circuit and Voltage Waveforms
12
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VCC
SW
S
1
VIL
2
VIH
VCC
S
VIL or VIH
1
B1
SW
VO
B2
2
50
RL = 50
A
fin
GND
Figure 7-5. Frequency Response (Switch On)
VCC
VCC
B1
50
VB1
S
VIL or VIH
S
TEST CONDITION
VIL
20log10(VO2/VI)
VIH
20log10(VO1/VI)
fin
1
VB2
B2
Analyzer
2
RL = 50
GND
Figure 7-6. Crosstalk (Between Switches)
VCC
VCC
SW
S
1
VIL
2
VIH
S
VIL or VIH
B1
1
SW
Analyzer
B2
2
50
RL = 50
A
fin
GND
Figure 7-7. Feed Through
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VCC
VCC
S
B1
LOGIC
INPUT
1
RGEN
SW
B2
2
VGE
A
VOUT
GND
RL
CL
RL/CL = 1 MΩ/100 pF
LOGIC
INPUT
OFF
ON
OFF
∆VOUT
VOUT
Q = (∆VOUT) (CL)
Figure 7-8. Charge-Injection Test
10 kΩ
600 Ω
Figure 7-9. Total Harmonic Distortion
14
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VCC
VCC
S
B1
VI = VCC/2
B2
VO
A
GND
VS
RL
CL
RL/CL = 50 Ω/35 pF
VO
0.9 x VO
tD
Figure 7-10. Break-Before-Make Internal Timing
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8 Detailed Description
8.1 Overview
The SN74LVC1G3157 device is a single-pole double-throw (SPDT) analog switch designed for 1.65-V to 5.5-V
VCC operation. The SN74LVC1G3157 device can handle analog and digital signals. The device permits signals
with amplitudes of up to VCC (peak) to be transmitted in either direction.
8.2 Functional Block Diagram
B2
1
6
4
S
B1
A
3
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
The 1.65-V to 5.5-V supply operation allows the device to function in many different systems comprised of
different logic levels, allowing rail-to-rail signal switching. Either the B1 channel or the B2 channel is activated
depending upon the control input. If the control input is low, B1 channel is selected. If the control input is high, B2
channel is selected.
8.4 Device Functional Modes
Table 8-1 lists the ON channel when one of the control inputs is selected.
Table 8-1. Function Table
16
CONTROL
INPUTS
ON
CHANNEL
L
B1
H
B2
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G3157 SPDT analog switch is flexible enough for use in a variety of circuits such as
analog audio routing, power-up monitor, memory sharing, and so on. For details on the applications, see
SN74LVC1G3157 and SN74LVC2G53 SPDT Analog Switches.
9.2 Typical Application
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
The inputs can be analog or digital, but TI recommends waiting until VCC has ramped to a level in Section 6.3
before applying any signals. Appropriate termination resistors should be used depending on the type of signal
and specification. The Select pin should not be left floating; either pull up or pull down with a resistor that can be
overdriven by a GPIO.
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9.2.2 Detailed Design Procedure
Using this circuit idea, a system designer can ensure a component or subsystem power has ramped up before
allowing signals to be applied to its input. This is useful for integrated circuits that do not have overvoltage
tolerant inputs. The basic idea uses a resistor divider on the VCC1 power rail, which is ramping up. The RC
time constant of the resistor divider further delays the voltage ramp on the select pin of the SPDT bus switch.
By carefully selecting values for R1, R2, and C, it is possible to ensure that VCC1 will reach its nominal value
before the path from A to B2 is established, thus preventing a signal being present on an I/O before the device/
system is powered up. To ensure the minimum desired delay is achieved, the designer should use Equation 1 to
calculate the time required from a transition from ground (0 V) to half the supply voltage (VCC1/2).
R2
VCC1 VIH of the select pin
Set
R1 + R2
(1)
Choose Rs and C to achieve the desired delay.
When VS goes high, the signal will be passed.
9.2.3 Application Curve
Figure 9-2. VS Voltage Ramp
18
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10 Power Supply Recommendations
Most systems have a common 3.3-V or 5-V rail that can supply the VCC pin of this device. If this is not available,
a Switch-Mode-Power-Supply (SMPS) or a Linear Dropout Regulator (LDO) can be used to provide supply to
this device from another voltage rail.
11 Layout
11.1 Layout Guidelines
TI recommends keeping signal lines as short as possible. TI also recommends incorporating microstrip or
stripline techniques when signal lines are greater than 1 inch in length. These traces must be designed with a
characteristic impedance of either 50 Ω or 75 Ω, as required by the application. Do not place this device too
close to high-voltage switching components, as they may interfere with the device.
11.2 Layout Example
Figure 11-1. Recommended Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs
Texas Instruments, SN74LVC1G3157 and SN74LVC2G53 SPDT Analog Switches
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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8-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74LVC1G3157DBVRE4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(CC5F, CC5R)
Samples
74LVC1G3157DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(CC5F, CC5R)
Samples
74LVC1G3157DCKRE4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C55, C5F, C5J, C5
K, C5R)
Samples
74LVC1G3157DCKRG4
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C55, C5F, C5J, C5
K, C5R)
Samples
74LVC1G3157DRYRG4
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C5
Samples
SN74LVC1G3157DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CC55, CC5F, CC5K,
CC5R)
Samples
SN74LVC1G3157DCK3
ACTIVE
SC70
DCK
6
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 125
C5Z
Samples
SN74LVC1G3157DCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C55, C5F, C5J, C5
K, C5R)
Samples
SN74LVC1G3157DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(C57, C5R)
Samples
SN74LVC1G3157DRY2
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
C5
Samples
SN74LVC1G3157DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
C5
Samples
SN74LVC1G3157DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
C5
Samples
SN74LVC1G3157DTBR
ACTIVE
X2SON
DTB
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7X
Samples
SN74LVC1G3157YZPR
ACTIVE
DSBGA
YZP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C5N
Samples
(1)
NIPDAU
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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