74LVC1G3208MDBVTEP

SN74LVC1G3208-EP www.ti.com SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 SINGLE 3-INPUT POSITIVE OR-AND GATE Check for Samples: SN74LVC1G3208-EP FEATURES 1 • • • • • • SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5 ns at 3.3 V Low Power Consumption, 12.5-μA Max ICC ±24-mA Output Drive at 3.3 V Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V) Can Be Used in Three Combinations: – OR-AND Gate – OR Gate – AND Gate Ioff Supports Partial-Power-Down Mode Operation • • • • • • • • • Controlled Baseline One Assembly and Test Site One Fabrication Site Available in Military (-55°C to 125°C) Temperature Ranges (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability DBV PACKAGE (TOP VIEW) (1) A 1 6 C GND 2 5 VCC B 3 4 Y Custom temperature ranges available DESCRIPTION/ORDERING INFORMATION This device is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G3208 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅ C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208 offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ⋅ C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅ C). This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Table 1. ORDERING INFORMATION (1) TA –55°C to 125°C (1) PACKAGE SOT (SOT-23) – DBV Reel of 250 ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER 74LVC1G3208MDBVTEP CDD5M V62/13605-01XE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated SN74LVC1G3208-EP SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 www.ti.com FUNCTION TABLE (1) INPUTS B C OUTPUT Y H X H H X H H H X X L L L L H L A (1) X = Valid H or L LOGIC DIAGRAM (POSITIVE LOGIC) A B 1 3 4 C Y 6 FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE 2-Input AND Gate 1 2-Input OR Gate 2 Y = (A + B) ⋅ C 3 LOGIC CONFIGURATIONS VCC B VCC A Y C B 1 6 2 5 3 4 C Y C Y A 1 6 2 5 3 4 C Y Figure 1. 2-Input AND Gate VCC A B Y A B 1 6 2 5 3 4 Y Figure 2. 2-Input OR Gate 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP SN74LVC1G3208-EP www.ti.com SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 VCC A B A Y C B 1 6 2 5 3 4 C Y Figure 3. Y = (A + B) ⋅ C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C (3) Continuous current through VCC or GND Tstg (1) (2) (3) Storage temperature range –65 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. THERMAL INFORMATION SN74LVC1G3208 THERMAL METRIC (1) DBV UNITS 6 PINS θJA Junction-to-ambient thermal resistance (2) θJCtop Junction-to-case (top) thermal resistance (3) 148.1 θJB Junction-to-board thermal resistance (4) 50.6 207 (5) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (6) 50.1 θJCbot Junction-to-case (bottom) thermal resistance (7) N/A (1) (2) (3) (4) (5) (6) (7) 41.2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP 3 SN74LVC1G3208-EP SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 www.ti.com Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 UNIT V 0.65 × VCC 1.7 V 2 0.7 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 4.5 V to 5.5 V 1.4 VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current V –8 VCC = 3 V –16 mA –24 VCC = 4.5 V IOL Low-level output current –32 VCC = 1.65 V 4 VCC = 2.3 V 8 VCC = 3 V 16 mA 24 Δt/Δv Input transition rise or fall rate VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA (1) 4 Operating free-air temperature ns/V 5 –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP SN74LVC1G3208-EP www.ti.com SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.11 IOL = 4 mA 1.65 V 0.52 IOL = 8 mA 2.3 V 0.45 IOL = 32 mA II 0.68 VI = 5.5 V or GND 1.1 0 to 5.5 V VI or VO = 5.5 V ICC VI = 5.5 V or GND IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND V 1.1 4.5 V Ioff (1) 3.8 3V IOL = 24 mA A, B, or C inputs 2.3 IOH = –32 mA IOL = 16 mA UNIT V 2.4 3V IOH = –24 mA MAX VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN TYP (1) VCC -12.05 8.6 μA -22 41.5 μA 1.65 V to 5.5 V 12.5 μA 3 V to 5.5 V 500 μA 0 3.3 V 3.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. xxx Estimated Life (Years) 100.00 10.00 1.00 85 105 125 150 Continuous T J (°C) (1) See datasheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) Enhanced plastic product disclaimer applies. Figure 4. 74LVC1G3208-EP Operating Life Derating Chart Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP 5 SN74LVC1G3208-EP SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 www.ti.com Switching Characteristics only valid for -40°C to 85°C, CL = 15 pF (unless otherwise noted) (see Figure 5) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A, B, or C Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3.7 14 2.5 7 1.7 5 1.3 3.4 ns Switching Characteristics only valid for -40°C to 85°C, CL = 30pF or 50 pF (unless otherwise noted) (see Figure 6) FROM (INPUT) TO (OUTPUT) A, B, or C Y PARAMETER tpd VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.5 17.5 1.8 7.6 1.8 5.9 1.3 4.0 UNIT ns Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6) FROM (INPUT) TO (OUTPUT) A, B, or C Y PARAMETER tpd VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX 17.5 VCC = 3.3 V ± 0.3 V MIN 7.6 MAX VCC = 5 V ± 0.5 V MIN UNIT MAX 5.9 4.5 ns Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 15 15 16 17 Submit Documentation Feedback UNIT pF Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP SN74LVC1G3208-EP www.ti.com SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 5. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP 7 SN74LVC1G3208-EP SCES846A – JANUARY 2013 – REVISED FEBRAURY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 6. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3208-EP PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 74LVC1G3208MDBVTEP ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CDD5M V62/13605-01XE ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CDD5M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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OTHER QUALIFIED VERSIONS OF SN74LVC1G3208-EP : Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 • Catalog: SN74LVC1G3208 • Automotive: SN74LVC1G3208-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing 74LVC1G3208MDBVTEP SOT-23 DBV 6 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 9.2 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.2 1.55 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVC1G3208MDBVTEP SOT-23 DBV 6 250 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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