8V182512IDGGREP

   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D D D D D Compatible With the IEEE Std 1149.1-1990 − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Members of the Texas Instruments SCOPE  Family of Testability Products Members of the Texas Instruments Widebus  Family State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors B-Port Outputs of SN74LVTH182512 Device Has Equivalent 25-Ω Series Resistors, So No External Resistors Are Required SCOPE  Instruction Set − IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ − Parallel-Signature Analysis at Inputs − Pseudo-Random Pattern Generation From Outputs − Sample Inputs/Toggle Outputs − Binary Count From Outputs − Device Identification − Even-Parity Opcodes (JTAG) Test Access Port and Boundary-Scan Architecture DGG PACKAGE (TOP VIEW) 1CLKAB 1LEAB 1OEAB 1A1 1A2 GND 1A3 1A4 1A5 VCC 1A6 1A7 1A8 GND 1A9 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 2A9 GND 2OEAB 2LEAB 2CLKAB TDO TMS 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 1CLKBA 1LEBA 1OEBA 1B1 1B2 GND 1B3 1B4 1B5 VCC 1B6 1B7 1B8 GND 1B9 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 2B9 GND 2OEBA 2LEBA 2CLKBA TDI TCK † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, and UBT are trademarks of Texas Instruments. Copyright  2003, Texas Instruments Incorporated 


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SCBS790 − NOVEMBER 2003 description/ordering information The SN74LVTH18512 and SN74LVTH182512 scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B-port outputs of SN74LVTH182512, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. ORDERING INFORMATION TA −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TSSOP − DGG Tape and reel 8V18512IDGGREP‡ TSSOP − DGG Tape and reel 8V182512IDGGREP TOP-SIDE MARKING LH182512EP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ Product Preview 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 FUNCTION TABLE† (normal mode, each register) INPUTS OUTPUT B OEAB LEAB CLKAB A L L L X L L ↑ L B0‡ L L L ↑ H H L H X L L L H X H H H X X X Z † A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 functional block diagram Boundary-Scan Register 2 1LEAB 1CLKAB 1OEAB 1LEBA 1CLKBA 1OEBA 1A1 1 VCC 3 63 64 VCC 62 C1 C1 1D 1D 61 4 C1 1D 1B1 C1 1D One of Nine Channels 2LEAB 2CLKAB 2OEAB 2LEBA 2CLKBA 2OEBA 2A1 29 30 VCC 28 36 35 VCC 37 C1 C1 1D 1D 49 16 C1 1D 2B1 C1 1D One of Nine Channels Bypass Register Boundary-Control Register Identification Register TDI TMS TCK 4 VCC 34 VCC 32 33 31 Instruction Register TAP Controller POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TDO 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 Terminal Functions TERMINAL NAME DESCRIPTION 1A1−1A9, 2A1−2A9 Normal-function A-bus I/O ports. See function table for normal-mode logic. 1B1−1B9, 2B1−2B9 Normal-function B-bus I/O ports. See function table for normal-mode logic. 1CLKAB, 1CLKBA, 2CLKAB, 2CLKBA GND Normal-function clock inputs. See function table for normal-mode logic. Ground 1LEAB, 1LEBA, 2LEAB, 2LEBA Normal-function latch enables. See function table for normal-mode logic. 1OEAB, 1OEBA, 2OEAB, 2OEBA Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the terminal to a high level if left unconnected. TCK Test clock. One of four terminals required by IEEE Std 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. TDI Test data input. One of four terminals required by IEEE Std 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. TDO Test data output. One of four terminals required by IEEE Std 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. TMS Test mode select. One of four terminals required by IEEE Std 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. VCC Supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 test architecture Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Std 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully one-half of the TCK cycle. The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device identification register. Test-Logic-Reset TMS = H TMS = L TMS = H TMS = H TMS = H Run-Test/Idle Select-DR-Scan Select-IR-Scan TMS = L TMS = L TMS = L TMS = H TMS = H Capture-DR Capture-IR TMS = L TMS = L Shift-DR Shift-IR TMS = L TMS = L TMS = H TMS = H TMS = H TMS = H Exit1-DR Exit1-IR TMS = L TMS = L Pause-DR Pause-IR TMS = L TMS = L TMS = H TMS = H TMS = L Exit2-DR TMS = L Exit2-IR TMS = H Update-DR TMS = H TMS = L Figure 1. TAP-Controller State Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS = H Update-IR TMS = H TMS = L 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 state diagram description The TAP controller is a synchronous finite-state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Std 1149.1-1990. The TAP controller proceeds through its states, based on the level of TMS at the rising edge of TCK. As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time. Test-Logic-Reset The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values. The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. For the SN74LVTH18512 and SN74LVTH182512, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Bits 47−44 in the boundary-scan register are reset to logic 1, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked the outputs would be at the high-impedance state). Reset-value of other bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test operation. Run-Test/Idle The TAP controller must pass through the Run-Test /Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test /Idle state also can be entered, following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test /Idle state. Select-DR-Scan, Select-lR-Scan No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan. Capture-DR When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register captures a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR state, data is shifted serially through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state. Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state. Pause-DR No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data. Update-DR If the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK, following entry to the Update-DR state. Capture-IR When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the SN74LVTH18512 and SN74LVTH182512, the status value loaded in the Capture-IR state is the fixed binary value 10000001. Shift-IR Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to the logic level present in the least-significant bit of the instruction register. While in the stable Shift-IR state, instruction data is shifted serially through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state. Exit1-IR, Exit2-IR The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state. Pause-IR No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data. Update-IR The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 register overview With the exception of the bypass and device-identification registers, any test register can be thought of as a serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register. instruction register description The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR. Table 3 lists the instructions supported by the SN74LVTH18512 and SN74LVTH182512. The even-parity feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE devices, but are not supported by this device, default to BYPASS. During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated, and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2. TDI Bit 7 Parity (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TDO Figure 2. Instruction Register Order of Scan POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 data register description boundary-scan register The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and output data). The BSR is used to store test data that is to be applied externally to the device output pins, and/or to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test /Idle, as determined by the current instruction. At power up or in Test-Logic-Reset, BSCs 47−44 are reset to logic 1, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the high-impedance state). Reset values of other BSCs should be considered indeterminate. The BSR order of scan is from TDI through bits 47−0 to TDO. Table 1 shows the BSR bits and their associated device pin signals. Table 1. Boundary-Scan Register Configuration 10 BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL 47 2OEAB 35 2A9-I/O 17 2B9-I/O 46 1OEAB 34 2A8-I/O 16 2B8-I/O 45 2OEBA 33 2A7-I/O 15 2B7-I/O 44 1OEBA 32 2A6-I/O 14 2B6-I/O 43 2CLKAB 31 2A5-I/O 13 2B5-I/O 42 1CLKAB 30 2A4-I/O 12 2B4-I/O 41 2CLKBA 29 2A3-I/O 11 2B3-I/O 40 1CLKBA 28 2A2-I/O 10 2B2-I/O 39 2LEAB 27 2A1-I/O 9 2B1-I/O 38 1LEAB 26 1A9-I/O 8 1B9-I/O 37 2LEBA 25 1A8-I/O 7 1B8-I/O 36 1LEBA 24 1A7-I/O 6 1B7-I/O −− −− 23 1A6-I/O 5 1B6-I/O −− −− 22 1A5-I/O 4 1B5-I/O −− −− 21 1A4-I/O 3 1B4-I/O −− −− 20 1A3-I/O 2 1B3-I/O −− −− 19 1A2-I/O 1 1B2-I/O −− −− 18 1A1-I/O 0 1B1-I/O POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 boundary-control register The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test (RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3. TDI Bit 2 (MSB) Bit 1 Bit 0 (LSB) TDO Figure 3. Boundary-Control Register Order of Scan bypass register The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4. TDI Bit 0 TDO Figure 4. Bypass Register Order of Scan POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 device-identification register The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device. For the SN74LVTH18512, the binary value 00000000000000111011000000101111 (0003B02F, hex) is captured (during Capture-DR state) in the IDR to identify this device as Texas Instruments SN74LVTH18512. For the SN74LVTH182512, the binary value 00000000000000111100000000101111 (0003C02F, hex) is captured (during Capture-DR state) in the device-identification register to identify this device as Texas Instruments SN74LVTH182512. The IDR order of scan is from TDI through bits 31−0 to TDO. Table 2 shows the IDR bits and their significance. Table 2. Device-Identification Register Configuration IDR BIT NUMBER IDENTIFICATION SIGNIFICANCE IDR BIT NUMBER IDENTIFICATION SIGNIFICANCE IDR BIT NUMBER IDENTIFICATION SIGNIFICANCE 31 VERSION3 27 PARTNUMBER15 11 30 VERSION2 26 PARTNUMBER14 10 MANUFACTURER10† MANUFACTURER09† 29 VERSION1 25 PARTNUMBER13 9 28 VERSION0 24 PARTNUMBER12 8 −− −− 23 PARTNUMBER11 7 −− −− 22 PARTNUMBER10 6 −− −− 21 PARTNUMBER09 5 −− −− 20 PARTNUMBER08 4 −− −− 19 PARTNUMBER07 3 −− −− 18 PARTNUMBER06 2 −− −− 17 PARTNUMBER05 1 −− −− 16 PARTNUMBER04 0 MANUFACTURER00† LOGIC1† −− −− 15 PARTNUMBER03 −− −− −− −− 14 PARTNUMBER02 −− −− −− −− 13 PARTNUMBER01 −− −− −− −− 12 PARTNUMBER00 −− MANUFACTURER08† MANUFACTURER07† MANUFACTURER06† MANUFACTURER05† MANUFACTURER04† MANUFACTURER03† MANUFACTURER02† MANUFACTURER01† −− † Note that, for TI products, bits 11−0 of the device-identification register always contain the binary value 000000101111 (02F, hex). 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3. Instruction-Register Opcodes BINARY CODE† BIT 7 → BIT 0 MSB → LSB SCOPE OPCODE DESCRIPTION SELECTED DATA REGISTER MODE 00000000 EXTEST Boundary scan Boundary scan Test 10000001 IDCODE Identification read Device identification Normal 10000010 SAMPLE/PRELOAD BYPASS‡ Sample boundary Boundary scan Normal Bypass scan Bypass Normal Bypass scan Bypass Normal 00000101 BYPASS‡ BYPASS‡ Bypass scan Bypass Normal 00000110 HIGHZ Control boundary to high impedance Bypass Modified test 10000111 CLAMP BYPASS‡ Control boundary to 1/0 Bypass Test Bypass scan Bypass Normal 00001001 RUNT Boundary-run test Bypass Test 00001010 READBN Boundary read Boundary scan Normal 10001011 READBT Boundary read Boundary scan Test 00001100 CELLTST Boundary self test Boundary scan Normal 10001101 TOPHIP Boundary toggle outputs Bypass Test 10001110 SCANCN Boundary-control register scan Boundary control Normal 00001111 SCANCT Boundary-control register scan Boundary control Test All others BYPASS Bypass scan Bypass Normal 00000011 10000100 10001000 † Bit 7 is used to maintain even parity in the 8-bit instruction. ‡ The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the SN74LVTH18512 or SN74LVTH182512. boundary scan This instruction conforms to the IEEE Std 1149.1-1990 EXTEST instruction. The BSR is selected in the scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has been scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device pins, except for output enables, is passed through the BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47−44 of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the input mode. The device operates in the test mode. identification read This instruction conforms to the IEEE Std 1149.1-1990 IDCODE instruction. The IDR is selected in the scan path. The device operates in the normal mode. sample boundary This instruction conforms to the IEEE Std 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs associated with I/O pins in the output mode. The device operates in the normal mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 bypass scan This instruction conforms to the IEEE Std 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Std 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 This instruction conforms to the IEEE Std 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode. boundary-run test The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test /Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT). boundary read The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation. boundary self test The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode. boundary toggle outputs The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK in Run-Test /Idle and is then updated in the shadow latches and thereby applied to the associated device I/O pins on each falling edge of TCK in Run-Test /Idle. Data in the input-mode BSCs remains constant. Data appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode. boundary-control-register scan The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2−0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test /Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 4. Boundary-Control Register Opcodes BINARY CODE BIT 2 → BIT 0 MSB → LSB DESCRIPTION X00 Sample inputs/toggle outputs (TOPSIP) X01 Pseudo-random pattern generation/36-bit mode (PRPG) X10 Parallel-signature analysis/36-bit mode (PSA) 011 Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG) 111 Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT) While the control input BSCs (bits 47−36) are not included in the toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSCs (bits 47−44 of the BSR) control the drive state (active or high impedance) of the selected device output pins. These BCR instructions are valid only when both bytes of the device are operating in one direction of data flow (i.e., 1OEAB ≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction of data flow (i.e., 1OEAB = 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated. sample inputs/toggle outputs (TOPSIP) Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each falling edge of TCK. Figures 5 and 6 show the 36-bit linear-feedback shift-register algorithms through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O = Figure 5. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1) 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O = Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 parallel-signature analysis (PSA) Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8 show the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O = = Figure 7. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1) 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O = = Figure 8. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an 18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. Figures 9 and 10 show the 18-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O = = Figure 9. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1) 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O = = Figure 10. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. Figures 11 and 12 show the 18-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O MSB 2B9-I/O LSB = = 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1) 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O MSB 2A9-I/O LSB = = 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O Figure 12. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 timing description All test operations of the SN74LVTH18512 and SN74LVTH182512 are synchronous to the TCK signal. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK. A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the operation of the test circuitry during each TCK cycle. Table 5. Explanation of Timing Example TCK CYCLE(S) TAP STATE AFTER TCK DESCRIPTION 1 Test-Logic-Reset TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state. 2 Run-Test/Idle 3 Select-DR-Scan 4 Select-IR-Scan 5 Capture-IR The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state. 6 Shift-IR TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. 7−13 Shift-IR One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR. 14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 24 15 Update-IR 16 Select-DR-Scan 17 Capture-DR The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state. 18 Shift-DR TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. 19−20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO. 21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR 23 Select-DR-Scan 24 Select-IR-Scan 25 Test-Logic-Reset The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. The selected data register is updated with the new data on the falling edge of TCK. Test operation completed POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Update-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Exit1-DR Capture-DR Update-IR Select-DR-Scan ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Exit1-IR Shift-IR Capture-IR Select-IR-Scan TAP Controller State Select-DR-Scan TDO ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Run-Test/Idle TDI Test-Logic-Reset TMS Shift-DR TCK 3-State (TDO) or Don’t Care (TDI) Figure 13. Timing Example absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . . . . . . . −0.5 V to 7 V Current into any output in the low state, IO: SN74LVTH18512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA SN74LVTH182512 (A port or TDO) . . . . . . . . . . . . . . . . . 128 mA SN74LVTH182512 (B port) . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the high state, IO (see Note 2): SN74LVTH18512 . . . . . . . . . . . . . . . . . . . . . 64 mA SN74LVTH182512 (A port or TDO) . . . . . . 64 mA SN74LVTH182512 (B port) . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed. 2. This current only flows when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 recommended operating conditions (see Note 4) SN74LVTH18512-EP MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 Input voltage 5.5 V IOH IOL IOL† High-level output current −32 mA Low-level output current 32 mA Low-level output current 64 mA ∆t/∆v Input transition rise or fall rate 10 ns/V 85 °C High-level input voltage 2 Outputs enabled TA Operating free-air temperature † Current duty cycle ≤ 50%, f ≥ 1 kHz NOTE 4: Unused control inputs must be held high or low to prevent them from floating.   ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −40 V V V 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −3 mA IOH = −8 mA VCC = 3 V IOH = −32 mA IOL = 100 µA VCC = 2.7 V II A or B ports‡ Ioff II(hold)§ A or B ports IOZH IOZL TDO IOZPU IOZPD TDO TDO TDO VCC = 3.6 V, VCC = 0 or 3.6 V, VI = VCC or GND VI = 5.5 V VCC = 3.6 V VI = 5.5 V VI = VCC VI = 0 VI = 5.5 V VCC = 3.6 V VI = VCC VI = 0 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V VCC = 3 V VI = 2 V VO = 3 V VCC = 3.6 V, VCC = 3.6 V, 2 0.2 0.5 0.4 0.5 ±1 10 5 1 −25 −100 1 −5 ±100 75 150 500 −75 −150 −500 −1 µA ±50 µA ±50 µA 2 18 24 Outputs disabled 0.6 VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 µA A µA 0.6 ∆ICC¶ µA 1 Outputs low VCC = 3.6 V, IO = 0, VI = VCC or GND µA A 20 VO = 0.5 V or 3 V Outputs high ICC V 0.55 VO = 0.5 V VO = 0.5 V or 3 V VCC = 0 to 1.5 V, VCC = 1.5 V to 0, V V 2.4 IOL = 32 mA IOL = 64 mA VCC = 3 V OE, TDI, TMS −1.2 UNIT VCC−0.2 2.4 IOL = 24 mA IOL = 16 mA VOL CLK, LE, TCK SN74LVTH18512-EP MIN TYP† MAX TEST CONDITIONS mA 2 0.5 mA 4 pF 10 pF Co VO = 3 V or 0 8 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND § The parameter II(hold) includes the off-state output leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. pF Cio   ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN74LVTH18512-EP VCC = 3.3 V ± 0.3 V fclock Clock frequency CLKAB or CLKBA CLKAB or CLKBA high or low tw Pulse duration tsu Setup time LEAB or LEBA high A before CLKAB↑ or B before CLKBA↑ th Hold time MIN MAX 0 100 VCC = 2.7 V MIN MAX 0 80 4.4 5.6 3 3 2.8 3 CLK high 1.5 0.7 CLK low 1.6 1.6 A after CLKAB↑ or B after CLKBA↑ 1.4 1.1 A after LEAB↓ or B after LEBA↓ 3.1 3.5 A before LEAB↓ or B before LEBA↓ UNIT MHz ns ns ns timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14) SN74LVTH18512-EP VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX 0 50 0 40 fclock tw Clock frequency TCK Pulse duration TCK high or low 9.5 A, B, CLK, LE, or OE before TCK↑ 6.5 7 tsu Setup time TDI before TCK↑ 2.5 3.5 TMS before TCK↑ 2.5 3.5 A, B, CLK, LE, or OE after TCK↑ 1.7 1 TDI after TCK↑ 1.5 1 10.5 UNIT MHz ns ns th Hold time TMS after TCK↑ 1.5 1 td tr Delay time Power up to TCK↑ 50 50 ns Rise time VCC power up 1 1 µs   ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN74LVTH18512-EP PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ CLKAB or CLKBA MAX 100 A or B B or A CLKAB or CLKBA B or A LEAB or LEBA B or A OEAB or OEBA B or A OEAB or OEBA B or A VCC = 2.7 V MIN UNIT MAX 80 MHz 1.5 4.9 5.6 1.5 4.9 5.6 1.5 5.8 6.8 1.5 5.8 6.8 1.5 7.4 8.4 1.5 5.7 6.4 1.5 7.1 8.3 1.5 7.1 8.3 2.5 7.8 8.4 2.5 7.8 8.4 ns ns ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14) SN74LVTH18512-EP PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ TCK MAX 50 TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO VCC = 2.7 V MIN UNIT MAX 40 MHz 2.5 14 17 2.5 14 17 1 5.5 6.5 1.5 6.5 7.5 4 17 20 4 17 20 1 5.5 6.5 1.5 5.5 6.5 4 18 20 4 17 18.5 1.5 7 8.5 1.5 7 8 ns ns ns ns ns ns   ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 recommended operating conditions (see Note 4) SN74LVTH182512-EP MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 5.5 V High-level input voltage IOH High-level output current IOL Low-level output current IOL† ∆t/∆v 2 V A port, TDO −32 B port −12 mA A port, TDO 32 B port 12 Low-level output current A port, TDO 64 mA Input transition rise or fall rate Outputs enabled 10 ns/V 85 °C TA Operating free-air temperature † Current duty cycle ≤ 50%, f ≥ 1 kHz NOTE 4: Unused control inputs must be held high or low to prevent them from floating. 30 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −40 mA 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A, B, TDO VOH A port, TDO B port A, B, TDO VOL A port, TDO B port VCC = 2.7 V, IOH = −3 mA IOH = −8 mA VCC = 3 V IOH = −32 mA IOH = −12 mA VCC = 3 V, VCC = 2.7 V, 0.4 IOL = 64 mA IOL = 12 mA 0.55 VCC = 3.6 V VI = VCC VI = 0 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V IOZPU IOZPD TDO TDO 2 IOL = 16 mA IOL = 32 mA A or B ports‡ TDO V VCC = 3 V VCC = 3 V, VCC = 3.6 V, VI = 0 VI = 5.5 V VCC = 3 V VI = 2 V VO = 3 V VCC = 3.6 V, VCC = 3.6 V, 0.5 0.5 VCC = 3.6 V, IO = 0, VI = VCC or GND ±1 10 5 1 −25 −100 1 −5 ±100 75 150 500 −75 −150 −500 µA µA ±50 µA ±50 µA 2 18 24 Outputs disabled 0.6 2 VI = 3 V or 0 VO = 3 V or 0 µA A 1 0.6 Ci µA −1 Outputs low VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND µA A 20 VO = 0.5 V or 3 V Outputs high ∆ICC¶ V 0.8 VO = 0.5 V VO = 0.5 V or 3 V VCC = 0 to 1.5 V, VCC = 1.5 V to 0, V 2 0.2 VI = 5.5 V VI = VCC TDO 2.4 IOL = 100 µA IOL = 24 mA VCC = 3.6 V A or B ports −1.2 UNIT VCC−0.2 2.4 VCC = 2.7 V, OE, TDI, TMS IOZH IOZL ICC II = −18 mA IOH = −100 µA VCC = 0 or 3.6 V, Ioff II(hold)§ VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VI = VCC or GND VI = 5.5 V CLK, LE, TCK II SN74LVTH182512-EP MIN TYP† MAX TEST CONDITIONS 0.5 mA mA 4 pF 10 pF VO = 3 V or 0 8 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND § The parameter II(hold) includes the off-state output leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. pF Cio Co POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN74LVTH182512-EP VCC = 3.3 V ± 0.3 V fclock Clock frequency CLKAB or CLKBA CLKAB or CLKBA high or low tw Pulse duration tsu Setup time LEAB or LEBA high A before CLKAB↑ or B before CLKBA↑ th Hold time MIN MAX 0 100 VCC = 2.7 V MIN MAX 0 80 4.4 5.6 3 3 2.8 3 CLK high 1.5 0.7 CLK low 1.6 1.6 A after CLKAB↑ or B after CLKBA↑ 1.4 1.1 A after LEAB↓ or B after LEBA↓ 3.1 3.5 A before LEAB↓ or B before LEBA↓ UNIT MHz ns ns ns timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14) SN74LVTH182512-EP VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX 0 50 0 40 fclock tw Clock frequency TCK Pulse duration TCK high or low 9.5 A, B, CLK, LE, or OE before TCK↑ 6.5 7 tsu Setup time TDI before TCK↑ 2.5 3.5 TMS before TCK↑ 2.5 3.5 A, B, CLK, LE, or OE after TCK↑ 1.7 1 TDI after TCK↑ 1.5 1 10.5 UNIT MHz ns ns th Hold time TMS after TCK↑ 1.5 1 td tr Delay time Power up to TCK↑ 50 50 ns Rise time VCC power up 1 1 µs 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN74LVTH182512-EP PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ CLKAB or CLKBA MAX 100 A B B A CLKAB B CLKBA A LEAB B LEBA A OEAB or OEBA B or A OEAB or OEBA B or A VCC = 2.7 V MIN UNIT MAX 80 MHz 1.5 5.7 6.4 1.5 5.7 6.4 1.5 4.9 5.6 1.5 4.9 5.6 1.5 6.7 7.7 1.5 6.7 7.7 1.5 5.8 6.8 1.5 5.8 6.8 1.5 8.2 9.2 1.5 6.2 6.7 1.5 7.4 8.4 1.5 5.7 6.4 1.5 7.9 8.7 1.5 7.9 8.7 2.5 8.4 8.9 2.5 8.4 8.9 ns ns ns ns ns ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14) SN74LVTH182512-EP PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ TCK MAX 50 TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 2.7 V MIN UNIT MAX 40 MHz 2.5 14 17 2.5 14 17 1 5.5 6.5 1.5 6.5 7.5 4 17 20 4 17 20 1 5.5 6.5 1.5 5.5 6.5 4 18 20 4 17 18.5 1.5 7 8.5 1.5 7 8 ns ns ns ns ns ns 33 
   
      
 
 
  
 


SCBS790 − NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT 2.7 V Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V 2.7 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 2.7 V Output Control tPHL tPLH 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V th Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 14. Load Circuit and Voltage Waveforms 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) 8V182512IDGGREP ACTIVE TSSOP DGG 64 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH182512EP V62/04730-01XE ACTIVE TSSOP DGG 64 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH182512EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of