®
ACF2101
FPO
Low Noise, Dual
SWITCHED INTEGRATOR
FEATURES
APPLICATIONS
● INCLUDES INTEGRATION CAPACITOR,
RESET AND HOLD SWITCHES, AND
OUTPUT MULTIPLEXER
● LOW NOISE: 10µVrms
● LOW CHARGE TRANSFER: 0.1pC
● WIDE DYNAMIC RANGE: 120dB
● LOW BIAS CURRENT: 100fA
●
●
●
●
●
●
CURRENT TO VOLTAGE CONVERSION
PHOTODIODE INTEGRATOR
CURRENT MEASUREMENT
CHARGE MEASUREMENT
CT SCANNER FRONT END
MEDICAL, SCIENTIFIC, AND INDUSTRIAL
INSTRUMENTATION
DESCRIPTION
Reset
The ACF2101 is a dual switched integrator for precision applications. Each channel can convert an input
current to an output voltage by integration, using either
an internal or external capacitor. Included on the chip
are precision 100pF integration capacitors, hold and
reset switches, and output multiplexers.
As a complete circuit on a single chip, the ACF2101
eliminates many of the problems commonly encountered in discrete designs, such as leakage current errors
and noise pickup. The integrating approach can provide lower noise than conventional transimpedance
amplifier designs and also eliminates the need for high
performance, high value feedback resistors.
The extremely low bias current and low noise of the
ACF2101’s Difet ® amplifiers, along with active laser trimming of both offset and drift, assure precision
current to voltage conversion.
Although designed for +5V, –15V supplies, the
ACF2101 can be operated on supplies up to ±18VDC.
It is available in both 24-pin plastic DIP and SOIC
packages.
A
Hold
B
Select
A
B
A
B
CINTERNAL
Cap A
Out A
100pF
A
In A
Reset
Select
Sw In A
Hold
Sw Out A
Com A
Sw Com A
CINTERNAL
Cap B
Out B
100pF
B
In B
Reset
Select
Sw In B
Hold
Sw Out B
Com B
Sw Com B
A
V+
B
Gnd
V–
Difet® Burr-Brown Corp.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
SBFS003
© 1990 Burr-Brown Corporation
PDS-1078D
Printed in U.S.A. September, 1994
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, V+ = +5V, V– = –15V, Internal CINTEGRATION = CINTERNAL = 100pF, unless otherwise noted.
ACF2101BP, BU
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
±100
±100
µA
µA
ANALOG INPUT
INPUT RANGE
Input Current Range
Switched Input (SW IN A, SW IN B)
Direct Input (IN A, IN B)
INPUT IMPEDANCE
Switched Input
Hold Switch OFF
Hold Switch ON
Direct Input
HOLD SWITCH VOLTAGE
Hold Switch Withstand Voltage
1000
1.5
Virtual Ground
Hold Switch OFF
–10
OFFSET VOLTAGE
Input Offset Voltage
Average Drift
GΩ
kΩ
+0.5
V
±2
±5
mV
µV/°C
5.5
0.8
2
0
V
V
µA
µA
200
200
ns
ns
±0.5
±1
DIGITAL INPUTS
Logic Family
VIH (Logic 1 = Switch OFF)
VIL (Logic 0 = Switch ON)
IIH
IIL
Switching Speed (All Switches)
Switch ON
Switch OFF
TTL Compatible
2
–0.5
VIH = +5V
VIL = 0V
TRANSFER CHARACTERISTICS
VOUT = –
TRANSFER FUNCTION
DYNAMIC CHARACTERISTICS
Integrate Mode
Slew Rate
Reset Mode
Slew Rate
Settling Time to 0.01%FSR(1)
Overload Recovery
Output Multiplexer (Select Switches)
Settling Time to 0.01%FSR
Settling Time to 0.01%FSR
1
1
CINTEGRATION
3
5
5
CLOAD < 1000pF
CLOAD < 100pF
6.5
2
–50
RESET SWITCH
Impedance
Reset OFF
Reset ON
100
0.5
–25
30
1000
1.5
MODES OF OPERATION
Switch
Integrate Mode
Hold Mode
Reset Mode
(Logic 1 = OFF, Logic 0 = ON)
Hold
ON
OFF
ON/OFF
IN
3
10V Step
Positive or Negative
INTEGRATION CAPACITOR (CINTERNAL)
Internal Capacitor
Value
Accuracy
Temperature Coefficient
Memory
∫ I dt
V
V/µs
10
V/µs
µs
µs
µs
µs
2
0
100
pF
%
ppm/°C
ppm of FSR
GΩ
kΩ
Reset
OFF
OFF
ON
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
ACF2101
2
SPECIFICATIONS (CONT)
At TA = +25°C, V+ = +5V, V– = –15V, Internal CINTEGRATION = CINTERNAL = 100pF, unless otherwise noted.
ACF2101BP, BU
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–10
±5
–13.5, +1.0
+0.5
V
mA
OUTPUT
Voltage Output Range (All Outputs)
Current Output, Direct Output (Out A, Out B)
Short Circuit Current
Direct Output
Switched Output (Sw Out A, Sw Out B)
Select Switch Withstand Voltage
Switched Output
Switched Common (Sw Com A, Sw Com B)
Output Impedance
Direct Output
Switched Output
Select Switch ON
Select Switch OFF
Leakage Current
Load Capacitance Stability
Direct Output
Switched Output
±2
±25
±8
–10
–0.5
Select Switch OFF
mA
mA
+0.5
+0.5
V
V
0.1
Ω
250 || 5
1000 || 4
10
Ω || pF
GΩ || pF
pA
100
500
Any
pF
pF
OUTPUT ACCURACY
Nonlinearity
Channel Separation
Op Amp Bias Current
Value
Temperature Coefficient
Hold Mode Droop
Integrate Mode Droop
Voltage Offset(2)
Value
Temperature Coefficient
Power Supply Rejection
OUTPUT NOISE
Total Output Noise(3)
Integrate Mode(4)
Hold Mode
Reset Mode
CHARGE TRANSFER ERRORS(5)
Reset to Integrate Mode(6)
Charge Transfer
Charge Transfer TC
Charge Offset Error
Charge Offset TC
Integrate to Hold Mode
Charge Transfer
Charge Transfer TC
Charge Offset Error
Charge Offset TC
Hold to Integrate Mode
Charge Transfer
Charge Transfer TC
Charge Offset Error
Charge Offset TC
VS = +4.5V to +18V, –10V to –18V
80
BW = 0.1Hz to 10Hz
BW = 0.1Hz to 250kHz
BW = 0.1Hz to 250kHz
BW = 0.1Hz to 250kHz
±0.005
–80
±0.01
%FSR
dB
100
Doubles Each +10°C
1
1
1000
fA
10
10
nV/µs
nV/µs
3
5
100
mV
µV/°C
dB
2
10(1 + CIN/CINTEGRATION)
10
10
µVrms
µVrms
µVrms
µVrms
0.1
0.2
1
2
0.5
0.2
0.4
2
4
1
5
pC
fC/°C
mV
µV/°C
CIN > 50pF
10
pC
fC/°C
mV
µV/°C
CIN > 50pF
0.2
0.4
2
4
1
10
pC
fC/°C
mV
µV/°C
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Positive Supply
Negative Supply
Current
Positive Supply
Negative Supply
+5, –15
+4.5
–10
For Dual
For Dual
12
3.5
V
+18
–18
V
V
15
5.2
mA
mA
+85
+125
+125
°C
°C
°C
°C/W
TEMPERATURE RANGE
Specification
Operation
Storage
Thermal Resistance (both packages)
–40
–40
–40
Junction to Ambient
100
NOTES: (1) FSR is Full Scale Range = 10V (0 to –10V). (2) Includes offset errors from all modes of operation. (3) Total noise is rms total of noise for the modes
of operation used. (4) CIN = capacitance of sensor connected to ACF2101 input; CINTERGRATION = integration capacitance = CINTERNAL + CEXTERNAL. (5) Errors created
when the internal switches are driven from one mode to another. (6) The charge transfer is 0.1pC; for an integration capacitance of 100pF, the resultant charge
offset voltage error is 1mV.
®
3
ACF2101
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Supply ............................................................................................... ±18V
Input Current ..................................................................................... ±5mA
Output Short Circuit Duration .................................. Continuous to Ground
Power Dissipation .......................................................................... 500mW
Operating Temperature .................................................. –40°C to +125°C
Storage Temperature ...................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
PACKAGE/ORDERING INFORMATION
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
TEMPERATURE
RANGE
24-Pin Plastic DIP
24-Pin Plastic SOIC
243
239
–40°C to +85°C
–40°C to +85°C
PRODUCT
ACF2101BP
ACF2101BU
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PIN CONFIGURATION
DIP and SOIC package have different pinouts.
TOP VIEW
ACF2101BU
TOP VIEW
ACF2101BP
Sw In A
24
1
Out A
Sw Out A
24
In A
23
2
Gnd A
Sw Com A
23
Cap B
Cap A
22
3
Com A
Select A
22
4
Com B
Com A
21
4
Cap A
Reset A
21
5
Gnd B
Gnd A
20
5
In A
Hold A
20
6
Out B
Out A
19
6
Sw In A
V+
19
7
Sw Out B
Sw Out A
18
7
Sw In B
V–
18
8
Sw Com B
Sw Com A
17
8
In B
Hold B
17
9
Select B
Select A
16
9
Cap B
Reset B
16
10
Reset B
Reset A
15
10
Com B
Select B
15
11
Hold B
Hold A
14
11
Gnd B
Sw Com B
14
12
V–
V+
13
12
Out B
Sw Out B
13
1
Sw In B
2
In B
3
SOIC
®
ACF2101
4
DIP
DICE INFORMATION
PAD
FUNCTION
PAD
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
A Out
A Ground
A Common
A Cap
A In
A Switch-In
B Switch-In
B In
B Cap
B Common
B Ground
B Out
13
14
15
16
17
18
19
20
21
22
23
24
B Switch-Out
B Switch-Common
B Select
B Reset
B Hold
V–
V+
A Hold
A Reset
A Select
A Switch-Common
A Switch-Out
Substrate Bias: Ground.
MECHANICAL INFORMATION
Die Size
Die Thickness
Min. Pad Size
MILS (0.001")
MILLIMETERS
132 x 157 ±5
20 ±3
4x4
3.35 x 3.99 ±0.13
0.51 ±0.08
0.10 x 0.10
Backing
ACF2101 DIE TOPOGRAPHY
None
®
5
ACF2101
TYPICAL PERFORMANCE CURVES
At TA = +25°C, V+ = +5V, V– = –15V, CINTEGRATION = CINTERNAL = 100pF, unless otherwise noted.
TOTAL OUTPUT NOISE vs C1 and C2
BIAS CURRENT vs TEMPERATURE
100
10pA
Total Output Noise (µVrms)
Op Amp Bias Current
90
1pA
100fA
80
C2 =
70
50
40
C2 = 200pF
30
F
C 2 = 500p
20
10fA
C2 = 1000pF
0
–40
–20
0
20
40
60
80
0
100
100 200 300 400 500 600 700 800 900 1000
C1 (pF)
Temperature (°C)
Sw Out Settling Time (µs) to 0.01%, 10V Step
RESET TIME vs CINTEGRATION
40
Reset Time to 0.01% (µs)
F
60
10
30
20
10
0
0
100 200
300 400
500 600
700 800
900 1000
Sw Out SETTLING TIME vs CLOAD
8
6
4
2
0
0
100 200
300 400
1.65k
1.6k
RON
IIN
1.6k
Hold SW
900 1000
RON
Reset SW
1.55k
RON (Ω)
1.55k
700 800
RESET SWITCH RON vs INPUT CURRENT
HOLD SWITCH RON vs INPUT CURRENT
1.65k
IIN
500 600
CLOAD (pF)
CINTEGRATION (pF)
RON (Ω)
100p
1.5k
1.5k
1.45k
1.45k
1.4k
1.4k
1.35k
NOTE: If IIN flows through Reset Switch that
is ON, an output offset voltage is created.
1.35k
–100µA
–10µA
–1µA
0
1µA
10µA
100µA
–100µA
IIN
–1µA
0
IIN
®
ACF2101
–10µA
6
1µA
10µA
100µA
APPLICATIONS INFORMATION
Improper handling or cleaning may increase droop. Contamination from handling parts and circuit boards can be
removed with cleaning solvents and de-ionized water.
BASIC CIRCUIT CONNECTION
Basic Layout
As with any precision circuit, careful layout will ensure best
performance. Make short, direct interconnections and avoid
stray wiring capacitance—especially at the analog and
digital input pins.
Pinout
The pinout for the DIP and SOIC package of the ACF2101 is
different. The pinouts for the different packages are shown in
several figures in this data sheet.
Figures 1a and 1b illustrate the basic connections needed for
operation. Figures 1c and 1d illustrate the addition of
external integration capacitors and input guards.
Power Supplies
The ACF2101 can operate from supplies that range from
+4.5V and –10V to ±18V. Since the output voltage
integrates negatively from ground, a positive supply of +5V
is sufficient to attain specified performance. Using +5V and
–15V power supplies reduces power dissipation by one-half
of that at ±15V.
Leakage currents between printed circuit board traces can
easily exceed the input bias current of the ACF2101. A
circuit board “guard” pattern reduces leakage effects by
surrounding critical high impedance input circuitry with a
low impedance circuit connection at the same potential.
Leakage will flow harmlessly to the low impedance node.
Figure 2a and 2b show printed circuit patterns that can be
used to guard critical pins. Note that traces leading to these
pins should also be guarded.
Top View
Power supply connections should be bypassed with good
high-frequency capacitors, such as 1µF solid tantalum
capacitors, positioned close to the power supply pins.
ACF2101BU
Input
1
Sw In A
Sw In B
Top View
Input
24
ACF2101BP
1
Out A
24
VOUT
In A
23
2
Gnd A
23
Cap B
Cap A
22
3
Com A
22
4
Com B
Com A
21
4
Cap A
21
5
Gnd B
Gnd A
20
5
In A
20
6
Out B
Out A
19
6
Sw In A
V+
19
7
Sw In B
V–
18
2
In B
3
Input
VOUT
VOUT
Input
V+
1µF
7
18
8
17
8
In B
17
9
16
9
Cap B
16
10
15
10
Com B
15
11
14
11
Gnd B
14
12
Out B
1µF
1µF
V–
1µF
12
+
V–
V–
SOIC
V+
13
+
DIP
13
VOUT
V+
These points must be connected to a
common ground point or a ground plane.
These points must be connected to a
common ground point or a ground plane.
FIGURE 1b. Basic Circuit Connections, DIP.
FIGURE 1a. Basic Circuit Connections, SOIC package.
®
7
ACF2101
Top View
ACF2101BU
Top View
ACF2101BP
Guards
Input
1
Sw In B
2
In B
Sw In A
24
In A
23
Input
1
Out A
24
2
Gnd A
23
VOUT
*
*
3
Cap B
Cap A
22
3
Com A
22
4
Com B
Com A
21
4
Cap A
21
5
Gnd B
Gnd A
20
5
In A
20
6
Out B
Out A
19
6
Sw In A
V+
19
V–
18
*
Input
VOUT
Guards
VOUT
Input
V+
1µF
7
18
7
Sw In B
8
17
8
In B
17
9
16
9
Cap B
16
10
15
10
Com B
15
11
Gnd B
14
12
Out B
1µF
V–
*
14
11
1µF
1µF
12
+
V–
SOIC
V+
13
* Optional External C
V–
+
DIP
13
VOUT
* Optional External C
V+
These points must be connected to a
common ground point or a ground plane.
These points must be connected to a
common ground point or a ground plane.
FIGURE 1d. Circuit Connections with External Capacitors
and Guarding, DIP.
FIGURE 1c. Circuit Connections with External Capacitors
and Guarding, SOIC package.
ACF2101BU
ACF2101BP
Guards
1 Sw In B
Sw In A 24
2 In B
In A 23
3 Cap B
Cap A 22
3 Com A
4 Com B
Com A 21
4 Cap A
5 In A
6 Sw In A
Guards
7 Sw In B
8 In B
9 Cap B
10 Com B
DIP
SOIC
FIGURE 2a. PC Board Layout Showing “Guard” Traces for
Input, SOIC package. Both top and bottom of
board should be guarded.
FIGURE 2b. PC Board Layout Showing “Guard” Traces for
Input, DIP. Both top and bottom of board
should be guarded.
®
ACF2101
8
MODES OF OPERATION
The three basic modes of operation of each integrator are
controlled by the Hold and Reset switches. In Integrate
mode, the output voltage integrates negatively toward –10V.
In Hold mode, the output voltage remains at the present
value, except for output droop. In Reset mode, the integration capacitor is discharged and the output voltage is driven
to analog common. See Figure 4.
Hold and Reset Switches
To use the Hold switch, connect the input current to the “Sw
In” pin. The Hold switch disconnects the input current, and
holds the output voltage at a fixed level. For direct input,
connect the input current to the “In” pin that bypasses the
Hold switch and connects directly to the input summing
junction. If the Hold switch is not used, the switch should be
in the off mode and the “Sw In” pin should be connected to
analog common.
SWITCHES
Each integrator includes four switches: a Hold switch, a
Reset switch, and two output Select switches. See Figure 3.
The Reset switch is used to discharge the integration capacitor before the start of a new integration period. See Typical
Performance Curve showing Reset Time vs CINTEGRATION.
Hold
Reset
Select Switches
The two Select switches can be used to multiplex the outputs
when multiple integrators are connected to a common bus.
Figure 5 shows a number of ACF2101s multiplexed together
into an A/D converter. The output settling time is determined by the Select switch “on” resistance of 250Ω and
the total output capacitance. The total output capacitance
includes the ACF2101 output capacitances plus the capacitance of the interconnections to the A/D converter.
Select
100pF
Cap
Out
CINTERNAL
In
Reset
Sw In
Hold
Sw Out
Com
Sw Com
FIGURE 3. Switch Control Lines on One Channel of Two
in ACF2101.
HOLD
INTEGRATE
HOLD RST HOLD INTEGRATE
To
ADC
OUTPUT (V)
0
Instrumentation
Amplifier
–10
OFF
HOLD
ON
OFF
RESET
ON
MODES OF OPERATION
SWITCH
Hold Switch
Reset Switch
MODE OF OPERATION
Integrate
Hold
Reset
ON
OFF
OFF
OFF
ON/OFF
ON
FIGURE 5. ACF2101s in Multiplexed Operation.
ON: Switch shorted; Logic 0 input. OFF: Switch open; Logic 1 input.
FIGURE 4. Modes of Operation.
®
9
ACF2101
OUTPUT VOLTAGE
The integrator output voltage range is from +0.5V to –10V.
The output voltage (VOUT) can be calculated as:
V OUT =
VOUT =
CINT =
IIN =
∆t
=
the
the
the
the
NOISE
The total output noise for a specific application of the
ACF2101 is the rms total of the noise in the modes used:
Integrate noise (enI), Hold noise (enH) and Reset noise (enR).
The noise in both the Hold (enH) and Reset (enR) modes is
10µVrms. The noise in the Integrate mode (enI) is directly
proportional to one plus the ratio of CIN to CINTEGRATION,
where CIN is the capacitance of the circuit at the input of the
integrator and CINTEGRATION = CINTERNAL + CEXTERNAL and
is the integration capacitance:
I IN x ∆t
C INT
maximum output voltage (in volts)
integration capacitance (in farads)
input current (in amperes)
integration time (in seconds)
Integrate output noise (enI) = (10µVrms) x (1 + CIN/CINTEGRATION)
Examples of Component Values for –10V Output
iIN (µA)
∆t (s)
CINT (pF)
VOUT (V)
0.01
0.1
1
10
100
10
100
100m
10m
1m
100µ
10µ
1m
100µ
100
100
100
100
100
1000
1000
–10
–10
–10
–10
–10
–10
–10
Therefore, for very low CIN, the Integrate noise will approach 10µVrms. The total noise when in the Hold mode
after proceeding through Reset and Integrate modes is
approximated as shown below.
Total Noise = e nI 2 + e nH 2 + e nR 2
See Typical Performance Curve showing Total Output Noise
vs CIN and CINTEGRATION for more accurate noise data under
specific circumstances. If only the Integrate and Reset modes
are used, the total noise is the rms sum of the noise of the two
modes as shown below.
OUTPUT OVERLOAD
When the output to the ACF2101 integrates to the negative
limit, the output voltage smoothly limits at approximately
1.5V from the negative power supply, and reset time will
increase by approximately 5µs for overload recovery. For
fastest reset time avoid integrating to the negative limit.
Total Noise = e nI 2 + e nR 2
DYNAMIC CHARACTERISTICS
Frequency Response
The ACF2101 switched integrator is a sampled system
controlled by the sampling frequency (fs), which is usually
dominated by the integration time. Input signals above the
Nyquist frequency (fs/2) create errors by being aliased into
the sampled frequency bandwidth. The sampled frequency
bandwidth of the switched integrator has a –3dB characteristic at fs/2.26 and a null at fs and harmonics 2fs, 3fs, 4fs,
etc. This characteristic is often used to eliminate known
interference.
EXTERNAL CAPACITOR
An external integration capacitor may be used instead of or
in addition to the internal 100pF integration capacitor. Since
the transfer function depends upon the characteristics of the
integration capacitor, it must be carefully selected. An
external integration capacitor should have low voltage
coefficient, temperature coefficient, memory, and leakage
current. The optimum selection depends upon the requirements of the specific application. Suitable types include
NPO ceramic, polycarbonate, polystyrene, and silver mica.
If the internal integration capacitor is not used, the Cap pin
should be connected to common.
FREQUENCY RESPONSE
0
Frequency Response (dB)
CINTERNAL
Cap
Out
In
Sensor
Sw In
Sw Out
RIN
CIN
Com
–10
Nyquist
(fs/2)
–20dB/decade
Slope
–20
–30
–40
Sw Com
–50
fs/10
fs
Sampling Frequency (fs)
FIGURE 6. Capacitance of Circuit at Input of Integrator.
FIGURE 7. Frequency Response.
®
ACF2101
10
10fs
20fs
Charge Transfer
Charge transfer is the charge that is coupled from the logic
control inputs through circuit capacitance to the integration
capacitor when the Hold and Reset switches change mode.
Careful printed circuit layout must be used to minimize
external coupling from digital to analog circuitry and the
resulting charge transfer. Charge transfer results in a DC
charge offset error voltage. The ACF2101 switches are
compensated to reduce charge transfer errors.
INTEGRATE
HOLD RESET HOLD
OUTPUT (V)
0
–10
OFF
HOLD
ON
Droop
1nV/µs*
OFF
RESET
ON
Since the ACF2101 switches contribute equal and opposite
charge for positive and negative logic input transitions, the
total error due to charge transfer is determined by the
switching sequence. For each switch, a logic transition
results in a specific charge (and offset voltage) while an
opposite going logic transition results in an opposite charge
(and opposite offset voltage). Thus, if the Hold switch is
turned on and off during one integration cycle, the total
charge transfer at the end of the sequence due to the Hold
switch is essentially zero.
Ideal Level
* 100pF Integration
Capacitor
FIGURE 8. Droop and Charge Offset Effects.
The amount of charge transfer to the integration capacitor is
constant for each switch. Therefore, the charge offset error
voltage is lower for larger integration capacitors. The
ACF2101’s 0.1pC charge transfer results in a 1mV charge
offset voltage when using the 100pF internal integration
capacitor. The offset voltage will change linearly with the
integration capacitance. That is, 50pF will result in a 2mV
charge offset and 200pF in a 0.5mV charge offset.
load is often useful in reducing the noise of systems not
requiring the full bandwidth of the ACF2101.
PROGRAMMABLE I TO V CONVERTER EXAMPLE
Figure 10 illustrates the use of the ACF2101 as a programmable current to voltage converter. The output of the circuit,
VOUT, is a DC level for a constant current input. The timing
diagram shown in Figure 9 shows VOUT for an input current
that varies from one sample to the next. This circuit offers
wide dynamic range without the use of extremely large
resistors. An ACF2101 and an OPA2107 op amp are configured to convert a low level input current to an output voltage.
The equivalent gain of the converter is determined by the
frequency of the digital input signal, fS. The inherent integrating function of the ACF2101 is very useful for rejection
of noise such as power line pickup.
Droop
Droop is the change in the output voltage over time as a
result of the bias current of the amplifier, leakage of the
integration capacitor and leakage of the Reset and Hold
switches. Droop occurs in both the Integrate and Hold
modes of operation. Careful printed circuit layout must be
used to minimize external leakage currents as discussed
previously.
The droop is calculated by the equation:
Droop =
The ACF2101 integrates the current signal for the period of
fS. The magnitude of the ramp voltage at the output of the
ACF2101 is a function of the frequency of fS and the value
of the integration capacitor, CINTEGRATION. The ACF2101’s
100pF internal capacitor is used for CINTEGRATION in this
example. The effect is that fS controls the equivalent feedback resistance of a transconductance (current-to-voltage)
amplifier. The equivalent feedback resistance range can vary
over a large range of at least 1MΩ to 1GΩ as illustrated in
the accompanying table. Larger equivalent feedback resistances can be obtained if internal capacitances smaller than
100pF are used with the ACF2101.
100fA
CINTEGRATION
where CINTEGRATION = CINTERNAL + CEXTERNAL and is the
integration capacitance in farads and the result is in volts per
second. For the internal integration capacitance of 100pF,
the droop is calculated as:
Droop =
Charge Offset
1mV*
MODES OF OPERATION
100 X 10 –15
= 1mV/s or 1nV/µs
100 X 10 –12
Droop increases by a factor of 2 for each 10°C increase
above 25°C. See the typical performance curve showing
Bias Current vs Temperature.
A simplified equation for the operation of this circuit is:
VOUT = ISENSOR X RPROGRAM
Capacitive Loads
Any capacitive load can be safely driven through the multiplexed output of the ACF2101. As with any op amp, however, best dynamic performance of the ACF2101 can be
achieved by minimizing the capacitive load. See the typical
performance curve showing settling time as a function of
capacitive load for more information. A large capacitive
Where:
VOUT is the voltage at the output of the OPA2107,
ISENSOR is the current into the ACF2101, and
RPROGRAM is the equivalent feedback resistance of the
circuit calculated by the equation,
RPROGRAM = 1/(fS X CINTEGRATION) = 1/(fS X 100pF)
®
11
ACF2101
For CINTEGRATION = 100pF, RPROGRAM is calculated below:
RPROGRAM
10kHz
1kHz
100Hz
60Hz
50Hz
10Hz
1MΩ
10MΩ
100MΩ
167MΩ
200MΩ
1GΩ
At the end of the integration cycle, the Hold switch of the
ACF2101 is opened to hold a constant value at the output of
the ACF2101. The constant value output voltage of the
ACF2101 is transferred onto a 10nF capacitor by closing the
ACF2101’s Select switch. The Select switch is then opened
which holds the voltage on the 10nF capacitor during the
next integration cycle and creates a DC output. With this
operation, the Select switch of the ACF2101 and the 10nF
capacitor form a Sample/Hold (S/H) circuit. The OPA2107
is used to buffer the Sample/Hold output. The charge injection of the Select switch creates a small offset voltage, of
approximately 1mV in this example. The 10nF capacitor
was chosen as a large value to minimize this offset voltage.
fS
Integrator
output
See
Close-up
below
VOUT
Current-to-Voltage converter timing diagram overview.
fS
After the Select switch opens, the ACF2101 is reset by
momentarily closing the Reset switch. The ACF2101’s Hold
switch is then closed to begin another integration cycle.
During the period of time that the Hold switch is open, the
input signal current is stored on the input capacitance of the
sensor (CIN). During this time, the input signal current
creates a voltage across the sensor. This voltage should be
kept below 500mV. When the Hold switch is closed, the
charge that has collected on CIN will be transferred to the
integration capacitor, CINTEGRATION, with no loss of signal.
Therefore, one integration cycle ends and the next integration cycle begins when the Hold switch is opened.
Select
Reset
Hold
Start/End
of integration cycle
Hold
Integrator
output
If 100% of signal acquisition is not required, or not wanted,
the Hold switch may be left closed, or the direct input to the
ACF2101 used. In this mode of operation, an integration
cycle ends when the Select switch is opened and the next
integration cycle begins when the Reset switch is opened.
Hold
Re
se
t
fS
Figure 11 shows a simple digital pattern generator which can
be used to create the timing signals to control the ACF2101
circuit of Figure 10. This circuit creates signals to control
the Select, Reset and Hold switches at a rate controlled by
the frequency of fS. Figure 9 shows the timing diagram
for these circuits.
In a sampled data system, the output of the ACF2101 at the
output of the Select switch can be converted to digital when
the ACF2101 is in the Hold mode. In this situation, of
course, the 10nF capacitor and the OPA2107 op amp are not
required.
Expanded view of ACF2101 timing signals.
FIGURE 9. ACF2101 Current-to-Voltage Converter
Timing Diagram.
100pF
Reset
ISENSOR
1/2
Hold
OPA2107
1/2
ACF2101
Select
10nF
CIN
FIGURE 10. Programmable Current-to-Voltage Converter.
®
ACF2101
Transfer of
charge
from CIN
12
VOUT
+15V
10kΩ
164kΩ
8
fs
4
2
1000pF
Approximately 18µs
7
555
Timer
6
1
100pF
3
Hold
+VS
10kΩ
14
1N914
4
6
54.5kΩ
100pF
Both approximately 6µs
1
2
556
Dual Timer
8
1000pF
54.5kΩ
10
7
5
13
12
9
100pF
20kΩ
Reset
Select
FIGURE 11. Timing Generator.
VOLTAGE INPUT EXAMPLE
Figure 12 illustrates the use of the ACF2101 with a voltage
input. This approach is useful in applications where a constant current source is needed. For example, the ACF2101
can be configured in a bipolar mode by using the current
generated by a voltage reference as an offset current. In the
example in Figure 12, a 10V reference (REF102) is used in
series with a 400kΩ resistor to generate a constant +25µA
input current to the ACF2101. The ACF2101 will operate as
expected in this configuration except in the Hold mode.
When the Hold switch is opened, the input to the ACF2101
becomes high impedance and consequently the Sw In node
will try to go to 10V. The Hold switch is specified to have
a withstand voltage of +0.5V. When the voltage at the Sw In
node exceeds +0.5V the Hold switch will begin to conduct
again. This will not cause damage to the switch, however,
the output will start to unexpectedly integrate again. The
addition of either C1 or D1 in the circuit is critical for proper
Hold mode operation. C1 will divert the charge being gener-
ated by the voltage source in series with the resistor. C1 is
selected so that the maximum voltage does not exceed 0.4V.
When the Hold switch is closed again, the charge collected
by C1 is transferred to the integration capacitor. D1 will
divert the charge being generated by the voltage source and
resistor to ground. When the Hold switch closes again, the
charge stored on the parasitic capacitor of the diode is
transferred to the integration capacitor. D1 should be selected so that the on voltage of the diode does not exceed
0.4V.
DEMONSTRATION BOARD AND MACROMODEL
Demonstration boards are available to speed prototyping.
The demonstration board, DEM-ACF2101BP-C includes a
programmable timing generator making it easy to do a quick
evaluation.
A Spice-based macromodel is also available. Request
AB-020 for Application Bulletin and Burr-Brown's Spice
Macromodel diskette.
®
13
ACF2101
+15V
2
6
REF
102
Hold
7
4
Reset
Select
1µF
CINTERNAL
Cap
Out
100pF
400kΩ
R1
In
Reset
IOFF
Sw In
Sw Out
Hold
D1
C1
Com
Sw Com
1/2 ACF2101
FIGURE 12. Using the ACF2101 with a Voltage Source.
®
ACF2101
14
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
ACF2101BP
OBSOLETE
PDIP
NT
24
ACF2101BU
ACTIVE
SOIC
DW
24
ACF2101BU/1K
ACTIVE
SOIC
DW
24
ACF2101BU/1KE4
ACTIVE
SOIC
DW
24
ACF2101BUE4
ACTIVE
SOIC
DW
24
Package Qty
Eco Plan
(2)
TBD
25
Green (RoHS
& no Sb/Br)
TBD
TBD
25
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
Call TI
Replaced by ACF2101BU
CU NIPDAU Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
Call TI
Call TI
Purchase Samples
Call TI
Call TI
Purchase Samples
CU NIPDAU Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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