ADC07D1520
Low Power, 7-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter
General Description
Features
The ADC07D1520 is a dual, low power, high performance
CMOS analog-to-digital converter. The ADC07D1520 digitizes signals to 7 bits of resolution at sample rates up to 1.5
GSPS. Its features include a test pattern output for system
debug, a clock phase adjust, and selectable output demultiplexer modes. This device is guaranteed to have no missing
codes over the full operating temperature range. The unique
folding and interpolating architecture, the fully differential
comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable
a very flat response of all dynamic parameters beyond
Nyquist, producing a high 6.8 Effective Number of Bits
(ENOB) with a 748 MHz input signal and a 1.5 GHz sample
rate while providing a 10-18 Code Error Rate (C.E.R.) Output
formatting is offset binary and the Low Voltage Differential
Signaling (LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample
rate on each bus. When Non-Demultiplexed Mode is selected,
the output data rate on channels DI and DQ is at the same
rate as the input sample clock. The two converters can be
interleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a leaded or lead-free,
128-pin, thermally enhanced, exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature
range.
●
●
●
●
●
●
●
●
●
Single +1.9V ±0.1V Operation
Interleave Mode for 2x Sample Rate
Multiple ADC Synchronization Capability
Adjustment of Input Full-Scale Range, Clock Phase, and
Offset
Choice of SDR or DDR Output Clocking
1:1 or 1:2 Selectable Output Demux
Second DCLK Output
Duty Cycle Corrected Sample Clock
Test pattern
Key Specifications
●
●
●
●
●
●
Resolution
Max Conversion Rate
Code Error Rate
ENOB @ 748 MHz Input
DNL
Power Consumption (Non-DES Mode)
— Operating in 1:2 Demux Mode
— Power Down Mode
7 Bits
1.5 GSPS (max)
10-18 (typ)
6.8 Bits (typ)
±0.15 LSB (typ)
1.9 W (typ)
2.5 mW (typ)
Applications
●
●
●
●
●
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
NS Package
ADC07D1520CIYB/NOPB
Lead-free 128-Pin Exposed Pad LQFP
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
301941 SLAS881A
Copyright © 1999-2012, Texas Instruments Incorporated
ADC07D1520
Block Diagram
30194153
2
Copyright © 1999-2012, Texas Instruments Incorporated
ADC07D1520
Pin Configuration
30194101
Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.
Copyright © 1999-2012, Texas Instruments Incorporated
3
ADC07D1520
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
3
OutV / SCLK
29
PDQ
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin logic high for normal differential DCLK and data
amplitude. Ground this pin for a reduced differential output
amplitude and reduced power consumption. See 1.1.6 The
LVDS Outputs. When the Extended Control Mode is
enabled, this pin functions as the SCLK input which clocks
in the serial data. See 1.2 NON-EXTENDED AND
EXTENDED CONTROL MODE for details on the Extended
Control Mode. See 1.3 THE SERIAL INTERFACE for
description of the serial interface.
Power Down Q-channel. A logic high on the PDQ pin puts
only the Q-channel into the Power Down Mode.
OutEdge / DDR /
SDATA
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. See 1.1.5.2 OutEdge and
Demultiplex Control Setting. When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is
enabled. When the Extended Control Mode is enabled, this
pin functions as the SDATA input. See 1.2 NON-EXTENDED
AND EXTENDED CONTROL MODE for details on the
Extended Control Mode. See 1.3 THE SERIAL
INTERFACE for description of the serial interface.
15
DCLK_RST /
DCLK_RST+
DCLK Reset. When single-ended DCLK_RST is selected by
floating or setting pin 52 logic high, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See 1.5 MULTIPLE ADC
SYNCHRONIZATION for detailed description. When
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
26
PD
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
CAL
Calibration Cycle Initiate. A minimum tCAL_L input clock
cycles logic low followed by a minimum of tCAL_H input clock
cycles high on this pin initiates the self calibration sequence.
See 2.4.2 Calibration for an overview of calibration and
2.4.2.2 On-Command Calibration for a description of oncommand calibration. The calibration cycle may similarly be
initiated via the CAL bit in the Calibration register (0h).
4
30
4
Symbol
Copyright © 1999-2012, Texas Instruments Incorporated
ADC07D1520
Pin Functions
Pin No.
14
127
18
19
Symbol
Equivalent Circuit
Description
FSR/ALT_ECE/
DCLK_RST-
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has three functions. It can
conditionally control the ADC full-scale voltage, enable the
Extended Control Mode, or become the negative polarity
signal of a differential pair in differential DCLK_RST mode.
If pin 52 is floating or at logic high and pin 41 is floating, this
pin can be used to set the full-scale-range or can be used as
an alternate Extended Control Mode enable pin. When used
as the FSR pin, a logic low on this pin sets the full-scale
differential input range to a reduced VIN input level . A logic
high on this pin sets the full-scale differential input range to
a higher VIN input level. See Converter Electrical
Characteristics. To enable the Extended Control Mode,
whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to VA/2. See 1.2 NON-EXTENDED AND EXTENDED
CONTROL MODE for information on the Extended Control
Mode. Note that pin 41 overrides the Extended Control Mode
enable of this pin. When pin 52 is held at logic low, this pin
acts as the DCLK_RST- pin. When in differential DCLK_RST
mode, there is no pin-controlled FSR and the full-scale-range
is defaulted to the higher VIN input level.
(Note 17)
CalDly / DES / SCS
Calibration Delay, Dual Edge Sampling and Serial Interface
Chip Select. In non-extended control mode, this pin functions
as the Calibration Delay select. A logic high or low the
number of input clock cycles after power up before
calibration begins (See 1.1.1 Calibration). When this pin is
floating or connected to a voltage equal to VA/2, DES (Dual
Edge Sampling) Mode is selected where the I-channel is
sampled at twice the input clock rate and the Q-channel is
ignored. See 1.1.5.1 Dual-Edge Sampling. In extended
control mode, this pin acts as the enable pin for the serial
interface input and the CalDly value becomes "0" (short
delay with no provision for a long power-up calibration delay).
(Note 17)
CLK+
CLK-
Differential clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See 1.1.2 Acquiring
the Input for a description of acquiring the input and 2.3 THE
CLOCK INPUTS for an overview of the clock inputs.
Copyright © 1999-2012, Texas Instruments Incorporated
5
ADC07D1520
Pin Functions
Pin No.
Equivalent Circuit
Description
VINIVINI+
VINQ+
VINQ−
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
14 in Non-Extended Control Mode and the Input Full-Scale
Voltage Adjust register in the Extended Control Mode. Refer
to the VIN specification in the Converter Electrical
Characteristics for the full-scale input range in the NonExtended Control Mode. Refer to 1.4 REGISTER
DESCRIPTION for the full-scale input range in the Extended
Control Mode.
7
VCMO
Common Mode Voltage. This pin is the common mode
output in d.c. coupling mode and also serves as the a.c.
coupling mode select pin. When d.c. coupling is used at the
analog inputs, the voltage output at this pin is required to be
the common mode input voltage at VIN+ and VIN−. When a.c.
coupling is used, this pin should be grounded. This pin is
capable of sourcing or sinking 100 μA. See 2.2 THE
ANALOG INPUT.
31
VBG
Bandgap output voltage. This pin is capable of sourcing or
sinking 100 μA and can drive a load up to 80 pF.
126
CalRun
32
REXT
10
11
22
23
34
35
41
6
Symbol
Calibration Running indication. This pin is at a logic high
when calibration is running.
(Note 17)
External bias resistor connection. Nominal value is 3.3 kΩ
(±0.1%) to ground. See 1.1.1 Calibration.
Tdiode_P
Tdiode_N
Temperature Diode Positive (Anode) and Negative
(Cathode). These pins may be used for die temperature
measurements, however no specified accuracy is implied or
guaranteed. Noise coupling from adjacent output data
signals has been shown to affect temperature
measurements using this feature. See 2.6.2 Thermal
Management.
ECE
Extended Control Enable. This pin always enables or
disables Extended Control Mode. When this pin is set logic
high, the Extended Control Mode is inactive and all control
of the device must be through control pins only . When it is
set logic low, the Extended Control Mode is active. This pin
overrides the Extended Control Enable signal set using pin
14.
Copyright © 1999-2012, Texas Instruments Incorporated
ADC07D1520
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
52
DRST_SEL
DCLK_RST select. This pin selects whether the DCLK is
reset using a single-ended or differential signal. When this
pin is floating or logic high, the DCLK_RST operation is
single-ended and pin 14 functions as FSR/ALT_ECE. When
this pin is logic low, the DCLK_RST operation becomes
differential with functionality on pin 15 (DCLK_RST+) and pin
14 (DCLK_RST-). When in differential DCLK_RST mode,
there is no pin-controlled FSR and the full-scale-range is
defaulted to the higher VIN input level. When pin 41 is set
logic low, the Extended Control Mode is active and the FullScale Voltage Adjust registers can be programmed.
(Note 17)
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
I- and Q-channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100Ω
differential resistor.
In Non-demultiplexed Mode, only these outputs are active.
104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
I- and Q-channel LVDS Data Outputs that are delayed by
one CLK cycle in the output demultiplexer. Compared with
the DI and DQ outputs, these outputs represent the earlier
time sample. These outputs should always be terminated
with a 100Ω differential resistor.
In Non-demultiplexed Mode, these outputs are disabled and
are high impedance. When disabled, these outputs must be
left floating.
OR+/DCLK2+
OR-/DCLK2-
Out Of Range, second Data Clock output. When functioning
as OR+/-, a differential high at these pins indicates that the
differential input is out of range (outside the range ±VIN/2 as
programmed by the FSR pin in Non-extended Control Mode
or the Input Full-Scale Voltage Adjust register setting in the
Extended Control Mode). This single out of range indication
is for both the I- and Q-channels, unless PDQ is asserted, in
which case it only applies to the I-channel input. When
functioning as DCLK2+/-, DCLK2 is the exact replica of
DCLK and outputs the same signal at the same rate. The
functionality of these pins is selectable in Extended Control
Mode only; default is OR+/-.
79
80
Copyright © 1999-2012, Texas Instruments Incorporated
7
ADC07D1520
Pin Functions
Pin No.
8
Symbol
Equivalent Circuit
Description
Data Clock. Differential Clock outputs used to latch the
output data. Delayed and non-delayed data outputs are
supplied synchronously to this signal. In 1:2 Demux Mode,
this signal is at 1/2 the input clock rate in SDR mode and at
1/4 the input clock rate in the DDR mode. In the Non-demux
Mode, DCLK can only be in DDR mode and is at 1/2 the input
clock rate. By default, the DCLK outputs are not active during
the termination resistor trim section of the calibration cycle.
If a system requires DCLK to run continuously during a
calibration cycle, the termination resistor trim portion of the
cycle can be disabled by setting the Resistor Trim Disable
(RTD) bit to logic high in the Extended Configuration
Register. This disables all subsequent termination resistor
trims after the initial trim which occurs during power-on
calibration. This output is not recommended as a system
clock unless the resistor trim is disabled.
81
82
DCLKDCLK+
2, 5, 8, 13,
16, 17, 20,
25, 28, 33,
128
VA
Analog power supply pins. Bypass these pins to ground.
40, 51, 62,
73, 88, 99,
110, 121
VDR
Output Driver power supply pins. Bypass these pins to DR
GND.
1, 6, 9, 12,
21, 24, 27
GND
Ground return for VA.
42, 53, 64,
74, 87, 97,
108, 119
DR GND
Ground return for VDR.
63, 98, 109,
120
NC
36 / 37
58 / 59
103 / 102
125 / 124
RSV+ / RSV-
No Connection. Make no connection to these pins.
Reserved. These pins may be left unconnected and floating,
or as recommended in 2.5.1 Terminating RSV Pins.
Copyright © 1999-2012, Texas Instruments Incorporated
ADC07D1520
Absolute Maximum Ratings
(Note 1, Note 2)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Supply Voltage (VA, VDR)
2.2V
Supply Difference
VDR - VA
0V to 100 mV
Voltage on Any Input Pin
(Except VIN+, VIN- )
−0.15V to (VA +0.15V)
Voltage on VIN+, VIN(Maintaining Common Mode)
Ground Difference
|GND - DR GND|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
-0.15V to 2.5V
0V to 100 mV
±25 mA
±50 mA
Maximum Package Power Dissipation at TA ≤ 85°C
2.35 W
2500V
250V
1000V
−65°C to +150°C
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
Charged Device Model
Storage Temperature
Operating Ratings
(Note 1, Note 2)
−40°C ≤ TA ≤ +85°C
Ambient Temperature Range
Supply Voltage (VA)
+1.8V to +2.0V
+1.8V to VA
Driver Supply Voltage (VDR)
Analog Input Common Mode Voltage
VCMO ±50 mV
VIN+, VIN- Voltage Range (Maintaining Common Mode)
0V to 2.15V
(100% duty cycle)
0V to 2.5V
(10% duty cycle)
Ground Difference
(|GND - DR GND|)
CLK Pins Voltage Range
0V
0V to VA
Differential CLK Amplitude
0.4VP-P to 2.0VP-P
Package Thermal Resistance
Package
θJA
θJC
Top of Package
θJC
Thermal Pad
128-Lead,
Exposed Pad LQFP
26°C / W
10°C / W
2.8°C / W
For soldering information please refer to http://www.ti.com/lit/an/snoa549c/snoa549c.pdf.(Note 5)
Copyright © 1999-2012, Texas Instruments Incorporated
9
ADC07D1520
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870
mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating;
Non-extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Demultiplex Mode; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise
noted. (Note 6, Note 7, Note 16, Note 18)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
INL
Integral Non-Linearity
(Best fit)
DC Coupled, 1 MHz Sine Wave Overranged
±0.3
±0.9
LSB (max)
DNL
Differential Non-Linearity
DC Coupled, 1 MHz Sine Wave Overranged
±0.15
±0.6
LSB (max)
7
Bits
Resolution with No Missing
Codes
VOFF
Offset Error
VOFF_ADJ
Input Offset Adjustment Range Extended Control Mode
PFSE
Positive Full-Scale Error
(Note 9)
±25
mV (max)
NFSE
Negative Full-Scale Error
(Note 9)
±25
mV (max)
FS_ADJ
Full-Scale Adjustment Range
Extended Control Mode
±15
%FS
−0.75
LSB
±45
mV
±20
1:2 DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ
FPBW
Full Power Bandwidth
C.E.R.
Code Error Rate
Gain Flatness
Non-DES Mode
2.0
GHz
10−18
Error/Sample
d.c. to 748 MHz
±0.5
dBFS
d.c. to 1.5 GHz
±1.0
fIN = 373 MHz, VIN = FSR − 0.5 dB
6.8
ENOB
Effective Number of Bits
fIN = 748 MHz, VIN = FSR − 0.5 dB
6.8
SINAD
Signal-to-Noise Plus Distortion fIN = 373 MHz, VIN = FSR − 0.5 dB
Ratio
fIN = 748 MHz, VIN = FSR − 0.5 dB
43
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
2nd Harm
Second Harmonic Distortion
3rd Harm
SFDR
IMD
Third Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Out of Range Output Code
dBFS
6.3
Bits (min)
39.5
dB (min)
40.8
dB (min)
Bits
43
dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
43.2
fIN = 748 MHz, VIN = FSR − 0.5 dB
43.2
fIN = 373 MHz, VIN = FSR − 0.5 dB
−55
fIN = 748 MHz, VIN = FSR − 0.5 dB
−60
dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
−63
dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
−63
dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
−58
dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
−67
fIN = 373 MHz, VIN = FSR − 0.5 dB
57
fIN = 748 MHz, VIN = FSR − 0.5 dB
61
dB
−50
dB
fIN1 = 365 MHz, VIN = FSR − 7 dB
fIN2 = 375 MHz, VIN = FSR − 7 dB
dB
-47
dB (max)
dB
45.5
(VIN+) − (VIN−) > + Full Scale
127
(VIN+) − (VIN−) < − Full Scale
0
dB (min)
1:4 DEMUX DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ
FPBW
Full Power Bandwidth
DES Mode
1.3
GHz
ENOB
Effective Number of Bits
fIN = 748 MHz, VIN = FSR − 0.5 dB
6.7
Bits
SINAD
Signal to Noise Plus Distortion
fIN = 748 MHz, VIN = FSR − 0.5 dB
Ratio
42
dB
SNR
Signal to Noise Ratio
fIN = 748 MHz, VIN = FSR − 0.5 dB
43
dB
THD
Total Harmonic Distortion
fIN = 748 MHz, VIN = FSR − 0.5 dB
−52
dB
2nd Harm
Second Harmonic Distortion
fIN = 748 MHz, VIN = FSR − 0.5 dB
−57
dB
10
Copyright © 1999-2012, Texas Instruments Incorporated
ADC07D1520
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
Units
(Limits)
3rd Harm
Third Harmonic Distortion
fIN = 748 MHz, VIN = FSR − 0.5 dB
−57
dB
SFDR
Spurious Free Dynamic Range fIN = 748 MHz, VIN = FSR − 0.5 dB
52
dB
ANALOG INPUT AND REFERENCE CHARACTERISTICS
VIN
Full Scale Analog Differential
Input Range
VCMI
Common Mode Input Voltage
CIN
Analog Input Capacitance,
Normal operation
(Note 10, Note 11)
RIN
FSR pin 14 Low
(Note 12)
650
FSR pin 14 High
870
VCMO
590
mVP-P (min)
730
mVP-P (max)
800
mVP-P (min)
940
mVP-P (max)
VCMO − 0.05
V (min)
VCMO + 0.05
V (max)
Differential
0.02
pF
Each input pin to ground
1.6
pF
Differential
Analog Input Capacitance,
DES Mode (Note 10, Note 11) Each input pin to ground
0.08
pF
2.2
pF
Differential Input Resistance
100
94
Ω (min)
106
Ω (max)
0.95
1.45
V (min)
V (max)
ANALOG OUTPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage ICMO = ±100 µA
1.26
TC VCMO
Common Mode Output Voltage
TA = −40°C to +85°C
Temperature Coefficient
118
ppm/°C
VCMO_LVL
VCMO input threshold to set D.C. VA = 1.8V
Coupling mode
VA = 2.0V
0.60
V
0.66
V
CLOAD VCMO
Maximum VCMO Load
Capacitance
VBG
Bandgap Reference Output
Voltage
IBG = ±100 µA
TC VBG
Bandgap Reference Voltage
Temperature Coefficient
TA = −40°C to +85°C,
IBG = ±100 µA
CLOAD VBG
Maximum Bandgap Reference
load Capacitance
1.26
80
pF
1.20
1.34
V (min)
V (max)
28
ppm/°C
80
pF
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Match
1
LSB
1
LSB
Positive Full-Scale Match
Zero offset selected in Control Register
Negative Full-Scale Match
Zero offset selected in Control Register
1
LSB
Phase Matching (I, Q)
fIN = 1.5 GHz
工商网监
湘ICP备2023018690号
