ADC08100CIMTC

ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 ADC08100 8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter Check for Samples: ADC08100 FEATURES DESCRIPTION • • • • • The ADC08100 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-andhold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 20 Msps to 100 Msps with outstanding dynamic performance over its full operating range while consuming just 1.3 mW per MHz of clock frequency. That's just 130 mW of power at 100 Msps. Raising the PD pin puts the ADC08100 into a Power Down mode where it consumes just 1 mW. 1 2 Single-ended Input Internal Sample-and-hold Function Low Voltage (Single +3V) Operation Small Package Power-down Feature APPLICATIONS • • • • • • • • • Flat Panel Displays Projection Systems Set-top Boxes Battery-powered Instruments Communications Medical Scan Converters X-ray Imaging High Speed Viterbi Decoders Astronomy KEY SPECIFICATIONS • • • • • • Resolution 8 bits Maximum Sampling Frequency 100 Msps (Min) DNL 0.4 LSB (Typ) ENOB 7.4 Bits (Typ) at fIN = 41 MHz THD –60 dB (Typ) Power Consumption – Operating 1.3 mW/Msps (Typ) – Power Down: 1 mW (Typ) The unique architecture achieves 7.4 Effective Bits with 41 MHz input frequency. The excellent DC and AC characteristics of this device, together with its low power consumption and single +3V supply operation, make it ideally suited for many imaging and communications applications, including use in portable equipment. Furthermore, the ADC08100 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08100's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 3V or 2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS compatible. The output format is straight binary The ADC08100 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40°C to +85°C. PIN CONFIGURATION 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Block Diagram DR VD (pin 18) VA VRT 17 COARSE/FINE COMPARATORS 1 ENCODER & ERROR CORRECTION 8 17 8 SWITCHES VRM MUX 17 256 ENCODER & ERROR CORRECTION 8 COARSE/FINE COMPARATORS VIN GND AGND PD 8 OUTPUT DRIVERS DATA OUT CLOCK GEN VRB CLK VIN DR GND (pin 17) PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See THE ANALOG INPUT for more information. 9 VRM Mid-point of the reference ladder. This pin should be bypassed to a clean, quiet point in the analog ground plane with a 0.1 µF capacitor. 10 VRB Analog Input that is the low side (bottom) of the reference ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V). Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See THE ANALOG INPUT for more information. 23 PD Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins hold the last conversion result. 24 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input. VD Description DGND 2 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol 13 thru 16 and 19 thru 22 D0–D7 7 VIN GND 1, 4, 12 VA 18 DR VD 17 DR GND 2, 5, 8, 11 AGND Equivalent Circuit Description Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. Reference ground for the single-ended analog input, VIN. Positive analog supply pin. Connect to a clean, quiet voltage source of +3V. VA should be bypassed with a 0.1 µF ceramic chip capacitor for each pin, plus one 10 µF capacitor. See POWER SUPPLY CONSIDERATIONS for more information. Power supply for the output drivers. If connected to VA, decouple well from VA. The ground return for the output driver supply. The ground return for the analog supply. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VA) 3.8V Driver Supply Voltage (DR VD) VA + 0.3V Voltage on Any Input or Output Pin −0.3V to VA Reference Voltage (VRT, VRB) VA to AGND −0.3V to (VA + 0.3V) CLK, OE Voltage Range Digital Output Voltage (VOH, VOL) DR GND to DR VD Input Current at Any Pin (4) ±25 mA Package Input Current (4) ±50 mA See (5) Power Consumption at TA = 25°C ESD Susceptibility (6) Human Body Model 2500V Machine Model 250V Soldering Temperature, Infrared, 10 seconds 235°C −65°C to +150°C Storage Temperature (1) (2) (3) (4) (5) (6) All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see Converter Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. In the 24-pin TSSOP, θJA is 92°C/W. The power consumption of this device under normal operating conditions is far below the package limit, which will be reached only when the ADC08100 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 3 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Range Supply Voltage (VA) +2.7V to +3.6V Driver Supply Voltage (DR VD) +2.4V to VA Ground Difference |GND - DR GND| 0V to 300 mV Upper Reference Voltage (VRT) 1.0V to (VA + 0.1V) Lower Reference Voltage (VRB) 0V to (VRT − 1.0V) VIN Voltage Range (1) (2) 4 VRB to VRT Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see Converter Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 Converter Electrical Characteristics The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 100 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) Symbol Parameter Conditions Typical Limits (4) (4) Units (Limits) DC ACCURACY 8 Bits INL Resolution with no missing codes Integral Non-Linearity ±0.5 ±1.3 LSB (max) DNL Differential Non-Linearity ±0.4 +1.0 −0.95 LSB (max) LSB (min) FSE Full Scale Error 18 ±28 mV (max) VOFF Zero Scale Offset Error 26 ±35 mV (max) ANALOG INPUT AND REFERENCE CHARACTERISTICS V (min) VRT V (max) Input Voltage CIN VIN Input Capacitance 4 pF RIN RIN Input Resistance >1 MΩ BW Full Power Bandwidth 200 MHz VRT Top Reference Voltage 1.9 VRB 1.6 VRB VIN VIN = 0.75V +0.5 Vrms (CLK LOW) (CLK HIGH) Bottom Reference Voltage 0.3 VRT - VRB Reference Delta RREF IREF (1) (2) (3) (4) Reference Ladder Resistance 3 1.6 VRT to VRB Reference Ladder Current 220 7.3 pF VA V (max) 1.0 V (min) VRT − 1.0 V (max) 0 V (min) 1.0 V (min) 2.3 V (max) 150 Ω (min) 300 Ω (max) 5.3 mA (min) 10.6 mA (max) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only and are not ensured. The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input voltage must be ≤2.6VDC to ensure accurate conversions. To ensure accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures represent most likely parametric norms at TJ = 25°C. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 5 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 100 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3) Symbol Parameter Typical Conditions (4) Limits (4) Units (Limits) CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage DR VD = VA = 3.3V 2.0 V (min) VIL Logical Low Input Voltage DR VD = VA = 2.7V 0.8 V (max) IIH Logical High Input Current VIH = DR VD = VA = 3.3V 10 nA IIL Logical Low Input Current VIL = 0V, DR VD = VA = 2.7V −50 nA CIN Logic Input Capacitance 3 pF DIGITAL OUTPUT CHARACTERISTICS VOH High Level Output Voltage VA = DR VD = 2.7V, IOH = −400 µA 2.6 2.4 V (min) VOL Low Level Output Voltage VA = DR VD = 2.7V, IOL = 1.0 mA 0.4 0.5 V (max) fIN = 4 MHz, VIN = −0.25 dBFS 7.5 fIN = 10 MHz, VIN = −0.25 dBFS 7.5 7.0 Bits (min) fIN = 41 MHz, VIN = −0.25 dBFS, TA= 25°C 7.3 6.9 Bits (min) fIN = 41 MHz, VIN = −0.25 dBFS, TA = TMIN to TMAX 7.3 6.8 Bits (min) fIN = 49.8 MHz, VIN = −0.25 dBFS 7.2 fIN = 4 MHz, VIN = −0.25 dBFS 47 fIN = 10 MHz, VIN = −0.25 dBFS 47 43.9 dB (min) fIN = 41 MHz, VIN = −0.25 dBFS, TA= 25°C 46 43.3 dB (min) fIN = 41 MHz, VIN = −0.25 dBFS, TA = TMIN to TMAX 46 42.7 dB (min) fIN = 49.8 MHz, VIN = −0.25 dBFS 45 dB fIN = 4 MHz, VIN = −0.25 dBFS 47 dB DYNAMIC PERFORMANCE ENOB SINAD SNR SFDR THD HD2 HD3 IMD 6 Effective Number of Bits Signal-to-Noise & Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion 2nd Harmonic Distortion 3rd Harmonic Distortion Intermodulation Distortion Bits Bits dB fIN = 10 MHz, VIN = −0.25 dBFS 47 44 dB (min) fIN = 41 MHz, VIN = −0.25 dBFS 46.5 42.8 dB (min) fIN = 49.8 MHz, VIN = −0.25 dBFS 45.8 dB fIN = 4 MHz, VIN = −0.25 dBFS 61 dBc fIN = 10 MHz, VIN = −0.25 dBFS 60 dBc fIN = 41 MHz, VIN = −0.25 dBFS 63 dBc fIN = 49.8 MHz, VIN = −0.25 dBFS 54 dBc fIN = 4 MHz, VIN = −0.25 dBFS −61 dBc fIN = 10 MHz, VIN = −0.25 dBFS −60 dBc fIN = 41 MHz, VIN = −0.25 dBFS -60 dBc fIN = 49.8 MHz, VIN = −0.25 dBFS −54 dBc fIN = 4 MHz, VIN = −0.25 dBFS -62 dBc fIN = 10 MHz, VIN = −0.25 dBFS −60 dBc fIN = 41 MHz, VIN = −0.25 dBFS -63 dBc fIN = 49.8 MHz, VIN = −0.25 dBFS −54 dBc fIN = 4 MHz, VIN = FS − 0.25 dB −68 dBc fIN = 10 MHz, VIN = −0.25 dBFS −65 dBc fIN = 41 MHz, VIN = −0.25 dBFS -64 dBc fIN = 49.8 MHz, VIN = −0.25 dBFS −68 dBc f1 = 9 MHz, VIN = −6.25 dBFS f2 = 10 MHz, VIN = −6.25 dBFS -48 dBc Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 Converter Electrical Characteristics (continued) The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 100 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3) Symbol Typical Limits (4) Units (Limits) DC Input 41 50 mA (max) fIN = 10 MHz, VIN = −3 dBFS 41 DC Input 1 Parameter Conditions (4) POWER SUPPLY CHARACTERISTICS IA Analog Supply Current DR ID IA + DR ID Output Driver Supply Current (5) Total Operating Current fIN = 10 MHz, VIN = −3 dBFS 8 DC Input 42 fIN = 10 MHz, VIN = −3 dBFS, PD = Low 49 mA (max) 2 mA (max) mA (max) 52 mA (max) CLK Low, PD = Hi 0.2 DC Input 126 fIN = 10 MHz, VIN = −3 dBFS, PD = Low 147 mW 156 mW (max) PC Power Consumption CLK Low, PD = Hi 0.6 mW PSRR1 Power Supply Rejection Ratio FSE change with 2.7V to 3.3V change in VA 54 dB Power Supply Rejection Ratio Rejection of 150 mV at 9.8 MHz riding upon supply 33 dB PSRR2 AC ELECTRICAL CHARACTERISTICS fC1 Maximum Conversion Rate 125 fC2 Minimum Conversion Rate 20 tCL Minimum Clock Low Time 4.5 ns (min) tCH Minimum Clock High Time 4.5 ns (min) tOH Output Hold Time CLK Rise to Data Invalid 4.4 tOD Output Delay CLK Rise to Data Valid 5.9 8.5 ns (max) Pipeline Delay (Latency) tAD Sampling (Aperture) Delay tAJ Aperture Jitter (5) 2.5 CLK Fall to Acquisition of Data 100 MHz (min) MHz ns Clock Cycles 1.5 ns 2 ps rms IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1 + … + C71 x f7) where VDR is the output driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the average frequency at which that pin is toggling. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 7 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes low. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first code and the negative reference voltage. Bottom Offset is defined as EOB = VZT – VRB, where VZT is the first code transition input voltage. VRB is the lower reference voltage. Note that this is different from the normal Zero Scale Error. CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. Measured at 100 Msps with a ramp input. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input signal is the full power bandwidth. FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and is defined as: Vmax + 1.5 LSB – VRT where • max is the voltage at which the transition to the maximum (full scale) code occurs. (1) INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. Measured at 100 Msps with a ramp input. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. MISSING CODE are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the Output Delay. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding D.C. 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where • where F1 is the RMS power of the fundamental (input) frequency and f2 through f10 is the power in the first 9 harmonics in the output spectrum. (2) ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is defined as VOFF = VZT − VRB where • where VZT is the first code transition input voltage. (3) Timing Diagram Figure 1. ADC08100 Timing Diagram Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 9 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless otherwise stated 10 INL INL vs. Temperature Figure 2. Figure 3. INL vs. Supply Voltage INL vs. Sample Rate Figure 4. Figure 5. DNL DNL vs. Temperature Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless otherwise stated DNL vs. Supply Voltage DNL vs. Sample Rate Figure 8. Figure 9. SNR vs. Temperature SNR vs. Supply Voltage Figure 10. Figure 11. SNR vs. Sample Rate SNR vs. Input Frequency Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 11 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless otherwise stated 12 SNR vs. Clock Duty Cycle Distortion vs. Temperature Figure 14. Figure 15. Distortion vs. Supply Voltage Distortion vs. Sample Rate Figure 16. Figure 17. Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless otherwise stated SINAD/ENOB vs. Temperature SINAD/ENOB vs. Supply Voltage Figure 20. Figure 21. SINAD/ENOB vs. Sample Rate SINAD/ENOB vs. Input Frequency Figure 22. Figure 23. SINAD/ENOB vs. Clock Duty Cycle Power Consumption vs. Sample Rate Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 13 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless otherwise stated 14 Spectral Response @ fIN = 10 MHz Spectral Response @ fIN = 41 MHz Figure 26. Figure 27. Spectral Response @ fIN = 76 MHz Intermodulation Distortion (IMD) Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 FUNCTIONAL DESCRIPTION The ADC08100 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and beyond 50 MHz. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRB will cause the output word to consist of all ones. Incorporating a switched capacitor bandgap, the ADC08100 exhibits a power consumption that is proportional to frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit needs. Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs 2.5 clock cycles plus tOD later. The ADC08100 will convert as long as the clock signal is present. The output coding is straight binary. The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in the power down mode, where the output pins hold the last conversion before the PD pin went high and the device consumes just 1 mW. Applications Information REFERENCE INPUTS The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in Operating Ratings. Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin. The reference bias circuit of Figure 30 is very simple and the performance is adequate for many applications. However, circuit tolerances will lead to a wide reference voltage range. Superior performance can generally be achieved by driving the reference pins with low impedance sources. The circuit of Figure 31 will allow a more accurate setting of the reference voltages. The upper amplifier must be able to source the reference current as determined by the value of the reference resistor and the value of (VRT − VRB). The lower amplifier must be able to sink this reference current. Both should be stable with a capacitive load. The LM8272 was chosen because of its rail-to-rail input and output capability, its high current output and its ability to drive large capacitance loads. The divider resistors at the inputs to the amplifiers could be changed to suit the application reference voltage needs, or the divider can be replaced with potentiometers or DACs for precise settings. The bottom of the ladder (VRB) may be returned to ground if the minimum input signal excursion is 0V. VRT should always be more positive than VRB by the minimum VRT - VRB difference in the Electrical Characteristics table to minimize noise. Furthermore, the difference between VRT and VRB should not exceed the maximum value specified in Converter Electrical Characteristics to avoid signal distortion. The VRM pin is the center of the reference ladder and should be bypassed to a clean, quiet point in the analog ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 15 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Choke +3V 10 PF + + 0.1 PF 1 4 0.1 PF 12 VA 6 + 10 PF 10 PF 0.1 PF 18 DR VD VIN +3V 7 VIN GND 110 1% 1.5V, nominal V RT 3 + 10 PF 0.1 PF 220 1% ADC08100 9 0.1 PF D7 D6 D5 D4 D3 D2 D1 D0 13 14 15 16 19 20 21 22 10 VRB 23 PD AGND 2 DR GND CLK 5 8 11 17 24 Because of the ladder and external resistor tolerances, the reference voltage can vary too much for some applications. Figure 30. Simple, Low Component Count Reference Biasing +3V Choke 10 PF + 10 PF 0.1 PF 3 8 + 2 1 1/2 LM8272 VIN - 1 4 12 0.1 PF 18 VA 6 DR VD 7 4 0.1 PF VIN GND 0.01 PF 3 D7 D6 D5 D4 D3 D2 D1 D0 VRT 1 PF 4.7k 9 1.62k ADC08100 0.1 PF 4.7k 10 13 14 15 16 19 20 21 22 VRB 1 PF 0.1 PF 10 PF +3V 1 PF 604: LM4040-2.5 + + 470: 0.01 PF 6 5 - 7 + 1/2 LM8272 23 PD AGND 2 5 8 11 DR GND CLK 17 24 309: Figure 31. Driving the Reference to Force Desired Values Requires Driving With a Low Impedance Source 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 THE ANALOG INPUT The analog input of the ADC08100 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature of the analog input causes current spikes at the input that result in voltage spikes there. Any amplifier used to drive the analog input must be able to settle within the clock high time. The LMH6702 and the LMH6628 have been found to be good amplifiers to drive the ADC08100. Figure 32 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a higher gain, as shown in Figure 32. Choke +3V 10 PF 0.1 PF 200 12 - * + 10 PF 0.1 PF Gain Adjust 10 240 Signal Input + +5V 1 22 LMH6702 + 6 VA VIN 47 DR VD VIN GND ADC08100 0.1 PF 0.33 PF VRT 3 * * 4.7k 9 VRM +3V 1k 1k Offset Adjust 0.1 PF 18 10 pF 7 100 4 12 -5V D7 D6 D5 D4 D3 D2 D1 D0 13 14 15 16 19 20 21 22 10 VRB 17 DR GND Ground connections marked with "*" should enter the ground plane at a common point. 23 PD CLK 24 AGND 2 5 7 8 11 Figure 32. The Input Amplifier Should Incorporate Some Gain for Best Performance (see text) The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but also on the circuit layout and board material. A resistor value should be chosen between 18Ω and 47Ω and the capacitor value chose according to the formula: (4) The value of "C" in the formula above should include the ADC input capacitance when the clock is high. This will provide optimum SNR performance for Nyquist applications. Best THD performance is realized when the capacitor and resistor values are both zero, but this would compromise SNR and SINAD performance. Generally, there should be no resistor or capacitor between the ADC input and any amplifier for undersampling applications. The circuit of Figure 32 has both gain and offset adjustments. If you eliminate these adjustments normal circuit tolerances may cause signal clipping unless care is exercised in the worst case analysis of component tolerance and the input signal excursion is appropriately limited to account for the worst case conditions. Of course, this means that the designer will not be able to depend upon getting a full scale output with maximum signal input. Full scale and offset adjustments may also be made by adjusting VRT and VRB, perhaps with the aid of a pair of DACs. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 17 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com POWER SUPPLY CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source is recommended for the VA and DR VD supplies of the ADC08100, these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins. As is the case with all high speed converters, the ADC08100 should be assumed to have little power supply rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other analog circuitry. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300 mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC08100 power pins. THE DIGITAL INPUT PINS The ADC08100 has two digital input pins: The PD pin and the Clock pin. The PD Pin The Power Down (PD) pin, when high, puts the ADC08100 into a low power mode where power consumption is reduced to 1 mW. Output data is valid and accurate about 1 microsecond after the PD pin is brought low. The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is high. The ADC08100 Clock Although the ADC08100 is tested and its performance is ensured with a 100 MHz clock, it typically will function well with clock frequencies from 20 MHz to 125 MHz. Halting the clock will provide nearly as much power saving as raising the PD pin high. Typical power consumption with a stopped clock is 3 mW, compared to 1 mW when PD is high. The digital outputs will remain in the same state as they were before the clock was halted. Once the clock is restored (or the PD pin is brought low), there is a time of about 1 microsecond before the output data is valid. However, because of the linear relationship between total power consumption and clock frequency, the part requires about one microsecond after the clock is restarted or substantially changed in frequency before the part returns to its specified accuracy. The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC08100 is designed to maintain performance over a range of duty cycles. While it is specified and performance is ensured with a 50% clock duty cycle and 100 Msps, ADC08100 performance is typically maintained with clock high and low times of 2 ns, corresponding to a clock duty cycle range of 20% to 80% with a 100 MHz clock. Note that the clock high and low times of 2 ns may not be asserted together. The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If the clock line is longer than where • • tr is the clock rise time tPD is the propagation rate of the signal along the trace (5) The CLOCK pin should be a.c. terminated with a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is: 18 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 where • tPD is the signal propagation rate down the clock line (6) "L" is the line length and Zo is the characteristic impedance of the clock line. This termination should be located as close as possible to, but within one centimeter of, the ADC08100 clock pin. Typical tPD is about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes where • L is the length of the clock line in inches. (7) LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog and digital ground plane should be used. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High power digital components should not be located on or near a straight line between the ADC or any linear component and the power supply area as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC. The DR Gnd connection to the ground plane should not use the same feedthrough use by other ground connections. Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the analog ground plane. Single Ground Plane ADC Clock Source Locate driving amplifier near ADC input pin RF Locate Clock Source near ADC clock pin RIN R C LMH6702 ADC 08100 Locate power supply on the digital side of the ADC Figure 33. Layout Example Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 19 ADC08100 SNAS060I – JUNE 2000 – REVISED MAY 2013 www.ti.com Figure 33 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed together away from any digital components. DYNAMIC PERFORMANCE The ADC08100 is AC tested and its dynamic performance is ensured. To meet the published specifications, the clock source driving the CLK input must exhibit less than 3 ps (rms) of jitter. For best AC performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 34. It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the analog path. Figure 34. Isolating the ADC Clock from Digital Circuitry COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in series with the offending digital input will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC08100. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from DR VD and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 10 pF. Dynamic performance can also be improved by adding 100Ω series resistors at each digital output, reducing the energy coupled back into the converter input pins. Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, the capacitance seen at the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The LMH6702 and the LMH6628 have been found to be good devices for driving the ADC08100. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally inadequate as a clock source. 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 REVISION HISTORY Changes from Revision H (May 2013) to Revision I • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC08100 21 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADC08100CIMTC ACTIVE TSSOP PW 24 61 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 85 ADC08100 CIMTC ADC08100CIMTC/NOPB ACTIVE TSSOP PW 24 61 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ADC08100 CIMTC ADC08100CIMTCX/NOPB ACTIVE TSSOP PW 24 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ADC08100 CIMTC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of