ADC08D1000CIYB/NOPB

Product Folder Order Now Technical Documents Tools & Software Support & Community ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter 1 Features 4 Description • • • • • • • • The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the selfcalibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. 1 • Internal Sample-and-Hold Single +1.9V ±0.1V Operation Choice of SDR or DDR Output Clocking Interleave Mode for 2x Sampling Rate Multiple ADC Synchronization Capability Ensured No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock 2 Applications • • • • • Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation 3 Key Specifications • • • • • • Resolution: 8 Bits Max Conversion Rate: 1 GSPS (min) Bit Error Rate: 10-18 (typ) ENOB @ 500 MHz Input: 7.4 Bits (typ) DNL: ±0.15 LSB (typ) Power Consumption – Operating: 1.6 W (typ) – Power Down Mode: 3.5 mW (typ) Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. Patenting Notice: The Texas Instruments products covered by this datasheet are protected by at least the following U.S. patents: Pat. No. 6,847,320; Pat. No. 7,015,729; Pat. No. 7,068,195; and Pat. No. 7,088,281. This list of patents may not be all inclusive, and the products covered by this datasheet may be protected by additional issued patents and patents pending both in the U.S. and elsewhere in the world. A copy of this datasheet including the patent list noted here is also available on the Internet www.ti.com/lit/gpn/adc08d1000. This is intended to serve as notice under 35 U.S.C. § 287(a). 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 10 11 Features .................................................................. Applications ........................................................... Key Specifications ................................................. Description ............................................................. Revision History..................................................... Block Diagram........................................................ Pin Configuration................................................... Absolute Maximum Ratings.................................. Operating Ratings.................................................. Package Thermal Resistance............................... Converter Electrical Characteristics ................... 1 1 1 1 2 3 4 8 9 9 9 11.1 Specification Definitions ........................................ 15 11.2 Transfer Characteristic.......................................... 17 11.3 TEST CIRCUIT DIAGRAMS ................................. 17 12 Typical Performance Characteristics................ 20 13 Functional Description ....................................... 25 13.1 OVERVIEW........................................................... 25 13.2 NORMAL/EXTENDED CONTROL........................ 28 13.3 THE SERIAL INTERFACE.................................... 30 13.4 REGISTER DESCRIPTION .................................. 31 13.5 MULTIPLE ADC SYNCHRONIZATION ................ 35 14 APPLICATIONS INFORMATION ......................... 36 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 THE REFERENCE VOLTAGE.............................. THE ANALOG INPUT ........................................... THE CLOCK INPUTS ........................................... CONTROL PINS ................................................... THE DIGITAL OUTPUTS...................................... POWER CONSIDERATIONS ............................... LAYOUT AND GROUNDING................................ DYNAMIC PERFORMANCE................................. USING THE SERIAL INTERFACE ....................... COMMON APPLICATION PITFALLS ................. 36 36 38 39 43 43 45 46 46 47 15 Device and Documentation Support ................. 48 15.1 Trademarks ........................................................... 48 15.2 Electrostatic Discharge Caution ............................ 48 15.3 Glossary ................................................................ 48 16 Mechanical, Packaging, and Orderable Information ........................................................... 48 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (April 2013) to Revision I • Added Patenting Notice ......................................................................................................................................................... 1 Changes from Revision G (April 2013) to Revision H • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 47 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 6 Block Diagram Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 3 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC DR GND DId6+ DId6DId7+ DId7DI0+ DI0DI1+ DI1VDR NC DR GND 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 ADC08D1000 * DI2+ DI2DI3+ DI3DI4+ DI4DI5+ DI5VDR DR GND DI6+ DI6DI7+ DI7DCLK+ DCLKOROR+ DQ7DQ7+ DQ6DQ6+ DR GND VDR DQ5DQ5+ DQ4DQ4+ DQ3DQ3+ DQ2DQ2+ GND DR GND DQd2+ DQd2DQd3+ DQd3DQd4+ DQd4DQd5+ DQd5VDR NC DR GND DQd6+ DQd6DQd7+ DQd7DQ0+ DQ0DQ1+ DQ1VDR NC DR GND VA Tdiode_p Tdiode_n DQd0+ DQd0DQd1+ DQd1VDR 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND VA OUTV/SCLK OutEdge/DDR/SDATA VA GND VCMO VA GND VINIVINI+ GND VA FSR/ECE DCLK_RST VA VA CLK+ CLKVA GND VINQ+ VINQGND VA PD GND VA PDQ CAL VBG REXT 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 VA CalDly/DES/SCS CalRun DId0+ DId0DId1+ DId1VDR NC DR GND DId2+ DId2DId3+ DId3DId4+ DId4DId5+ DId5VDR 7 Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. Figure 1. HLQFP Package See Package Number NNB0128A 4 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description VA Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. SeeThe LVDS Outputs. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See NORMAL/EXTENDED CONTROL for details on the extended control mode. See THE SERIAL INTERFACE for description of the serial interface. 50k 3 OutV / SCLK GND VA 50k 200k 4 50k OutEdge / DDR / SDATA DDR 8 pF GND SDATA DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See OutEdge Setting). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See NORMAL/EXTENDED CONTROL for details on the extended control mode. See THE SERIAL INTERFACE for description of the serial interface. VA DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See MULTIPLE ADC SYNCHRONIZATION for detailed description. VA 15 DCLK_RST/DCL K_RST- 26 PD Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. CAL Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the self calibration sequence. See Self Calibration for an overview of self-calibration and On-Command Calibration for a description of on-command calibration. 30 GND VA 50 k: 29 A logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode. PDQ GND VA 50k 14 200k FSR/ECE 50k 8 pF GND Full Scale Range Select and Extended Control Enable. In nonextended control mode, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level . A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See NORMAL/EXTENDED CONTROL for information on the extended control mode. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 5 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Pin Descriptions and Equivalent Circuits (continued) Pin Functions Pin No. Symbol Equivalent Circuit Description VA Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See Self-Calibration). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the input clock rate and the "Q" input is ignored. See Dual-Edge Sampling. 50k 127 CalDly / DES / SCS 50k GND VA 18 19 50k AGND CLK+ CLK- 100 VA VBIAS 50k LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See Acquiring the Input for a description of acquiring the input and THE CLOCK INPUTS for an overview of the clock inputs. AGND VA 50k 11 10 VINI+ VINI− 22 23 VINQ+ VINQ− AGND VCMO 100 Control from VCMO VA 50k Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in normal mode and the Input Full-Scale Voltage Adjust register in the extended control mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the normal mode. Refer to REGISTER DESCRIPTION for the fullscale input range in the extended control mode. AGND VA 7 Common Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100μA. See THE ANALOG INPUT. VCMO GND VD 31 VBG 126 CalRun Bandgap output voltage capable of 100 μA source/sink. Calibration Running indication. This pin is at a logic high when calibration is running. DGND 6 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Pin Descriptions and Equivalent Circuits (continued) Pin Functions Pin No. Symbol Equivalent Circuit Description VA V 32 External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Self-Calibration. REXT GND Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be used for die temperature measurements, however no specified accuracy is implied or ensured. Noise coupling from adjacent output data signals has been shown to affect temperature measurements using this feature. See Thermal Management. Tdiode_P 34 35 Tdiode_P Tdiode_N 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 / 105 / 106 / 107 / 111 / 112 / 113 / 114 / 115 / 116 / 117 / 118 / 122 / 123 / 124 / 125 / 57 56 55 54 50 49 48 47 46 45 44 43 39 38 37 36 DI7− / DI7+ / DI6− / DI6+ / DI5− / DI5+ / DI4− / DI4+ / DI3− / DI3+ / DI2− / DI2+ / DI1− / DI1+ / DI0− / DI0+ / Tdiode_N DQ7− DQ7+ DQ6− DQ6+ DQ5− DQ5+ DQ4− DQ4+ DQ3− DQ3+ DQ2− DQ2+ DQ1− DQ1+ DQ0− DQ0+ DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. VDR - + - + I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. DR GND OR+ OR- Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in non-extended control mode or the Input Full-Scale Voltage Adjust register setting in the extended control mode). 82 81 DCLK+ DCLK- Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. The DCLK outputs are not active during a calibration cycle, therefore this is not recommended as a system clock. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 VA 79 80 Analog power supply pins. Bypass these pins to ground. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 7 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Pin Descriptions and Equivalent Circuits (continued) Pin Functions Pin No. Symbol Equivalent Circuit Description 40, 51 ,62, 73, 88, 99, 110, 121 VDR Output Driver power supply pins. Bypass these pins to DR GND. 1, 6, 9, 12, 21, 24, 27, 41 GND Ground return for VA. 42, 53, 64, 74, 87, 97, 108, 119 DR GND Ground return for VDR. 52, 63, 98, 109, 120 NC No Connection. Make no connection to these pins. 8 Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VA, VDR) 2.2V Supply Difference (VDR - VA) 0V to 100 mV Voltage on Any Input Pin (Except VIN+, VIN- ) −0.15V to (VA +0.15V) Voltage on VIN+, VIN(Maintaining Common Mode) -0.15V to 2.5V Ground Difference |GND - DR GND| 0V to 100 mV Input Current at Any Pin (4) ±25 mA Package Input Current (4) ±50 mA Power Dissipation at TA ≤ 85°C ESD Susceptibility (5) Soldering Temperature 2.0 W Human Body Model (3) (4) (5) (6) 8 250V Infrared, 10 seconds (6)(Applies to standard plated package only) 235°C −65°C to +150°C Storage Temperature (1) (2) 2500V Machine Model All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Soldering Process must comply with Reflow Temperature Profile Specifications. Refer to http://www.ti.com/packaging. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 9 Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Ambient Temperature Range Supply Voltage (VA) +1.8V to +2.0V Driver Supply Voltage (VDR) +1.8V to VA Analog Input Common Mode Voltage VCMO ±50mV VIN+, VIN- Voltage Range (Maintaining Common Mode) 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) Ground Difference (|GND - DR GND|) 0V CLK Pins Voltage Range 0V to VA Differential CLK Amplitude (1) (2) 0.4VP-P to 2.0VP-P Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified. 10 Package Thermal Resistance Package θJA θJC(Top of Package) θJ-PAD (Thermal Pad) 128-Lead Exposed Pad HLQFP 25°C / W 10°C / W 2.8°C / W 11 Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (1) (2) Parameter Test Conditions Typical (3) Limits (3) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL Integral Non-Linearity (Best fit) DC Coupled, 1MHz Sine Wave Over ranged ±0.3 ±0.9 LSB (max) DNL Differential Non-Linearity DC Coupled, 1MHz Sine Wave Over ranged ±0.15 ±0.6 LSB (max) 8 Bits −1.5 0.5 LSB (min) LSB (max) Resolution with No Missing Codes VOFF Offset Error VOFF_AD Input Offset Adjustment Range J -0.45 Extended Control Mode ±45 mV PFSE Positive Full-Scale Error (4) −0.6 ±25 mV (max) NFSE Negative Full-Scale Error (4) −1.31 ±25 mV (max) FS_ADJ Full-Scale Adjustment Range ±20 ±15 %FS (1) (2) (3) (4) Extended Control Mode The analog inputs are protected as shown in Figure 2. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level). Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 9 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.(1)(2) Parameter Typical (3) Test Conditions Limits (3) Units (Limits) NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth B.E.R. Bit Error Rate Gain Flatness ENOB SINAD SNR THD 2nd Harm Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR IMD Spurious-Free dynamic Range Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) Normal Mode (non DES) 1.7 GHz 10-18 Error/ Sample d.c. to 500 MHz ±0.5 dBFS d.c. to 1 GHz ±1.0 dBFS fIN = 100 MHz, VIN = FSR − 0.5 dB 7.5 fIN = 248 MHz, VIN = FSR − 0.5 dB 7.4 7.0 Bits (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 7.4 7.0 Bits (min) Bits fIN = 100 MHz, VIN = FSR − 0.5 dB 47 fIN = 248 MHz, VIN = FSR − 0.5 dB 46.3 43.9 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 46.3 43.9 dB (min) dB fIN = 100 MHz, VIN = FSR − 0.5 dB 48 fIN = 248 MHz, VIN = FSR − 0.5 dB 47.1 44.0 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 47.1 44.0 dB (min) fIN = 100 MHz, VIN = FSR − 0.5 dB -55 fIN = 248 MHz, VIN = FSR − 0.5 dB -55 -47.5 dB (max) fIN = 498 MHz, VIN = FSR − 0.5 dB -55 -47.5 dB (max) fIN = 100 MHz, VIN = FSR − 0.5 dB −60 dB fIN = 248 MHz, VIN = FSR − 0.5 dB −60 dB fIN = 498 MHz, VIN = FSR − 0.5 dB −60 dB fIN = 100 MHz, VIN = FSR − 0.5 dB −65 dB fIN = 248 MHz, VIN = FSR − 0.5 dB −65 dB fIN = 498 MHz, VIN = FSR − 0.5 dB −65 dB fIN = 100 MHz, VIN = FSR − 0.5 dB 55 dB fIN = 248 MHz, VIN = FSR − 0.5 dB 55 47.5 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 55 47.5 dB (min) fIN1 = 321 MHz, VIN = FSR − 7 dB fIN2 = 326 MHz, VIN = FSR − 7 dB -50 dB dB dB (VIN+) − (VIN−) > + Full Scale 255 (VIN+) − (VIN−) < − Full Scale 0 INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS FPBW (DES) Full Power Bandwidth ENOB Effective Number of Bits SINAD Signal to Noise Plus Distortion Ratio SNR Signal to Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 10 Dual Edge Sampling Mode 900 fIN = 248 MHz, VIN = FSR − 0.5 dB 7.3 6.8 Bits (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 7.3 6.8 Bits (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 46 42.5 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 46 42.5 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 46.4 43 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 46.4 43 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB -58 -49 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB -58 -49 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB -64 dB fIN = 498 MHz, VIN = FSR − 0.5 dB -64 dB Submit Documentation Feedback MHz Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Converter Electrical Characteristics (continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.(1)(2) Parameter Test Conditions 3rd Harm Third Harmonic Distortion SFDR Spurious Free Dynamic Range Typical (3) Limits (3) Units (Limits) fIN = 248 MHz, VIN = FSR − 0.5 dB -69 dB fIN = 498 MHz, VIN = FSR − 0.5 dB -69 dB fIN = 248 MHz, VIN = FSR − 0.5 dB 57 47 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 57 47 dB (min) 570 mVP-P (min) 730 mVP-P (max) 790 mVP-P (min) 950 mVP-P (max) VCMO − 50 VCMO + 50 mV (min) mV (max) ANALOG INPUT AND REFERENCE CHARACTERISTICS FSR pin 14 Low VIN 650 Full Scale Analog Differential Input Range FSR pin 14 High VCMI Analog Input Common Mode Voltage VCMO Analog Input Capacitance, Normal operation (5) (6) CIN Analog Input Capacitance, DES Mode (5) (6) RIN 870 Differential 0.02 pF Each input pin to ground 1.6 pF Differential 0.08 pF Each input pin to ground 2.2 pF Differential Input Resistance 100 94 Ω (min) 106 Ω (max) 0.95 1.45 V (min) V (max) ANALOG OUTPUT CHARACTERISTICS VCMO Common Mode Output Voltage VCMO_LVL VCMO input threshold to set DC Coupling mode ICMO = ±100 µA 1.26 VA = 1.8V 0.60 V VA = 2.0V 0.66 V TA = −40°C to +85°C 118 ppm/°C TC VCMO Common Mode Output Voltage Temperature Coefficient CLOAD VCMO Maximum VCMO load Capacitance VBG Bandgap Reference Output Voltage IBG = ±100 µA TC VBG Bandgap Reference Voltage Temperature Coefficient TA = −40°C to +85°C, IBG = ±100 µA CLOAD VBG Maximum Bandgap Reference load Capacitance 1.26 80 pF 1.20 1.33 V (min) V (max) 28 ppm/°C 80 pF TEMPERATURE DIODE CHARACTERISTICS ΔVBE Temperature Diode Voltage 192 µA vs. 12 µA, TJ = 25°C 71.23 mV 192 µA vs. 12 µA, TJ = 85°C 85.54 mV CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match (5) (6) 1 LSB Positive Full-Scale Match Zero offset selected in Control Register 1 LSB Negative Full-Scale Match Zero offset selected in Control Register 1 LSB The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. This parameter is ensured by design and is not tested in production. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 11 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.(1)(2) Parameter Typical (3) Test Conditions Limits (3) Units (Limits) Phase Matching (I, Q) FIN = 1.0 GHz (VIN-) 0.0V +VIN/2 Differential Analog Input Voltage (+VIN/2) - (-VIN/2) Figure 4. Input / Output Transfer Characteristic 11.3 TEST CIRCUIT DIAGRAMS 11.3.1 Timing Diagrams Sample N D Sample N-1 Dd VIN Sample N+1 tAD CLK, CLK tOD DId, DI DQd, DQ Sample N-18 and Sample N-17 Sample N-16 and Sample N-15 Sample N-14 and Sample N-13 tOSK DCLK+, DCLK(OutEdge = 0) DCLK+, DCLK(OutEdge = 1) Figure 5. ADC08D1000 Timing — SDR Clocking Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 17 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com TEST CIRCUIT DIAGRAMS (continued) Sample N D Sample N-1 Dd VIN Sample N+1 tAD CLK, CLK tOD DId, DI DQd, DQ Sample N-18 and Sample N-17 Sample N-16 and Sample N-15 Sample N-14 and Sample N-13 tOSK DCLK+, DCLK(0° Phase) tSU tH DCLK+, DCLK(90° Phase) Figure 6. ADC08D1000 Timing — DDR Clocking Single Register Access SCS 1 12 13 16 17 32 SCLK SDATA Fixed Header Pattern Register Write Data Register Address tSH MSB LSB tSSU Figure 7. Serial Interface Timing Synchronizing Edge CLK tRH tRS tSD DCLK_RST tRPW DCLK+ Figure 8. Clock Reset Timing in DDR Mode 18 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 TEST CIRCUIT DIAGRAMS (continued) Synchronizing Edge CLK tRH tRS tSD DCLK_RST tRPW DCLK+ OUTEDGE Figure 9. Clock Reset Timing in SDR Mode with OUTEDGE Low Synchronizing Edge CLK tRH tRS tSD DCLK_RST tRPW DCLK+ OUTEDGE Figure 10. Clock Reset Timing in SDR Mode with OUTEDGE High tCAL tCAL CalRun tCAL_H tCalDly CAL Calibration Delay determined by CalDly Pin (127) tCAL_L POWER SUPPLY Figure 11. Self Calibration and On-Command Calibration Timing Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 19 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 12 Typical Performance Characteristics VA=VDR=1.9V, FCLK=1000MHz, TA=25°C unless otherwise stated. 20 Figure 12. INL vs. CODE Figure 13. INL vs. TEMPERATURE Figure 14. DNL vs. CODE Figure 15. DNL vs. TEMPERATURE Figure 16. POWER DISSIPATION vs. SAMPLE RATE Figure 17. ENOB vs. CLOCK DUTY CYCLE Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Typical Performance Characteristics (continued) VA=VDR=1.9V, FCLK=1000MHz, TA=25°C unless otherwise stated. Figure 18. ENOB vs. TEMPERATURE Figure 19. ENOB vs. SUPPLY VOLTAGE Figure 20. ENOB vs. SAMPLE RATE Figure 21. ENOB vs. INPUT FREQUENCY Figure 22. SNR vs. TEMPERATURE Figure 23. SNR vs. SUPPLY VOLTAGE Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 21 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Typical Performance Characteristics (continued) VA=VDR=1.9V, FCLK=1000MHz, TA=25°C unless otherwise stated. 22 Figure 24. SNR vs. SAMPLE RATE Figure 25. SNR vs. INPUT FREQUENCY Figure 26. THD vs. TEMPERATURE Figure 27. THD vs. SUPPLY VOLTAGE Figure 28. THD vs. SAMPLE RATE Figure 29. THD vs. INPUT FREQUENCY Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Typical Performance Characteristics (continued) VA=VDR=1.9V, FCLK=1000MHz, TA=25°C unless otherwise stated. Figure 30. SFDR vs. TEMPERATURE Figure 31. SFDR vs. SUPPLY VOLTAGE Figure 32. SFDR vs. SAMPLE RATE Figure 33. SFDR vs. INPUT FREQUENCY Figure 34. Spectral Response at FIN = 248 MHz Figure 35. Spectral Response at FIN = 498 MHz Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 23 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Typical Performance Characteristics (continued) VA=VDR=1.9V, FCLK=1000MHz, TA=25°C unless otherwise stated. 24 Figure 36. CROSSTALK vs. SOURCE FREQUENCY Figure 37. FULL POWER BANDWIDTH Figure 38. STEP RESPONSE Figure 39. STEP RESPONSE DETAIL VIEW Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 13 Functional Description The ADC08D1000 is a versatile A/D Converter with an innovative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in APPLICATIONS INFORMATION. While it is generally poor practice to allow an active pin to float, pins 4, 14 and 127 of the ADC08D1000 are designed to be left floating without jeopardy. In all discussions throughout this data sheet, whenever a function is called by allowing a control pin to float, connecting that pin to a potential of one half the VA supply voltage will have the same effect as allowing it to float. 13.1 OVERVIEW The ADC08D1000 uses a calibrated folding and interpolating architecture that achieves 7.5 effective bits. The use of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. In addition to other things, on-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely fast, high performance, low power converter. The analog input signal that is within the converter's input voltage range is digitized to eight bits at speeds of 200 MSPS to 1.3 GSPS, typical. Differential input voltages below negative full-scale will cause the output word to consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of all ones. Either of these conditions at either the "I" or "Q" input will cause the OR (Out of Range) output to be activated. This single OR output indicates when the output code from one or both of the channels is below negative full scale or above positive full scale. Each of the two converters has a 1:2 demultiplexer that feeds two LVDS output buses. The data on these buses provide an output word rate on each bus at half the ADC sampling rate and must be interleaved by the user to provide output words at the full conversion rate. The output levels may be selected to be normal or reduced. Using reduced levels saves power but could result in erroneous data capture of some or all of the bits, especially at higher sample rates and in marginally designed systems. 13.1.1 Self-Calibration A self-calibration is performed upon power-up and can also be invoked by the user upon command. Calibration trims the 100Ω analog input differential termination resistor and minimizes full-scale error, offset error, DNL and INL, resulting in maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal bias currents are also set with the calibration process. All of this is true whether the calibration is performed upon power up or is performed upon command. Running the self calibration is an important part of this chip's functionality and is required in order to obtain adequate performance. In addition to the requirement to be run at power-up, self calibration must be rerun whenever the sense of the FSR pin is changed. For best performance, we recommend that self calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, according to the system design performance specifications. See On-Command Calibration for more information. Calibration can not be initiated or run while the device is in the power-down mode. See Power Down for information on the interaction between Power Down and Calibration. During the calibration process, the input termination resistor is trimmed to a value that is equal to REXT / 33. This external resistor is located between pin 32 and ground. REXT must be 3300 Ω ±0.1%. With this value, the input termination resistor is trimmed to be 100 Ω. Because REXT is also used to set the proper current for the Track and Hold amplifier, for the preamplifiers and for the comparators, other values of REXT should not be used. In normal operation, calibration is performed just after application of power and whenever a valid calibration command is given, which is holding the CAL pin low for at least tCAL_L clock cycles, then hold it high for at least another tCAL_H clock cycles as defined in the Converter Electrical Characteristics. The time taken by the calibration procedure is specified as tCALin Converter Electrical Characteristics. Holding the CAL pin high upon power up will prevent the calibration process from running until the CAL pin experiences the above-mentioned tCAL_L clock cycles followed by tCAL_H clock cycles. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 25 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com OVERVIEW (continued) CalDly (pin 127) is used to select one of two delay times after the application of power to the start of calibration. This calibration delay time is depedent on the setting of the CalDly pin and is specified as tCalDly in the Converter Electrical Characteristics. These delay values allow the power supply to come up and stabilize before calibration takes place. If the PD pin is high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the power supply. Calibration Operation Notes: • During the calibration cycle, the OR output may be active as a result of the calibration algorithm. All data on the output pins and the OR output are invalid during the calibration cycle. • During the power-up calibration and during the on-command calibration, all clocks are halted on chip, including internal clocks and DCLK, while the input termination resistor is trimmed to a value that is equal to REXT / 33. This is to reduce noise during the input resistor calibration portion of the calibration cycle. See Self Calibration for information on maintaining DCLK operation during on-command calibration. – This external resistor is located between pin 32 and ground. REXT must be 3300 Ω ±0.1%. With this value, the input termination resistor is trimmed to be 100 Ω. Because REXT is also used to set the proper current for the Track and Hold amplifier, for the preamplifiers and for the comparators, other values of REXT should not be used. • The CalRun output is high whenever the calibration procedure is running. This is true whether the calibration is done at power-up or on-command. 13.1.2 Acquiring the Input Data is acquired at the falling edge of CLK+ (pin 18) and the digital equivalent of that data is available at the digital outputs 13 input clock cycles later for the DI and DQ output buses and 14 input clock cycles later for the DId and DQd output buses. There is an additional internal delay called tOD before the data is available at the outputs. See the Timing Diagrams. The ADC08D1000 will convert as long as the input clock signal is present. The fully differential comparator design and the innovative design of the sample-and-hold amplifier, together with self calibration, enables a very flat SINAD/ENOB response beyond 1.0 GHz. The ADC08D1000 output data signaling is LVDS and the output format is offset binary. 13.1.3 Control Modes Much of the user control can be accomplished with several control pins that are provided. Examples include initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08D1000 also provides an Extended Control mode whereby a serial interface is used to access register-based control of several advanced features. The Extended Control mode is not intended to be enabled and disabled dynamically. Rather, the user is expected to employ either the normal control mode or the Extended Control mode at all times. When the device is in the Extended Control mode, pin-based control of several features is replaced with registerbased control and those pin-based controls are disabled. These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin 14) and CalDly/DES (pin 127). See NORMAL/EXTENDED CONTROL for details on the Extended Control mode. 13.1.4 The Analog Inputs The ADC08D1000 must be driven with a differential input signal. Operation with a single-ended signal is not recommended. It is important that the inputs either be a.c. coupled to the inputs with the VCMO pin grounded, or d.c. coupled with the VCMO pin left floating. An input common mode voltage equal to the VCMO output must be provided when d.c. coupling is used. Two full-scale range settings are provided with pin 14 (FSR). The input full-scale range is programmable in the normal mode by setting a level on pin 14 (FSR) as defined in by the specification VIN in the Converter Electrical Characteristics. The full-scale range setting operates equally on both ADCs. In the Extended Control mode, programming the Input Full-Scale Voltage Adjust register allows the input fullscale range to be adjusted as described in ??1.4 and ??2.2. 26 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 OVERVIEW (continued) 13.1.5 Clocking The ADC08D1000 must be driven with an a.c. coupled, differential clock signal. THE CLOCK INPUTS section describes the use of the clock input pins. A differential LVDS output clock is available for use in latching the ADC output data into whatever device is used to receive the data. The ADC08D1000 offers two options for input and output clocking. These options include a choice of Dual Edge Sampling (DES) or "interleaved mode" where the ADC08D1000 performs as a single device converting at twice the input clock rate, a choice of which DCLK edge the output data transitions on, and a choice of Single Data Rate (SDR) or Double Data Rate (DDR) outputs. The ADC08D1000 also has the option to use a duty cycle corrected clock receiver as part of the input clock circuit. This feature is enabled by default and provides improved ADC clocking especially in the Dual-Edge Sampling mode (DES). This circuitry allows the ADC to be clocked with a signal source having a duty cycle ratio of 80 / 20 % (worst case) for both the normal and the Dual Edge Sampling modes. 13.1.5.1 Dual-Edge Sampling The DES mode allows one of the ADC08D1000's inputs (I or Q Channel) to be sampled by both ADCs. One ADC samples the input on the positive edge of the input clock and the other ADC samples the same input on the other edge of the input clock. A single input is thus sampled twice per input clock cycle, resulting in an overall sample rate of twice the input clock frequency, or 2 GSPS with a 1 GHz input clock. In this mode the outputs are interleaved such that the data is effectively demultiplexed 1:4. Since the sample rate is doubled, each of the 4 output buses have a 500 MSPS output rate with a 1 GHz input clock. All data is available in parallel. The four bytes of parallel data that are output with each clock is in the following sampling order, from the earliest to the latest: DQd, DId, DQ, DI. Table 1 indicates what the outputs represent for the various sampling possibilities. In the non-extended mode of operation only the "I" input can be sampled in the DES mode. In the extended mode of operation the user can select which input is sampled. The ADC08D1000 also includes an automatic clock phase background calibration feature which can be used in DES mode to automatically and continuously adjust the clock phase of the I and Q channel. This feature removes the need to adjust the clock phase setting manually and provides optimal Dual-Edge Sampling ENOB performance. IMPORTANT NOTE: The background calibration feature in DES mode does not replace the requirement for OnCommand Calibration which should be run before entering DES mode, or if a large swing in ambient temperature is experienced by the device. Table 1. Input Channel Samples Produced at Data Outputs Data Outputs (Always sourced with respect to fall of DCLK) (1) Normal Sampling Mode Dual-Edge Sampling Mode (DES) Q-Channel Selected (1) I-Channel Selected DI "I" Input Sampled with Fall of CLK 13 cycles earlier. "I" Input Sampled with Fall of CLK 13 cycles earlier. "Q" Input Sampled with Fall of CLK 13 cycles earlier. DId "I" Input Sampled with Fall of CLK 14 cycles earlier. "I" Input Sampled with Fall of CLK 14 cycles earlier. "Q" Input Sampled with Fall of CLK 14 cycles earlier. DQ "Q" Input Sampled with Fall of CLK 13 cycles earlier. "I" Input Sampled with Rise of CLK 13.5 cycles earlier. "Q" Input Sampled with Rise of CLK 13.5 cycles earlier. DQd "Q" Input Sampled with Fall of CLK 14 cycles after being sampled. "I" Input Sampled with Rise of CLK 14.5 cycles earlier. "Q" Input Sampled with Rise of CLK 14.5 cycles earlier. Note: In DES + normal mode, only the I Channel is sampled. In DES + extended control mode, I or Q channel can be sampled. 13.1.5.2 OutEdge Setting To help ease data capture in the SDR mode, the output data may be caused to transition on either the positive or the negative edge of the output data clock (DCLK). This is chosen with the OutEdge input (pin 4). A high on the OutEdge input pin causes the output data to transition on the rising edge of DCLK, while grounding this input causes the output to transition on the falling edge of DCLK. See Output Edge Synchronization. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 27 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 13.1.5.3 Double Data Rate A choice of single data rate (SDR) or double data rate (DDR) output is offered. With single data rate the output clock (DCLK) frequency is the same as the data rate of the two output buses. With double data rate the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK. DDR clocking is enabled in non-Extended Control mode by allowing pin 4 to float. 13.1.6 The LVDS Outputs The data outputs, the Out Of Range (OR) and DCLK, are LVDS. Output current sources provide 3 mA of output current to a differential 100 Ohm load when the OutV input (pin 14) is high or 2.2 mA when the OutV input is low. For short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low, which results in lower power consumption. If the LVDS lines are long and/or the system in which the ADC08D1000 is used is noisy, it may be necessary to tie the OutV pin high. The LVDS data output have a typical common mode voltage of 800mV when the VBG pin is unconnected and floating. This common mode voltage can be increased to 1.2V by tying the VBG pin to VA if a higher common mode is required. IMPORTANT NOTE: Tying the VBG pin to VA will also increase the differential LVDS output voltage by up to 40mV. 13.1.7 Power Down The ADC08D1000 is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in the power down mode. In this power down mode the data output pins (positive and negative) are put into a high impedance state and the devices power consumption is reduced to a minimal level. The DCLK+/- and OR +/- are not tri-stated, they are weakly pulled down to ground internally. Therefore when both I and Q are powered down the DCLK +/- and OR +/- should not be terminated to a DC voltage. A high on the PDQ pin will power down the "Q" channel and leave the "I" channel active. There is no provision to power down the "I" channel independently of the "Q" channel. Upon return to normal operation, the pipeline will contain meaningless information. If the PD input is brought high while a calibration is running, the device will not go into power down until the calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in the power down state. Calibration will function with the "Q" channel powered down, but that channel will not be calibrated if PDQ is high. If the "Q" channel is subsequently to be used, it is necessary to perform a calibration after PDQ is brought low. 13.2 NORMAL/EXTENDED CONTROL The ADC08D1000 may be operated in one of two modes. In the simpler standard control mode, the user affects available configuration and control of the device through several control pins. The "extended control mode" provides additional configuration and control options through a serial interface and a set of 9 registers. The two control modes are selected with pin 14 (FSR/ECE: Extended Control Enable). The choice of control modes is required to be a fixed selection and is not intended to be switched dynamically while the device is operational. 28 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 NORMAL/EXTENDED CONTROL (continued) Table 2 shows how several of the device features are affected by the control mode chosen. Table 2. Features and modes Feature Normal Control Mode Extended Control Mode SDR or DDR Clocking Selected with nDE in the Configuration Register DDR Clocking selected with pin 4 floating. SDR (1h; bit-10). When the device is in DDR mode, clocking selected when pin 4 not floating. address 1h, bit-8 must be set to 0b. DDR Clock Phase Not Selectable (0° Phase Only) Selected with DCP bit in the Configuration Register (1h; bit-11). SDR Data transitions with rising or falling DCLK edge SDR Data transitions with rising edge of DCLK+ when pin 4 is high and on falling edge when low. Selected with OE in the Configuration Register (1h; bit-8). LVDS output level Normal differential data and DCLK amplitude selected when pin 3 is high and reduced amplitude selected when low. Selected with the OV in the Configuration Register (1h; bit-9). Power-On Calibration Delay Short delay selected when pin 127 is low and longer delay selected when high Short delay only. Full-Scale Range Up to 512 step adjustments over a nominal Options (650 mVP-P or 870 mVP-P) selected with range specified in ??1.4. Selected using the pin 14. Selected range applies to both Input Full-Scale Adjust register (3h; bits-7 thru channels. 15). Input Offset Adjust Not possible 512 steps of adjustment using the Input Offset register (2h; bits-7 thru 15) as specified in ??1.4 Dual Edge Sampling Selection Enabled with pin 127 Enabled through DES Enable Register. Dual Edge Sampling Input Channel Selection Only I-Channel Input can be used Either I- or Q-Channel input may be sampled by both ADCs. The Clock Phase is adjusted automatically Automatic Clock Phase control can be selected by setting bit 14 in the DES Enable register (Dh). The clock phase can also be adjusted manually through the Coarse & Fine registers (Eh and Fh). DES Sampling Clock Adjustment The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device) and is shown in Table 3. Table 3. Extended Control Mode Operation (Pin 14 Floating) Feature Extended Control Mode Default State SDR or DDR Clocking DDR Clocking DDR Clock Phase Data changes with DCLK edge (0° phase) LVDS Output Amplitude Normal amplitude (710 mVP-P) Calibration Delay Short Delay Full-Scale Range 700 mV nominal for both channels Input Offset Adjust No adjustment for either channel Dual Edge Sampling (DES) Not enabled Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 29 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 13.3 THE SERIAL INTERFACE IMPORTANT NOTE: During the initial write using the serial interface, all 8 user registers must be written with desired or default values. In addition, the first write to the DES Enable register (Dh) must load the default value (0x3FFFh). Once all registers have been written once, other desired settings, including enabling DES can be loaded. The 3-pin serial interface is enabled only when the device is in the Extended Control mode. The pins of this interface are Serial Clock (SCLK), Serial Data (SDATA) and Serial Interface Chip Select (SCS) Eight write only registers are accessible through this serial interface. SCS: This signal should be asserted low while accessing a register through the serial interface. Setup and hold times with respect to the SCLK must be observed. SCLK: Serial data input is accepted with the rising edge of this signal. There is no minimum frequency requirement for SCLK. SDATA: Each register access requires a specific 32-bit pattern at this input. This pattern consists of a header, register address and register value. The data is shifted in MSB first. Setup and hold times with respect to the SCLK must be observed. See the Timing Diagrams. Each Register access consists of 32 bits, as shown in Figure 7 of the Timing Diagrams. The fixed header pattern is 0000 0000 0001 (eleven zeros followed by a 1). The loading sequence is such that a "0" is loaded first. These 12 bits form the header. The next 4 bits are the address of the register that is to be written to and the last 16 bits are the data written to the addressed register. The addresses of the various registers are indicated in Table 4. Refer to the REGISTER DESCRIPTION for information on the data to be written to the registers. Subsequent register accesses may be performed immediately, starting with the 33rd SCLK. This means that the SCS input does not have to be de-asserted and asserted again between register addresses. It is possible, although not recommended, to keep the SCS input permanently enabled (at a logic low) when using extended control. IMPORTANT NOTE: The Serial Interface should not be used when calibrating the ADC. Doing so will impair the performance of the device until it is re-calibrated correctly. Programming the serial registers will also reduce dynamic performance of the ADC for the duration of the register access time. Table 4. Register Addresses 4-Bit Address Loading Sequence: A3 loaded after Fixed Header Pattern, A0 loaded last 30 A3 A2 A1 A0 Hex 0 0 0 0 0h Reserved 0 0 0 1 1h Configuration 0 0 1 0 2h "I" Ch Offset 0 0 1 1 3h "I" Ch Full-Scale Voltage Adjust 0 1 0 0 4h Reserved 0 1 0 1 5h Reserved 0 1 1 0 6h Reserved 0 1 1 1 7h Reserved 1 0 0 0 8h Reserved 1 0 0 1 9h Reserved 1 0 1 0 Ah "Q" Ch Offset 1 0 1 1 Bh "Q" Ch Full-Scale Voltage Adjust 1 1 0 0 Ch Reserved 1 1 0 1 Dh DES Enable 1 1 1 0 Eh DES Coarse Adjust 1 1 1 1 Fh DES Fine Adjust Submit Documentation Feedback Register Addressed Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 13.4 REGISTER DESCRIPTION Eight write-only registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Normal Control Mode. Each register description below also shows the Power-On Reset (POR) state of each control bit. Table 5. Configuration Register Addr: 1h (0001b) W only (0xB2FF) D15 D14 D13 D12 D11 D10 D9 D8 1 0 1 DCS DCP nDE OV OE D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 IMPORTANT: The Configuration Register should not be written if the DES Enable bit = 1. The DES Enable bit should first be changed to 0, then the Configuration Register can be written. Failure to follow this procedure can cause the internal DES clock generation circuitry to stop. Bit 15 Must be set to 1b Bit 14 Must be set to 0b Bit 13 Must be set to 1b Bit 12 DCS: Duty Cycle Stabilizer. When this bit is set to 1b , a duty cycle stabilization circuit is applied to the clock input. When this bit is set to 0b the stabilization circuit is disabled. POR State: 1b Bit 11 DCP: DDR Clock Phase. This bit only has an effect in the DDR mode. When this bit is set to 0b, the DCLK edges are time-aligned with the data bus edges ("0° Phase"). When this bit is set to 1b, the DCLK edges are placed in the middle of the data bit-cells ("90° Phase"), using the one-half speed DCLK shown in Figure 6 as the phase reference. POR State: 0b Bit 10 nDE: DDR Enable. When this bit is set to 0b, data bus clocking follows the DDR (Dual Data Rate) mode whereby a data word is output with each rising and falling edge of DCLK. When this bit is set to a 1b, data bus clocking follows the SDR (single data rate) mode whereby each data word is output with either the rising or falling edge of DCLK , as determined by the OutEdge bit. POR State: 0b Bit 9 OV: Output Voltage. This bit determines the LVDS outputs' voltage amplitude and has the same function as the OutV pin that is used in the normal control mode. When this bit is set to 1b, the standard output amplitude of 710 mVP-P is used. When this bit is set to 0b, the reduced output amplitude of 510 mVP-P is used. POR State: 1b Bit 8 OE: Output Edge. This bit selects the DCLK edge with which the data words transition in the SDR mode and has the same effect as the OutEdge pin in the normal control mode. When this bit is 1, the data outputs change with the rising edge of DCLK+. When this bit is 0, the data output change with the falling edge of DCLK+. POR State: 0b Bits 7:0 Must be set to 1b. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 31 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Table 6. I-Channel Offset Addr: 2h (0010b) D15 W only (0x007F) D14 D13 D12 (MSB) D11 D10 D9 Offset Value D8 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 Sign 1 1 1 1 1 1 1 Bits 15:8 Offset Value. The input offset of the I-Channel ADC is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero offset, while FFh provides a nominal 45 mV of offset. Thus, each code step provides 0.176 mV of offset. POR State: 0000 0000 b Bit 7 Sign bit. 0b gives positive offset, 1b gives negative offset. POR State: 0b Bit 6:0 Must be set to 1b Table 7. I-Channel Full-Scale Voltage Adjust Addr: 3h (0011b) D15 W only (0x807F) D14 D13 D12 (MSB) D11 D10 D9 D8 Adjust Value D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 1 1 1 1 1 1 1 Bit 15:7 Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I-Channel ADC is adjusted linearly and monotonically with a 9 bit data value. The adjustment range is ±20% of the nominal 700 mVP-P differential value. 0000 0000 0 560mVP-P 1000 0000 0 Default Value 700mVP-P 1111 1111 1 840mVP-P For best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to 1110 0000 0b. i.e., limit the amount of adjustment to ±15%. The remaining ±5% headroom allows for the ADC's own full scale variation. A gain adjustment does not require ADC re-calibration. POR State: 1000 0000 0b (no adjustment) Bits 6:0 Must be set to 1b Table 8. Q-Channel Offset Addr: Ah (1010b) D15 W only (0x007F) D14 D13 D12 (MSB) 32 D11 D10 D9 Offset Value D8 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 Sign 1 1 1 1 1 1 1 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Bit 15:8 Offset Value. The input offset of the Q-Channel ADC is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero offset, while FFh provides a nominal 45 mV of offset. Thus, each code step provides about 0.176 mV of offset. POR State: 0000 0000 b Bit 7 Sign bit. 0b gives positive offset, 1b gives negative offset. POR State: 0b Bit 6:0 Must be set to 1b Table 9. Q-Channel Full-Scale Voltage Adjust Addr: Bh (1011b) D15 W only (0x807F) D14 D13 D12 (MSB) D11 D10 D9 D8 Adjust Value D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 1 1 1 1 1 1 1 Bit 15:7 Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I-Channel ADC is adjusted linearly and monotonically with a 9 bit data value. The adjustment range is ±20% of the nominal 700 mVP-P differential value. 0000 0000 0 560mVP-P 1000 0000 0 700mVP-P 1111 1111 1 840mVP-P For best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to 1110 0000 0b. i.e., limit the amount of adjustment to ±15%. The remaining ±5% headroom allows for the ADC's own full scale variation. A gain adjustment does not require ADC re-calibration. POR State: 1000 0000 0b (no adjustment) Bits 6:0 Must be set to 1b Table 10. DES Enable Addr: Dh (1101b) W only (0x3FFF) D15 D14 D13 D12 D11 D10 D9 D8 DEN ACP 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 Bit 15 DES Enable. Setting this bit to 1b enables the Dual Edge Sampling mode. In this mode the ADCs in this device are used to sample and convert the same analog input in a time-interleaved manner, accomplishing a sampling rate of twice the input clock rate. When this bit is set to 0b, the device operates in the normal dual channel mode. POR State: 0b Bit 14 Automatic Clock Phase Control. (ACP) Setting this bit to 1b enables the Automatic Clock Phase Control. In this mode the DES Coarse and Fine manual controls are disabled. A phase detection circuit continually adjusts the I and Q sampling edges to be 180 degrees out of phase. When this bit is set to 0b, the sample (input) clock delay between the I and Q channels is set manually using the DES Coarse and Fine Adjust registers. (See Dual Edge Sampling for important application information) Using the ACP Control option is recommended over the manual DES settings. POR State: 0b Bits 13:0 Must be set to 1b Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 33 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com Table 11. DES Coarse Adjust Addr: Eh (1110b) W only (0x07FF) D15 D14 IS ADS D7 D6 D5 D4 1 1 1 1 Bit 15 D13 D12 D11 D10 D9 D8 1 1 1 D3 D2 D1 D0 1 1 1 1 CAM Input Select. When this bit is set to 0b the "I" input is operated upon by both ADCs. When this bit is set to 1b the "Q" input is operated on by both ADCs. POR State: 0b Bit 14 Adjust Direction Select. When this bit is set to 0b, the programmed delays are applied to the "I" channel sample clock while the "Q" channel sample clock remains fixed. When this bit is set to 1b, the programmed delays are applied to the "Q" channel sample clock while the "I" channel sample clock remains fixed. POR State: 0b Bits 13:11 Coarse Adjust Magnitude. Each code value in this field delays either the "I" channel or the "Q" channel sample clock (as determined by the ADS bit) by approximately 20 picoseconds. A value of 000b in this field causes zero adjustment. POR State: 000b Bits 10:0 Must be set to 1b Table 12. DES Fine Adjust Addr: Fh (1111b) D15 W only (0x007F) D14 D13 D12 (MSB) D11 D10 D9 D8 FAM D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 1 1 1 1 1 1 1 Bits 15:7 Fine Adjust Magnitude. Each code value in this field delays either the "I" channel or the "Q" channel sample clock (as determined by the ADS bit of the DES Coarse Adjust Register) by approximately 0.1 ps. A value of 0000 0000 0b in this field causes zero adjustment. Note that the amount of adjustment achieved with each code will vary with the device conditions as well as with the Coarse Adjustment value chosen. POR State: 0000 0000 0b Bit 6:0 34 Must be set to 1b Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 13.4.1 Note Regarding Extended Mode Offset Correction When using the I or Q channel Offset Adjust registers, the following information should be noted. For offset values of +0000 0000 and -0000 0000, the actual offset is not the same. By changing only the sign bit in this case, an offset step in the digital output code of about 1/10th of an LSB is experienced. This is shown more clearly in the Figure below. Figure 40. Extended Mode Offset Behavior 13.5 MULTIPLE ADC SYNCHRONIZATION The ADC08D1000 has the capability to precisely reset its sampling clock input to DCLK output relationship as determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time with respect to the shared CLK input that all the ADCs use for sampling. The DCLK_RST signal must observe some timing requirements that are shown in Figure 8, Figure 9 and Figure 10 of the Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its desertion edge must observe setup and hold times with respect to the CLK input rising edge. These times are specified in the AC Converter Electrical Characteristics. The DCLK_RST signal can be asserted asynchronous to the input clock. If DCLK_RST is asserted, the DCLK output is held in a designated state. The state in which DCLK is held during the reset period is determined by the mode of operation (SDR/DDR) and the setting of the Output Edge configuration pin or bit. (Refer to Figure 8, Figure 9 and Figure 10 for the DCLK reset state conditions). Therefore, depending upon when the DCLK_RST signal is asserted, there may be a narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal is de-asserted in synchronization with the CLK rising edge, the next CLK falling edge synchronizes the DCLK output with those of other ADC08D1000s in the system. The DCLK output is enabled again after a constant delay (relative to the input clock frequency) which is equal to the CLK input to DCLK output delay (tSD). The device always exhibits this delay characteristic in normal operation. The DCLK-RST pin should NOT be brought high while the calibration process is running (while CalRun is high). Doing so could cause a digital glitch in the digital circuitry, resulting in corruption and invalidation of the calibration. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 35 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 14 APPLICATIONS INFORMATION 14.1 THE REFERENCE VOLTAGE The voltage reference for the ADC08D1000 is derived from a 1.254V bandgap reference, a buffered version of which is made available at pin 31, VBG, for user convenience. This output has an output current capability of ±100 μA and should be buffered if more current than this is required. The internal bandgap-derived reference voltage has a nominal value VIN, as determined by the FSR pin and described in The Analog Inputs. There is no provision for the use of an external reference voltage, but the full-scale input voltage can be adjusted through a Configuration Register in the Extended Control mode, as explained in NORMAL/EXTENDED CONTROL. Differential input signals up to the chosen full-scale level will be digitized to 8 bits. Signal excursions beyond the full-scale range will be clipped at the output. These large signal excursions will also activate the OR output for the time that the signal is out of range. See Out Of Range (OR) Indication. One extra feature of the VBG pin is that it can be used to raise the common mode voltage level of the LVDS outputs. The output offset voltage (VOS) is typically 800mV when the VBG pin is used as an output or left unconnected. To raise the LVDS offset voltage to a typical value of 1200mV the VBG pin can be connected directly to the supply rails. 14.2 THE ANALOG INPUT The analog input is a differential one to which the signal source may be a.c. coupled or d.c. coupled. In the normal mode, the full-scale input range is selected using the FSR pin as specified in the Converter Electrical Characteristics. In the Extended Control mode, the full-scale input range is selected by programming the FullScale Voltage Adjust register through the Serial Interface. For best performance when adjusting the input fullscale range in the Extended Control, refer to ??1.4. for guidelines on limiting the amount of adjustment. Table 13 gives the input to output relationship with the FSR pin high and the normal (non-extended) mode is used. With the FSR pin grounded, the millivolt values in Table 13 are reduced to 75% of the values indicated. In the Enhanced Control Mode, these values will be determined by the full scale range and offset settings in the Control Registers. Table 13. DIFFERENTIAL INPUT TO OUTPUT RELATIONSHIP (Non-Extended Control Mode, FSR High) VIN+ VIN− Output Code VCM − 217.5mV VCM + 217.5mV 0000 0000 VCM − 109 mV VCM + 109 mV 0100 0000 VCM 0111 1111 / 1000 0000 VCM + 109 mV VCM −109 mV 1100 30000 VCM + 217.5mV VCM − 217.5mV 1111 1111 VCM The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at sampling ADC inputs is not required. If it is desired to use an amplifier circuit before the ADC, use care in choosing an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used for the application. Note that a precise d.c. common mode voltage must be present at the ADC inputs. This common mode voltage, VCMO, is provided on-chip when a.c. input coupling is used and the input signal is a.c. coupled to the ADC. When the inputs are a.c. coupled, the VCMO output must be grounded, as shown in Figure 41. This causes the on-chip VCMO voltage to be connected to the inputs through on-chip 50k-Ohm resistors. IMPORTANT NOTE: An Analog input channel that is not used (e.g. in DES Mode) should be left floating when the inputs are a.c. coupled. Do not connect an unused analog input to ground. 36 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 Ccouple VIN+ Ccouple VINVCMO ADC081000 Figure 41. Differential Input Drive When the d.c. coupled mode is used, a common mode voltage must be provided at the differential inputs. This common mode voltage should track the VCMO output pin. Note that the VCMO output potential will change with temperature. The common mode output of the driving device should track this change. IMPORTANT NOTE: An analog input channel that is not used (e.g. in DES Mode) should be tied to the VCMO voltage when the inputs are d.c. coupled. Do not connect unused analog inputs to ground. Full-scale distortion performance falls off rapidly as the input common mode voltage deviates from V CMO. This is a direct result of using a very low supply voltage to minimize power. Keep the input common voltage within 50 mV of VCMO. Performance is as good in the d.c. coupled mode as it is in the a.c. coupled mode, provided the input common mode voltage at both analog inputs remain within 50 mV of VCMO. If d.c. coupling is used, it is best to servo the input common mode voltage, using the VCMO pin, to maintain optimum performance. An example of this type of circuit is shown in Figure 42. 3.3V RF1 RT2 50: RG1 100: + 50: RT1 50: RG2 VIN- 50: 50: VIN+ RF2 VCM_REF ADC081000 RADJ- RADJ+ Signal Input LMH6555 VCMO + LMV321 Figure 42. Example of Servoing the Analog Input with VCMO One such circuit should be used in front of the VIN+ input and another in front of the VIN− input. In that figure, RD1, RD2 and RD3 are used to divide the VCMO potential so that, after being gained up by the amplifier, the input common mode voltage is equal to VCMO from the ADC. RD1 and RD2 are split to allow the bypass capacitor to isolate the input signal from VCMO. RIN, RD2 and RD3 will divide the input signal, if necessary. Capacitor "C" in Figure 42 should be chosen to keep any component of the input signal from affecting VCMO. Be sure that the current drawn from the VCMO output does not exceed 100 μA. The Input impedance in the d.c. coupled mode (VCMO pin not grounded) consists of a precision 100Ω resistor between VIN+ and VIN− and a capacitance from each of these inputs to ground. In the a.c. coupled mode the input appears the same except there is also a resistor of 50K between each analog input pin and the VCMO potential. Driving the inputs beyond full scale will result in a saturation or clipping of the reconstructed output. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 37 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 14.2.1 Handling Single-Ended Input Signals There is no provision for the ADC08D1000 to adequately process single-ended input signals. The best way to handle single-ended signals is to convert them to differential signals before presenting them to the ADC. The easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun-connected transformer, as shown in Figure 43. 14.2.1.1 a.c. Coupled Input The easiest way to accomplish single-ended a.c. Input to differential a.c. signal is with an appropriate balunconnected transformer, as shown in ?? F13. Ccouple 50: Source VIN+ 100: 1:2 Balun Ccouple VINADC08D1000 Figure 43. Single-Ended to Differential Signal Conversion Using a Balun The 100 Ohm external resistor placed across the output terminals of the balun in parallel with the ADC08D1000's on-chip 100 Ohm resistor makes a 50 Ohms differential impedance at the balun output. Or, 25 Ohms to virtual ground at each of the balun output terminals. Looking into the balun, the source sees the impedance of the first coil in series with the impedance at the output of that coil. Since the transformer has a 1:1 turns ratio, the impedance across the first coil is exactly the same as that at the output of the second coil, namely 25 Ohms to virtual ground. So, the 25 Ohms across the first coil in series with the 25 Ohms at its output gives 50 Ohms total impedance to match the source. 14.2.2 Out Of Range (OR) Indication When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and ORgoes low. This output is active as long as accurate data on either or both of the buses would be outside the range of 00h to FFh. 14.2.3 Full-Scale Input Range As with all A/D Converters, the input range is determined by the value of the ADC's reference voltage. The reference voltage of the ADC08D1000 is derived from an internal band-gap reference. The FSR pin controls the effective reference voltage of the ADC08D1500 such that the differential full-scale input range at the analog inputs is a normal amplitude with the FSR pin high, or a reduced amplitude with FSR pin low as defined by the specification VIN in the Converter Electrical Characteristics. Best SNR is obtained with FSR high, but better distortion and SFDR are obtained with the FSR pin low. The LMH6555 of Figure 42 is suitable for any Full Scale Range. 14.3 THE CLOCK INPUTS The ADC08D1000 has differential LVDS clock inputs, CLK+ and CLK-, which must be driven with an a.c. coupled, differential clock signal. Although the ADC08D1000 is tested and its performance is specified with a differential 1.0 GHz clock, it typically will function well with input clock frequencies indicated in the Converter Electrical Characteristics. The clock inputs are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as indicated in Figure 44. Operation up to the sample rates indicated in the Converter Electrical Characteristics is typically possible if the maximum ambient temperatures indicated are not exceeded. Operating at higher sample rates than indicated for the given ambient temperature may result in reduced device reliability and product lifetime. This is because of the higher power consumption and die temperatures at high sample rates. Important also for reliability is proper thermal management . See Thermal Management. 38 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 THE CLOCK INPUTS (continued) Ccouple CLK+ Ccouple CLK- ADC081000 Figure 44. Differential (LVDS) Input Clock Connection The differential input clock line pair should have a characteristic impedance of 100Ω and (when using a balun), be terminated at the clock source in that (100Ω) characteristic impedance. The input clock line should be as short and as direct as possible. The ADC08D1000 clock input is internally terminated with an untrimmed 100Ω resistor. Insufficient input clock levels will result in poor dynamic performance. Excessively high input clock levels could cause a change in the analog input offset voltage. To avoid these problems, keep the input clock level within the range specified in the Converter Electrical Characteristics. The low and high times of the input clock signal can affect the performance of any A/D Converter. The ADC08D1000 features a duty cycle clock correction circuit which can maintain performance over temperature even in DES mode. The ADC will meet its performance specification if the input clock high and low times are maintained within the range (20/80% ratio) as specified in the Converter Electrical Characteristics. High speed, high performance ADCs such as the ADC08D1000 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale range. The maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be tJ(MAX) = (VINFSR / VIN(P-P)) x (1/(2(N+1) x π x fIN)) (3) where tJ(MAX) is the rms total of all jitter sources in seconds, VIN(P-P) is the peak-to-peak analog input signal, VINFSR is the full-scale range of the ADC, "N" is the ADC resolution in bits and fIN is the maximum input frequency, in Hertz, to the ADC analog input. Note that the maximum jitter described above is the arithmetic sum of the jitter from all sources, including that in the ADC input clock, that added by the system to the ADC input clock and input signals and that added by the ADC itself. Since the effective jitter added by the ADC is beyond user control, the best the user can do is to keep the sum of the externally added input clock jitter and the jitter added by the analog circuitry to the analog signal to a minimum. Input clock amplitudes above those specified in the Converter Electrical Characteristics may result in increased input offset voltage. This would cause the converter to produce an output code other than the expected 127/128 when both input pins are at the same potential. 14.4 CONTROL PINS Six control pins (without the use of the serial interface) provide a wide range of possibilities in the operation of the ADC08D1000 and facilitate its use. These control pins provide Full-Scale Input Range setting, Self Calibration, Calibration Delay, Output Edge Synchronization choice, LVDS Output Level choice and a Power Down feature. 14.4.1 Full-Scale Input Range Setting The input full-scale range can be selected with the FSR control input (pin 14) in the normal mode of operation. The is specified as VIN in the Converter Electrical Characteristics. In the extended control mode, the input fullscale range may be programmed using the Full-Scale Adjust Voltage register. See THE ANALOG INPUT for more information. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 39 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com CONTROL PINS (continued) 14.4.2 Self Calibration The ADC08D1000 self-calibration must be run to achieve specified performance. The calibration procedure is run upon power-up and can be run any time on command. The calibration procedure is exactly the same whether there is an input clock present upon power up or if the clock begins some time after application of power. The CalRun output indicator is high while a calibration is in progress. Note that DCLK outputs are not active during a calibration cycle, therefore it is not recommended as a system clock. 14.4.2.1 Power-On Calibration Power-on calibration begins after a time delay following the application of power. This time delay is determined by the setting of CalDly, as described in the Calibration Delay Section, below. The calibration process will be not be performed if the CAL pin is high at power up. In this case, the calibration cycle will not begin until the on-command calibration conditions are met. The ADC08D1000 will function with the CAL pin held high at power up, but no calibration will be done and performance will be impaired. A manual calibration, however, may be performed after powering up with the CAL pin high. See On-Command Calibration. The internal power-on calibration circuitry comes up in an unknown logic state. If the input clock is not running at power up and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the power consumption will typically be less than 200 mW. The power consumption will be normal after the clock starts. 14.4.2.2 On-Command Calibration On-command calibration may be run at any time in NORMAL (non-DES) mode only. Do not run a calibration while operating the ADC in Auto DES Mode. If the ADC is operating in Auto DES mode and a calibration cycle is required then the controlling application should bring the ADC into normal (non DES) mode before an On Command calibration is initiated. Once calibration has completed, the ADC can be put back into Auto DES mode. To initiate an on-command calibration, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power up will prevent execution of power-on calibration until the CAL pin is low for a minimum of tCAL_L input clock cycles, then brought high for a minimum of another tCAL_H input clock cycles. The calibration cycle will begin tCAL_H input clock cycles after the CAL pin is thus brought high. The CalRun signal should be monitored to determine when the calibration cycle has completed. The minimum tCAL_H and tCAL_L input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. As mentioned in Self-Calibration for best performance, a self calibration should be performed 20 seconds or more after power up and repeated when the operating temperature changes significantly, according to the particular system performance requirements. ENOB drops slightly with increasing junction temperature, and a self calibration eliminates the change. In the first example, (see Figure 45) a sample clock of 1GSPS is used to capture a full-scale 749MHz signal at the I-channel input as the junction temperature (TJ) is increased from 65°C to 125°C with no intermediate calibration cycles. The vertical line at 125°C is the result of an on-command calibration cycle that essentially eliminates the drop in ENOB. Of course, calibration cycles can be run more often, at smaller intervals of temperature change, if system design specifications require it. In the second example, (see Figure 46) the test method is the same and the Ichannel input signal is 249MHz. The variation in ENOB vs. TJ has a smaller range then the previous example, and is again removed by an on-command calibration cycle at the maximum test temperature. 40 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 CONTROL PINS (continued) Figure 45. ENOB vs. Junction Temperature, 749 MHz Input Figure 46. ENOB vs. Junction Temperature, 249 MHz Input 14.4.2.3 Calibration Delay The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of calibration, as described in Self-Calibration. The calibration delay values allow the power supply to come up and stabilize before calibration takes place. With no delay or insufficient delay, calibration would begin before the power supply is stabilized at its operating value and result in non-optimal calibration coefficients. If the PD pin is high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the power supply. Note that the calibration delay selection is not possible in the Extended Control mode and the short delay time is used. 14.4.3 Output Edge Synchronization DCLK signals are available to help latch the converter output data into external circuitry. The output data can be synchronized with either edge of these DCLK signals. That is, the output data transition can be set to occur with either the rising edge or the falling edge of the DCLK signal, so that either edge of that DCLK signal can be used to latch the output data into the receiving circuit. When OutEdge (pin 4) is high, the output data is synchronized with (changes with) the rising edge of the DCLK+ (pin 82). When OutEdge is low, the output data is synchronized with the falling edge of DCLK+. At the very high speeds of which the ADC08D1000 is capable, slight differences in the lengths of the DCLK and data lines can mean the difference between successful and erroneous data capture. The OutEdge pin is used to capture data on the DCLK edge that best suits the application circuit and layout. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 41 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com CONTROL PINS (continued) 14.4.4 LVDS Output Level Control The output level can be set to one of two levels with OutV (pin3). The strength of the output drivers is greater with OutV high. With OutV low there is less power consumption in the output drivers, but the lower output level means decreased noise immunity. For short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low. If the LVDS lines are long and/or the system in which the ADC08D1000 is used is noisy, it may be necessary to tie the OutV pin high. 14.4.5 Dual Edge Sampling IMPORTANT NOTE: When using the ADC in Extended Control Mode, the Configuration Register must only be written when the DES Enable bit = 0. Writing to the Configuration Register when the DES Enable bit = 1 can cause the internal DES clock generation circuitry to stop. The Dual Edge Sampling (DES) feature causes one of the two input pairs to be routed to both ADCs. The other input pair is deactivated. One of the ADCs samples the input signal on one input clock edge (duty cycle corrected), the other samples the input signal on the other input clock edge (duty cycle corrected). The result is a 1:4 demultiplexed output with a sample rate that is twice the input clock frequency. To use this feature in the non-enhanced control mode, allow pin 127 to float and the signal at the "I" channel input will be sampled by both converters. The Calibration Delay will then only be a short delay. In the enhanced control mode, either input may be used for dual edge sampling. See Dual-Edge Sampling. IMPORTANT NOTES : 1) For the Extended Control Mode - When using the Automatic Clock Phase Control feature in dual edge sampling mode, it is important that the automatic phase control is disabled (set bit 14 of DES Enable register Dh to 0) before the ADC is powered up. Not doing so may cause the device not to wake up from the power down state. 2) For the Non-Extended Control Mode - When the ADC08D1000 is powered up and DES mode is required, ensure that pin 127 (CalDly/DES/SCS) is initially pulled low during or after the power up sequence. The pin can then be allowed to float or be tied to VA / 2 to enter the DES mode. This will ensure that the part enters the DES mode correctly. 3) The automatic phase control should also be disabled if the input clock is interrupted or stopped for any reason. This is also the case if a large abrupt change in the clock frequency occurs. 4) If a calibration of the ADC is required in Auto DES mode, the device must be returned to the Normal Mode of operation before performing a calibration cycle. Once the Calibration has been completed, the device can be returned to the Auto DES mode and operation can resume. 14.4.6 Power Down Feature The Power Down pins (PD and PDQ) allow the ADC08D1000 to be entirely powered down (PD) or the "Q" channel to be powered down and the "I" channel to remain active. See Power Down for details on the power down feature. The digital data (+/-) output pins are put into a high impedance state when the PD pin for the respective channel is high. Upon return to normal operation, the pipeline will contain meaningless information and must be flushed. If the PD input is brought high while a calibration is running, the device will not go into power down until the calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in the power down state. 42 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 14.5 THE DIGITAL OUTPUTS The ADC08D1000 demultiplexes the output data of each of the two ADCs on the die onto two LVDS output buses (total of four buses, two for each ADC). For each of the two converters, the results of successive conversions started on the odd falling edges of the CLK+ pin are available on one of the two LVDS buses, while the results of conversions started on the even falling edges of the CLK+ pin are available on the other LVDS bus. This means that, the word rate at each LVDS bus is 1/2 the ADC08D1000 input clock rate and the two buses must be multiplexed to obtain the entire 1 GSPS conversion result. Since the minimum recommended input clock rate for this device is 200 MSPS (normal non DES mode), the effective rate can be reduced to as low as 100 MSPS by using the results available on just one of the two LVDS buses and a 200 MHz input clock, decimating the 200 MSPS data by two. There is one LVDS output clock pair (DCLK+/-) available for use to latch the LVDS outputs on all buses. Whether the data is sent at the rising or falling edge of DCLK is determined by the sense of the OutEdge pin, as described in Output Edge Synchronization. DDR (Double Data Rate) clocking can also be used. In this mode a word of data is presented with each edge of DCLK, reducing the DCLK frequency to 1/4 the input clock frequency. See the Timing Diagrams section for details. The OutV pin is used to set the LVDS differential output levels. See LVDS Output Level Control. The output format is Offset Binary. Accordingly, a full-scale input level with VIN+ positive with respect to VIN− will produce an output code of all ones, a full-scale input level with VIN− positive with respect to VIN+ will produce an output code of all zeros and when VIN+ and VIN− are equal, the output code will vary between codes 127 and 128. 14.6 POWER CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 33 µF capacitor should be placed within an inch (2.5 cm) of the A/D converter power pins. A 0.1 µF capacitor should be placed as close as possible to each VA pin, preferably within one-half centimeter. Leadless chip capacitors are preferred because they have low lead inductance. The VA and VDR supply pins should be isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A ferrite choke, such as the JW Miller FB20009-3B, is recommended between these supply lines when a common source is used for them. As is the case with all high speed converters, the ADC08D1000 should be assumed to have little power supply noise rejection. Any power supply used for digital circuitry in a system where a lot of digital power is being consumed should not be used to supply power to the ADC08D1000. The ADC supplies should be the same supply used for other analog circuitry, if not a dedicated supply. 14.6.1 Supply Voltage The ADC08D1000 is specified to operate with a supply voltage of 1.9V ±0.1V. It is very important to note that, while this device will function with slightly higher supply voltages, these higher supply voltages may reduce product lifetime. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 150 mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC08D1000 power pins. The Absolute Maximum Ratings should be strictly observed, even during power up and power down. A power supply that produces a voltage spike at turn-on and/or turn-off of power can destroy the ADC08D1000. The circuit of Figure 47 will provide supply overshoot protection. Many linear regulators will produce output spiking at power-on unless there is a minimum load provided. Active devices draw very little current until their supply voltages reach a few hundred millivolts. The result can be a turnon spike that can destroy the ADC08D1000, unless a minimum load is provided for the supply. The 100Ω resistor at the regulator output provides a minimum output current during power-up to ensure there is no turn-on spiking. In the circuit of Figure 47, an LM317 linear regulator is satisfactory if its input supply voltage is 4V to 5V. If a 3.3V supply is used, an LM1086 linear regulator is recommended. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 43 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com POWER CONSIDERATIONS (continued) Linear Regulator VIN 1.9V to ADC + 10 PF 210 + 33 PF 100 + 10 PF 110 Figure 47. Non-Spiking Power Supply The output drivers should have a supply voltage, VDR, that is within the range specified in the Operating Ratings table. This voltage should not exceed the VA supply voltage. If the power is applied to the device without an input clock signal present, the current drawn by the device might be below 200 mA. This is because the ADC08D1000 gets reset through clocked logic and its initial state is unknown. If the reset logic comes up in the "on" state, it will cause most of the analog circuitry to be powered down, resulting in less than 100 mA of current draw. This current is greater than the power down current because not all of the ADC is powered down. The device current will be normal after the input clock is established. 14.6.2 Thermal Management The ADC08D1000 is capable of impressive speeds and performance at very low power levels for its speed. However, the power consumption is still high enough to require attention to thermal management. For reliability reasons, the die temperature should be kept to a maximum of 130°C. That is, TA (ambient temperature) plus ADC power consumption times θJA (junction to ambient thermal resistance) should not exceed 130°C. This is not a problem if the ambient temperature is kept to a maximum of +85°C as specified in the Operating Ratings section. As a convenience to the user, the ADC08D100 incorporates a thermal diode to aid in temperature measurement. However, this diode has not been characterized and TI has no information to provide regarding its characteristics. Hence, no information is available as to the temperature accuracy attainable when using this diode. Please note that the following are general recommendations for mounting exposed pad devices onto a PCB. This should be considered the starting point in PCB and assembly process development. It is recommended that the process be developed based upon past experience in package mounting. The package of the ADC08D1000 has an exposed pad on its back that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. The land pattern design for lead attachment to the PCB should be the same as for a conventional HLQFP, but the exposed pad must be attached to the board to remove the maximum amount of heat from the package, as well as to ensure best product parametric performance. To maximize the removal of heat from the package, a thermal land pattern must be incorporated on the PC board within the footprint of the package. The exposed pad of the device must be soldered down to ensure adequate heat conduction out of the package. The land pattern for this exposed pad should be at least as large as the 5 x 5 mm of the exposed pad of the package and be located such that the exposed pad of the device is entirely over that thermal land pattern. This thermal land pattern should be electrically connected to ground. A clearance of at least 0.5 mm should separate this land pattern from the mounting pads for the package pins. 44 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 POWER CONSIDERATIONS (continued) 5.0 mm, min 0.25 mm, typ 0.33 mm, typ 1.2 mm, typ Figure 48. Recommended Package Land Pattern Since a large aperture opening may result in poor release, the aperture opening should be subdivided into an array of smaller openings, similar to the land pattern of Figure 48. To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done by including a copper area of about 2 square inches (6.5 square cm) on the opposite side of the PCB. This copper area may be plated or solder coated to prevent corrosion, but should not have a conformal coating, which could provide some thermal insulation. Thermal vias should be used to connect these top and bottom copper areas. These thermal vias act as "heat pipes" to carry the thermal energy from the device side of the board to the opposite side of the board where it can be more effectively dissipated. The use of 9 to 16 thermal vias is recommended. The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this wicking could cause voids in the solder between the package exposed pad and the thermal land on the PCB. Such voids could increase the thermal resistance between the device and the thermal land on the board, which would cause the device to run hotter. If it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the board near the thermal vias. .Allow for a thermal gradient between the temperature sensor and the ADC08D1000 die of θJ-PAD times typical power consumption = 2.8 x 1.6 = 4.5°C. Allowing for a 5.5°C (including an extra 1°C) temperature drop from the die to the temperature sensor, then, would mean that maintaining a maximum pad temperature reading of 124.5°C will ensure that the die temperature does not exceed 130°C, assuming that the exposed pad of the ADC08D1000 is properly soldered down and the thermal vias are adequate. (The inaccuracy of the temperature sensor is additional to the above calculation). 14.7 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A single ground plane should be used, instead of splitting the ground plane into analog and digital areas. Since digital switching transients are composed largely of high frequency components, the skin effect tells us that total ground plane copper weight will have little effect upon the logic-generated noise. Total surface area is more important than is total ground plane volume. Coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High power digital components should not be located on or near any linear component or power supply trace or plane that services analog or mixed signal components as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC, causing excessive noise in the conversion result. Generally, we assume that analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The input clock lines should be isolated from ALL other lines, analog AND digital. The generally accepted 90° crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 45 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com LAYOUT AND GROUNDING (continued) The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. This is especially important with the low level drive required of the ADC08D1000. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the analog ground plane. All analog circuitry (input amplifiers, filters, etc.) should be separated from any digital components. 14.8 DYNAMIC PERFORMANCE The ADC08D1000 is a.c. tested and its dynamic performance is ensured. To meet the published specifications and avoid jitter-induced noise, the clock source driving the CLK input must exhibit low rms jitter. The allowable jitter is a function of the input frequency and the input signal level, as described in THE CLOCK INPUTS. It is good practice to keep the ADC input clock line as short as possible, to keep it well away from any other signals and to treat it as a transmission line. Other signals can introduce jitter into the input clock signal. The clock signal can also introduce noise into the analog path if not isolated from that path. Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection to ground. This is because this path from the die to ground is a lower impedance than offered by the package pins. 14.9 USING THE SERIAL INTERFACE The ADC08D1000 may be operated in the non-extended control (non-Serial Interface) mode or in the extended control mode. Table 14 and Table 15 describe the functions of pins 3, 4, 14 and 127 in the non-extended control mode and the extended control mode, respectively. 14.9.1 Non-Extended Control Mode Operation Non-extended control mode operation means that the Serial Interface is not active and all controllable functions are controlled with various pin settings. That is, the full-scale range, single-ended or differential input, the power on calibration delay, the output voltage and the input coupling (a.c. or d.c.). The non-extended control mode is used by setting pin 14 high or low, as opposed to letting it float. Table 14 indicates the pin functions of the ADC08D1000 in the non-extended control mode. Table 14. Non-Extended Control Mode Operation (Pin 14 High or Low) Pin Low High Floating 3 Reduced VOD Normal VOD n/a DDR 4 OutEdge = Neg OutEdge = Pos 127 CalDly Short CalDly Long n/a 14 Reduced VIN Normal VIN Extended Control Mode Pin 3 can be either high or low in the non-extended control mode. Pin 14 must not be left floating to select this mode. See NORMAL/EXTENDED CONTROL for more information. Pin 4 can be high or low or can be left floating in the non-extended control mode. In the non-extended control mode, pin 4 high or low defines the edge at which the output data transitions. See Output Edge Synchronization for more information. If this pin is floating, the output clock (DCLK) is a DDR (Double Data Rate) clock (see Double Data Rate) and the output edge synchronization is irrelevant since data is clocked out on both DCLK edges. Pin 127 in the non-extended control mode sets the calibration delay. Pin 127 is not designed to remain floating. Table 15. Extended Control Mode Operation (Pin 14 Floating) Pin 46 Function 3 SCLK (Serial Clock) 4 SDATA (Serial Data) 127 SCS (Serial Interface Chip Select) Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 ADC08D1000 www.ti.com SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 14.10 COMMON APPLICATION PITFALLS Failure to write all register locations when using extended control mode. When using the serial interface, all 8 user registers must be written at least once with the default or desired values before calibration and subsequent use of the ADC. In addition, the first write to the DES Enable register (Dh) must load the default value (0x3FFFh). Once all registers have been written once, other desired settings, including enabling DES can be loaded. Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, no input should go more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on even a transient basis may not only cause faulty or erratic operation, but may impair device reliability. It is not uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground. Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance should control overshoot. Care should be taken not to overdrive the inputs of the ADC08D1000. Such practice may lead to conversion inaccuracies and even to device damage. Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in The Analog Inputs and THE ANALOG INPUT, the Input common mode voltage must remain within 50 mV of the VCMO output , which has a variability with temperature that must also be tracked. Distortion performance will be degraded if the input common mode voltage is more than 50 mV from VCMO . Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier to drive the ADC08D1000 as many high speed amplifiers will have higher distortion than will the ADC08D1000, resulting in overall system performance degradation. Driving the VBG pin to change the reference voltage. As mentioned in THE REFERENCE VOLTAGE, the reference voltage is intended to be fixed to provide one of two different full-scale values (650 mVP-P and 870 mVP-P). Over driving this pin will not change the full scale value, but can be used to change the LVDS common mode voltage from 0.8V to 1.2V by tying the VBG pin to VA. Driving the clock input with an excessively high level signal. The ADC input clock level should not exceed the level described in the Operating Ratings Table or the input offset could change. Inadequate input clock levels. As described in THE CLOCK INPUTS, insufficient input clock levels can result in poor performance. Excessive input clock levels could result in the introduction of an input offset. Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having other signals coupled to the input clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. Failure to provide adequate heat removal. As described in Thermal Management, it is important to provide adequate heat removal to ensure device reliability. This can be done either with adequate air flow or the use of a simple heat sink built into the board. The backside pad should be grounded for best performance. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 47 ADC08D1000 SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015 www.ti.com 15 Device and Documentation Support 15.1 Trademarks All trademarks are the property of their respective owners. 15.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 15.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 16 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 48 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: ADC08D1000 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) ADC08D1000CIYB/NOPB ACTIVE HLQFP NNB 128 60 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC08D1000 CIYB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of