ADC1038CIWM

ADC1038 ADC1038 10-Bit Serial I/O A/D Converter with Analog Multiplexer and Track/Hold Function Literature Number: SNAS063 ADC1038 10-Bit Serial I/O A/D Converter with Analog Multiplexer and Track/Hold Function General Description Features The ADC1038 is a 10-bit successive approximation A/D converters with serial I/O. The serial input controls a single-ended analog multiplexer that selects one of 8 input channels. The serial output data can be configured into a left- or right-justified format. An input track/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the analog input to vary during the A/D conversion cycle. Separate serial I/O and conversion clock inputs are provided to facilitate the interface to various microprocessors. n Serial I/O ( MICROWIRE™ compatible) n Separate asynchronous converter clock and serial data I/O clock n Analog input track/hold function n Ratiometric or absolute voltage referencing n No zero or full scale adjustment required n 0V to 5V analog input range with single 5V power supply n TTL/MOS input/output compatible n No missing codes Applications Key Specifications n n n n Engine control Process control Instrumentation Test equipment n n n n n n Resolution Total unadjusted error Single supply Power dissipation Max. conversion time (fC = 3 MHz) Serial data exchange time (fS = 1 MHz) 10 bit ± 1 LSB (max) 5V ± 5% 20 mW (max) 13.7 µs (max) 10 µs (max) Connection Diagrams SO Package DS010556-2 Top View ADC1038 In NS Package M20B Ordering Information Industrial −40˚C ≤ TA ≤ +85˚C ADC1038CIWM Package M20B TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS010556 www.national.com ADC1038 10-Bit Serial I/O A/D Converter with Analog Multiplexer and Track/Hold Function June 1999 Absolute Maximum Ratings (Notes 1, 3) Soldering Information SO Package (Note 7) : Vapor Phase (60 sec.) Infrared (15 sec.) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Inputs and Outputs Input Current at Any Pin (Note 4) Package Input Current (Note 4) Package Dissipation at TA = 25˚C (Note 5) ESD Susceptability (Note 6) 6.5V −0.3V to VCC + 0.3V ± 5 mA ± 20 mA Operating Ratings Temperature Range ADC1038CIWM Supply Voltage (VCC) Reference Voltage (VREF = VREF+ − VREF−) 500 mW 2000V 215˚C 220˚C −65˚C to +150˚C (Notes 2, 3) TMIN ≤ TA ≤ TMAX −40˚C ≤ TA ≤ +85˚C 4.75 VDC to 5.25 VDC 2.0 VDC to VCC + 0.05V Electrical Characteristics The following specifications apply for VCC = +5.0V, VREF = +4.6V, fS = 700 kHz, and fC = 3 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX ; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limit Units (Note 8) (Note 9) (Limits) ±1 LSB (max) 10 Bits (min) 5 kΩ (min) CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted CIN, CIWM, CMJ (Note 10) Error Differential Linearity RREF Reference Input Resistance VREF Reference Voltage VIN Analog Input Voltage 8 (Note 11) On Channel Leakage Current (Note 12) Off Channel Leakage Current On Channel = 5 VDC, Off Channel = 0 VDC On Channel = 0 VDC, Off Channel = 5 VDC On Channel = 5 VDC, Off Channel = 0 VDC On Channel = 0 VDC, Off Channel = 5 VDC (Note 12) Power Supply Zero Error Sensitivity Full Scale Error kΩ 11 kΩ (max) (VCC + 0.05) V (max) (VCC + 0.05) V (max) (GND − 0.05) V (min) 5.0 200 nA (max) 500 nA (max) 5.0 −200 nA (max) −500 nA (max) 5.0 5.0 4.75 VDC ≤ VCC ≤ 5.25 VDC −200 nA (max) −500 nA (max) 200 nA (max) 500 nA (max) ± 1/4 ± 1/4 LSB (max) LSB (max) DIGITAL AND DC CHARACTERISTICS VIN(1) Logical “1” Input Voltage VIN(0) Logical “0” Input Voltage IIN(1) Logical “1” Input Current IIN(0) Logical “0” Input Current VOUT(1) Logical “1” Output Voltage VOUT(0) Logical “0” Output Voltage IOUT TRI-STATE Output Current VCC = 5.25 VDC VCC = 4.75 VDC VIN = 5.0 VDC VIN = 0 VDC VCC = 4.75 VDC V (min) 0.8 V (max) 0.005 2.5 µA (max) −0.005 −2.5 µA (max) 2.4 V (min) IOUT = −360 µA IOUT = −10 µA VCC = 4.75 VDC IOUT = 1.6 mA ISOURCE Output Source Current ISINK Output Sink Current VOUT = 0V VOUT = 5V VOUT = 0V VOUT = VCC ICC Supply Current CS = HIGH, VREF Open www.national.com 2.0 2 4.5 V (min) 0.4 V (max) −0.01 −3 µA (max) 0.01 3 µA (max) −14 −6.5 mA (min) 16 8.0 mA (min) 1.5 3 mA (max) Electrical Characteristics (Continued) The following specifications apply for VCC = +5.0V, VREF = +4.6V, fS = 700 kHz, and fC = 3 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX ; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limit Units (Note 8) (Note 9) (Limits) 3.0 MHz (max) AC CHARACTERISTICS fC fS Conversion Clock (CCLK) 0.7 Frequency 4.0 Serial Data Clock (SCLK) Frequency (Note 13) TC tCA fC = 3 MHz, R/L = “0” fC = 3 MHz, R/L = “1” fC = 3 MHz, R/L = “0” or R/L = “1” MHz (min) 183 kHz (min) 622 2 kHz (min) 1.0 MHz (max) (max) Conversion Time Not Including MUX Addressing and 41 (1/fC) + 200 ns Analog Sampling Time Analog Input Sampling Times After Address is Latched,CS = Low 4.5 (1/fS) (max) + 200 ns tACC Access Time Delay from CS or OE OE = “0” 100 200 ns (max) 75 150 ns (min) 100 120 ns (max) Falling Edge to DO Data Valid tSET-UP Set-up Time of CS Falling Edge to SCLK Rising Edge t1H, t0H Delay from OE or CS Rising RL = 3 kΩ, CL = 100 pF Edge to DO TRI-STATE tHDI DI Hold Time from SCLK Rising Edge 0 50 ns (min) tSDI DI Set-up Time to SCLK Rising Edge 50 100 ns (min) tHDO DO Hold Time from SCLK Falling Edge tDDO Delay from SCLK Falling RL = 30 kΩ, CL = 100 pF RL = 30 kΩ, CL = 100 pF 70 10 ns (min) 150 250 ns (max) Edge to DO Data Valid tRDO tFDO CIN DO Rise Time DO Fall Time Input Capacitance RL = 30 kΩ, CL = 100 pF RL = 30 kΩ, CL = 100 pF TRI-STATE to High 35 75 ns (max) Low to High 75 150 ns (max) TRI-STATE to Low 35 75 ns (max) High to Low 75 150 ns (max) Analog Inputs (CH0–CH7) 50 pF All Other Inputs 7.5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: All voltages are measured with respect to AGND and DGND, unless otherwise specified. Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < DGND, or VIN > VCC) the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins. Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 125˚C. The typical thermal resistance (θJA) when board mounted is 64˚C/W. Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor. Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Databook section “Surface Mount” for other methods of soldering surface mount devices. Note 8: Typicals are at TJ = 25˚C and represent most likely parametric norm. Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors. Note 11: Two on-chip diodes are tied to each analog input. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 12: Channel leakage current is measured after the channel selection. Note 13: In order to synchronize the serial data exchange properly, SARS needs to go low after completion of the serial I/O data exchange. If this does not occur the output shift register will be reset and the correct output data lost. The minimum limit for SCLK will depend on CCLK frequency and whether right-justified or left-justified, and can be determined by the following equations: fS > (8.5/41) (fC) with right-justification (R/L = “1”) and fS > (2.5/41) (fC) with left-justification (R/L = “0”). 3 www.national.com Typical Performance Characteristics Power Supply Current (ICC) vs CCLK Power Supply Current (ICC) vs Ambient Temperature DS010556-29 DS010556-28 Linearity Error vs CCLK Frequency Linearity Error vs Ambient Temperature Zero Error vs Reference Voltage DS010556-34 4 DS010556-30 Linearity Error vs Reference Voltage DS010556-32 DS010556-31 www.national.com Reference Current (IREF) vs Ambient Temperature DS010556-33 Test Circuits t1H, t0H DO except “TRI-STATE” Leakage Current DS010556-6 DS010556-7 DS010556-8 Timing Diagrams DO High to Low State DS010556-9 DO Low to High State DO “TRI-STATE” Rise and Fall Times DS010556-10 DS010556-11 DI Data Input Timing DO Data Output Timing DS010556-12 DS010556-13 5 www.national.com Timing Diagrams (Continued) ADC1038 CS High during Conversion DS010556-15 CCLK continuously enabled ADC1038 CS Low Continuously DS010556-16 CCLK continuously enabled www.national.com 6 Multiplexer Address/Channel Assignment Table MUX Address A2 A1 MUX Address Analog A0 Channel Analog A2 A1 A0 Channel 0 0 CH4 Selected Selected 0 0 0 CH0 1 0 0 1 CH1 1 0 1 CH5 0 1 0 CH2 1 1 0 CH6 0 1 1 CH3 1 1 1 CH7 7 www.national.com DS010556-17 ADC1038 Functional Block Diagram 1.0 Pin Descriptions CCLK The clock applied to this input controls the successive approximation conversion time interval. The clock frequency applied to this input can be between 700 kHz and 4 MHz. SCLK The serial data clock input. The clock applied to this input controls the rate at which the serial data exchange occurs and the analog sampling time available to acquire an analog input voltage. The rising edge loads the information on the DI pin into the multiplexer address shift reg- www.national.com DI 8 ister (address register). This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts the data resulting from the previous A/D conversion out on DO. CS and OE enable or disable the above functions. The serial data input pin. The data applied to this pin is shifted by SCLK into the multiplexer address register. The first 3 bits of data (A0–A2) are the MUX channel address (see the Multiplexer Address/Channel Assignment tables). The fourth bit (R/L ) determines the data format of the conversion result in the conversion to be 1.0 Pin Descriptions DO 2.0 Functional Description (Continued) started. When R/L is low the output data format is left-justified; when high it is right-justified. When right-justified, six leading “0”s are output on DO before the MSB information; thus the complete conversion result is shifted out in 16 clock periods. The data output pin. The A/D conversion result (D0–D9) is output on this pin. This result can be left- or right-justified depending on the value of R/L bit shifted in on DI. SARS This pin is an output and indicates the status of the internal successive approximation register (SAR). When high, it signals that the A/D conversion is in progress. This pin is set high after the analog input sampling time (tCA) and remains high for 41 CCLK periods. When SARS goes low, the output shift register has been loaded with the conversion result and another A/D conversion sequence can be started. CS The chip select pin. When a low is applied to this pin, the rising edge of SCLK shifts the data on DI into the address register. 2.1 DIGITAL INTERFACE The ADC1038 implement its serial interface via seven digital control lines. There are two clock inputs for the ADC1038. The SCLK controls the rate at which the serial data exchange occurs and the duration of the analog sampling time window. The CCLK controls the conversion time and must be continuously enabled. A low on CS enables the rising edge of SCLK to shift in the serial multiplexer addressing data on the DI pin. The first three bits of this data select the analog input channel (see the Channel Addressing Tables). The following bit, R/L , selects the output data format (right-justified or left-justified) for the conversion to be started. With CS and OE low the DO pin is active (out of TRI-STATE ® ) and the falling edge of SCLK shifts out the data from the previous analog conversion. When the first conversion is started the data shifted out on DO is erroneous as it depends on the state of the Parallel Load 16-Bit Shift Register on power up, which is unpredictable. The ADC1031 implements its serial interface with only four control pins since it has only one analog input and comes in an eight pin mini-dip package. The SCLK, CCLK, CS and DO pins are available for the serial interface. The output data format cannot be selected and defaults to a left-justified format. The state of DO is controlled by CS only. OE The output enable pin. When OE and CS are both low the falling edge of SCLK shifts out the previous A/D conversion data on the DO pin. CH0–CH7 The analog inputs of the MUX. A channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register. Source impedances (RS) driving these inputs should be kept below 1 kΩ. If RS is greater than 1 kΩ, the sampled data comparator will not have enough time to acquire the correct value of the applied input voltage. The voltage applied to these inputs should not exceed VCC or go below DGND or AGND by more than 50 mV. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. VREF+ The positive analog voltage reference for the analog inputs. In order to maintain accuracy the voltage range of VREF (VREF = VREF+ − VREF−) is 2.5 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VCC + 50 mV. VREF− The negative voltage reference for the analog inputs. In order to maintain accuracy the voltage at this pin must not go below DGND and AGND by more than 50 mV or exceed 40% of VCC (for VCC = 5V, VREF− (max) = 2V). The power supply pin. The operating voltage range VCC of VCC is 4.75 VDC to 5.25 VDC. VCC should be bypassed with 10 µF and 0.1 µF capacitors to digital ground for proper operation of the A/D converter. 2.2 OUTPUT DATA FORMAT When R/L is low the output data format is left-justified; when high it is right-justified. When right-justified, six leading “0”s are output on DO before the MSB, and the complete conversion result is shifted out in 16 clock periods. 2.3 CS HIGH DURING CONVERSION With a continuous SCLK input, CS must be used to synchronize the serial data exchange. A valid CS is recognized if it occurs at least 100 ns (tSET-UP) before the rising edge of SCLK, thus causing data to be input on DI. If this does not occur there will be an uncertainty as to which SCLK rising edge will clock in the first bit of data. CS must remain low during the complete I/O exchange. Also, OE needs to be low if data from the previous conversion needs to be accessed. 2.3.1 CS LOW CONTINUOUSLY Another way to accomplish synchronous serial communication is to tie CS low continuously and use SARS and SCLK to synchronize the serial data exchange. SCLK can be disabled low during the conversion time and enabled after SARS goes low. With CS low during the conversion time a zero will remain on DO until the conversion is completed. Once the conversion is complete, the falling edge of SARS will shift out on DO the MSB before SCLK is enabled. This MSB would be a leading zero if right-justified or D9 if left-justified. The rest of the data will be shifted out once SCLK is enabled as discussed previously. If CS goes high during the conversion sequence DO is put into TRI-STATE, and the conversion result is not affected so long as CS remains high until the end of the conversion. DGND, AGND The digital and analog ground pins. In order to maintain accuracy the voltage difference between these two pins must not exceed 300 mV. 2.4 TYING SCLK and CCLK TOGETHER SCLK and CCLK can be tied together. The total conversion time will increase because the maximum clock frequency is now 1 MHz. The timing diagrams and the serial I/O exchange time (10 SCLK cycles) remain the same, but the conversion time (TC = 41 CCLK cycles) lengthens from a minimum of 14 µs to a minimum of 41 µs. In the case where CS GND The digital and analog ground pin for the ADC1031. 9 www.national.com 2.0 Functional Description of the full scale input signal amplitude to the value of the total error amplitude (including noise) caused by the transfer function of the A/D. An ideal 10 bit A/D converter with a total unadjusted error of 0 LSB would have a signal to noise ratio of about 62 dB, which can be derived from the equation: S/N = 6.02(N) + 1.76 (Continued) is low continuously, since the applied clock cannot be disabled, SARS must be used to synchronize the data output on DO and initiate a new conversion. The falling edge of SARS sends the MSB information out on DO. The next rising edge of the clock shifts in MUX address bit A2 on DI. The following clock falling edge will clock the next data bit of information out on DO. A conversion will be started after MUX addressing information has been loaded in (3 more clocks) and the analog sampling time (4.5 clocks) has elapsed. where S/N is in dB and N is the number of bits. Figure 2 shows the signal to noise ratio vs. input frequency of a typical ADC1038 with 1⁄2 LSB total unadjusted error. The dotted lines show signal-to-noise ratios for an ideal (noiseless) 10 bit A/D with 0 LSB error and an A/D with a 1 LSB error. The sample-and-hold error specifications are included in the error and timing specifications of the A/D. The hold step and gain error sample/hold specs are taken into account in the total unadjusted error specification, while the hold settling time is included in the A/D’s maximum conversion time specification. The hold droop rate can be thought of as being zero since an unlimited amount of time can pass between a conversion and the reading of data. However, once the data is read it is lost and another conversion is started. 3.0 Analog Considerations 3.1 THE INPUT SAMPLE AND HOLD The sample/hold capacitor is implemented in its capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog input. This sampling mode is maintained for 4.5 SCLK cycles after the multiplexer addressing information is loaded in. The sampling of the analog input starts on SCLK’s 4th rising edge. 3.2 INPUT FILTERING Due to the sampling nature of the analog input, transients will appear on the input pins. They are caused by the ladder capacitance and internal stray capacitance charging current flowing into VIN. These transients will not degrade the A/D’s performance if they settle out within the sampling window. This will occur if external source resistance is kept to a minimum. DS010556-18 FIGURE 1. Analog Input Model An acquisition window of 4.5 SCLK cycles is available to allow the ladder capacitance to settle to the analog input voltage. Any change in the analog voltage before or after the acquisition window will not effect the A/D conversion result. In the most simple case, the ladder’s acquisition time is determined by the Ron (9 kΩ) of the multiplexer switches, the CS1 (3.5 pF) and the total ladder (CL) and stray (CS2) capacitance (48 pF). For large source resistance the analog input can be modeled as an RC network as shown in Figure 1. The values shown yield an acquisition time of about 3 µs for 10 bit accuracy with a zero to a full scale change in the reading. External source resistance and capacitance will lengthen the acquisition time and should be accounted for. The curve “Signal to Noise Ratio vs Output Frequency” (Figure 2) gives an indication of the usable bandwidth. The signal to noise ratio of an ideal A/D is the ratio of the RMS value www.national.com DS010556-19 FIGURE 2. ADC1038 Signal to Noise Ratio vs Input Frequency 10 3.0 Analog Considerations (Continued) External Reference 2.5V Full Scale Power Supply as Reference DS010556-20 DS010556-21 Input Not Referred to GND DS010556-22 Note 14: *Current path must still exist from VIN(−) to ground FIGURE 3. Analog Input Options eration and in many cases the chip power supply can be used for transducer power as well as the VREF source. 3.3 REFERENCE AND INPUT The two VREF inputs are fully differential and define the zero to full-scale input range of the A to D converter. This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VREF+ and VREF−. By reducing VREF (VREF = VREF+ − VREF−) to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF = 2V then 1 LSB = 1.95 mV). The input/reference arrangement also facilitates ratiometric op- This reference flexibility lets the input span not only be varied but also offset from zero. The voltage at VREF− sets the input level which produces a digital output of all zeros. Though VIN is not itself differential, the reference design allows nearly differential-input capability for many measurement applications. Figure 3 shows some of the configurations that are possible. Power Supply Bypassing DS010556-23 DS010556-24 11 www.national.com Protecting the Analog Inputs DS010556-26 DS010556-25 Diodes are IN914 Zero-Shift and Span-Adjust (2V ≤ VIN ≤ 4.5V) DS010556-27 *1% resistors www.national.com 12 inches (millimeters) unless otherwise noted Order Number ADC1038CIWM NS Package Number M20B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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