ADC10464CIWM

ADC10461ADC10462ADC10464 10-Bit 600 ns AD Converter with Input Multiplexer and SampleHold General Description Features Using an innovative patented multistep conversion technique the 10-bit ADC10461 ADC10462 and ADC10464 CMOS analog-to-digital converters offer sub-microsecond conversion times yet dissipate a maximum of only 235 mW The ADC10461 ADC10462 and ADC10464 perform a 10-bit conversion in two lower-resolution ‘‘flashes’’ thus yielding a fast AD without the cost power dissipation and other problems associated with true flash approaches Dynamic performance (THD SN) is guaranteed The ADC10461 is pin-compatible with the ADC1061 but much faster thus providing a convenient upgrade path for the ADC1061 The analog input voltage to the ADC10461 ADC10462 and ADC10464 is sampled and held by an internal sampling circuit Input signals at frequencies from dc to over 200 kHz can therefore be digitized accurately without the need for an external sample-and-hold circuit The ADC10462 and ADC10464 include a ‘‘speed-up’’ pin Connecting an external resistor between this pin and ground reduces the typical conversion time to as little as 350 ns with only a small increase in linearity error For ease of interface to microprocessors the ADC10461 ADC10462 and ADC10464 have been designed to appear as a memory location or IO port without the need for external interface logic Y Y Y Y Y Built-in sample-and-hold Single a 5V supply 1 2 or 4-input multiplexer options No external clock required Speed adjust pin for faster conversions (ADC10462 and ADC10464) Key Specifications Y Y Y Y Y Conversion time to 10 bits 600 ns typical 900 ns max over temperature Sampling Rate 800 kHz Low power dissipation 235 mW (max) b 60 dB (max) Total harmonic distortion (50 kHz) No missing codes over temperature Applications Y Y Y Y Digital signal processor front ends Instrumentation Disk drives Mobile telecommunications Ordering Information ADC10461 ADC10464 Industrial (b40 C s TA s a 85 C) Package ADC10461CIN ADC10461CIWM N20A Molded DIP M20B Small Outline Industrial (b40 C s TA s a 85 C) ADC10464CIN ADC10464CIWM Package N28B Molded DIP M28B Small Outline ADC10462 Industrial (b40 C s TA s a 85 C) ADC10462CIN ADC10462CIWM Package N24A Molded DIP M24B Small Outline US Patent Number 4918449 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TLH11108 RRD-B30M75Printed in U S A ADC10461ADC10462ADC10464 10-Bit 600 ns AD Converter with Input Multiplexer and SampleHold December 1994 Absolute Maximum Ratings (Notes 1 2) Supply Voltage (V a e AVCC e DVCC) Voltage at Any Input or Output Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) ESD Susceptability (Note 5) Soldering Information (Note 6) N Package (10 Sec) SO Package Vapor Phase (60 Sec) Infrared (15 Sec) b 65 C to a 150 C Storage Temperature Range If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications 150 C Junction Temperature b 03V to a 6V Operating Ratings (Notes 1 2) Temperature Range TMIN s TA s TMAX ADC10461CIN ADC10461CIWM ADC10462CIN ADC10462CIWM ADC10464CIN b 40 C s TA s a 85 C ADC10464CIWM Supply Voltage Range 45V to 55V b 03V to V a a 03V 5 mA 20 mA 875 mW 2000V 260 C 215 C 220 C Converter Characteristics The following specifications apply for V a e a 5V VREF( a ) e a 5V VREF(b) e GND and Speed Adjust pin unconnected unless otherwise specified Boldface limits apply for TA e TJ e TMin to TMax all other limits TA e TJ e a 25 C Symbol Parameter Conditions Typical (Note 7) 10 Resolution Integral Linearity Error RSA t 18 kX g 05 ENOB Bits LSB g1 LSB (max) Full-Scale Error g1 LSB (max) 0 (max) RSA t 18 kX g 05 Missing Codes SNR Units (Limit) Offset Error Total Unadjusted Error THD Limit (Note 8) Power Supply Sensitivity V a e 5V g 5% VREF e 45V V a e 5V g 10% VREF e 45V Total Harmonic Distortion fIN fIN fIN fIN Signal-to-Noise Ratio Effective Number of Bits e e e e 1 kHz 485 VP-P 50 kHz 485 VP-P 100 kHz 485 VP-P 240 kHz 485 VP-P LSB g  g  b 68 b 66 b 62 b 58 LSB LSB b 60 fIN e 1 kHz 485 VP-P fIN e 50 kHz 485 VP-P fIN e 100 kHz 485 VP-P 61 60 60 fIN e 1 kHz 485 VP-P fIN e 50 kHz 485 VP-P 96 95 9 58 dB dB (max) dB dB dB dB (min) dB Bits Bits (min) RREF Reference Resistance 650 400 X (min) RREF Reference Resistance 650 900 X (max) VREF( a ) VREF( a ) Input Voltage V a a 005 V (max) VREF(b) VREF(b) Input Voltage GND b 005 V (min) VREF( a ) VREF( a ) Input Voltage VREF(b) V (min) VREF(b) VREF(b) Input Voltage VREF( a ) V (max) VIN Input Voltage V a a 005 V (max) VIN Input Voltage GND b 005 V (min) 3 b3 mA (max) mA (max) OFF Channel Input Leakage Current ON Channel Input Leakage Current CS e V a  VIN e V a CS e V a  VIN e V a 2 001 g1 DC Electrical Characteristics The following specifications apply for V a e a 5V VREF( a ) e 5V VREF(b) e GND and Speed Adjust pin unconnected unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e a 25 C Symbol Parameter Logical ‘‘1’’ Input Voltage V a e 55V VIN(0) Logical ‘‘0’’ Input Voltage Va e IIN(1) Logical ‘‘1’’ Input Current VIN(1) e 5V IIN(0) Logical ‘‘0’’ Input Current VIN(0) 0V VOUT(1) Logical ‘‘1’’ Output Voltage V a e 45V IOUT e b360 mA V a e 45V IOUT e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage V a e 45V IOUT e 16 mA IOUT TRI-STATE Output Current VOUT e 5V VOUT e 0V DICC DVCC Supply Current AICC AVCC Supply Current VIN(1) Typical (Note 7) Conditions Limit (Note 8) Units (Limits) 20 V (min) 08 V (max) 0005 30 mA (max) b 0005 b 30 mA (max) 24 425 V (min) V (min) 45V 04 V (max) 01 b 01 50 b 50 mA (max) mA (max) CS e SH e RD e 0 RSA e % CS e SH e RD e 0 RSA e 18 kX 10 10 2 mA (max) mA (max) CS e SH e RD e 0 RSA e % CS e SH e RD e 0 RSA e 18 kX 30 30 45 mA (max) mA (max) AC Electrical Characteristics The following specifications apply for V a e a 5V tr e tf e 20 ns VREF( a ) e 5V VREF(b) e GND and Speed Adjust pin unconnected unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e a 25 C Symbol tCONV tCRD Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limits) Mode 1 Conversion Time from Rising Edge of SH to Falling Edge of INT CIN CIWM Suffixes RSA e 18k 600 375 750900 ns (max) ns Mode 2 Conversion Time CIN CIWM Suffixes Mode 2 RSA e 18k 850 530 1400 ns (max) ns tACC1 Access Time (Delay from Falling Edge of RD to Output Valid) Mode 1 CL e 100 pF 30 60 ns (max) tACC2 Access Time (Delay from Falling Edge of RD to Output Valid) Mode 2 CL e 100 pF 900 tCRD a 50 ns (max) tSH Minimum Sample Time (Figure 1)  (Note 9) 250 ns (max) t1H t0H TRI-STATE Control (Delay from Rising Edge of RD to High-Z State) RL e 1k CL e 10 pF 30 60 ns (max) tINTH Delay from Rising Edge of RD to Rising Edge of INT CL e 100 pF 25 50 ns (max) tP Delay from End of Conversion to Next Conversion 50 ns (max) 3 AC Electrical Characteristics (Continued) The following specifications apply for V a e a 5V tr e tf e 20 ns VREF( a ) e 5V VREF(b) e GND and Speed Adjust pin unconnected unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e a 25 C (Continued) Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limits) ns (max) tMS Multiplexer Control Setup Time 10 75 tMH Multiplexer Hold Time 10 40 CVIN Analog Input Capacitance 35 pF (max) COUT Logic Output Capacitance 5 pF (max) CIN Logic Input Capacitance 5 pF (max) ns (max) Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditons Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k GND or VIN l V a ) the absolute value of current at that pin should be limited to 5 mA or less The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four Note 4 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX iJA and the ambient temperature TA The maximum allowable power dissipation at any temperature is PD e (TJMAX b TA)iJA or the number given in the Absolute Maximum Ratings whichever is lower In most cases the maximum derated power dissipation will be reached only during fault conditions For these devices TJMAX for a board-mounted device can be found from the tables below ADC10462 ADC10461 Suffix iJA ( CW) ADC10464 iJA ( CW) Suffix Suffix iJA ( CW) CIN 70 CIN 60 CIN 53 CIWM 85 CIWM 82 CIWM 78 Note 5 Human body model 100 pF discharged through a 15 kX resistor Note 6 See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devices Note 7 Typicals represent most likely parametric norm Note 8 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 9 Accuracy may degrade if tSH is shorter than the value specified See curves of Accuracy vs tSH 4 Typical Performance Characteristics Zero (Offset) Error vs Reference Voltage Linearity Error vs Reference Voltage Analog Supply Current vs Temperature Digital Supply Current vs Temperature Conversion Time vs Temperature Conversion Time vs Temperature Conversion Time vs Speed-Up Resistor (ADC10462 and ADC10464 Only) Conversion Time vs Speed-Up Resistor (ADC10462 and ADC10464 Only) Spectral Response with 100 kHz Sine Wave Input Spectral Response with 100 kHz Sine Wave Input TLH11108– 1 5 Typical Performance Characteristics (Continued) Signal-to-Noise a THD Ratio vs Signal Frequency Linearity Change vs Speed-Up Resistor (ADC10462 and ADC10464 Only) Linearity Change vs Speed-Up Resistor (ADC10462 and ADC10464 Only) Linearity Error Change vs Sample Time TLH11108– 2 6 TRI-STATE Test Circuits and Waveforms TLH11108– 4 TLH11108– 3 TLH11108– 6 TLH11108– 5 Timing Diagrams TLH11108– 7 FIGURE 1 Mode 1 The conversion time (tCONV) is set by the internal timer 7 Timing Diagrams (Continued) TLH11108– 8 FIGURE 2 Mode 2 (RD Mode) The conversion time (tCRD) includes the sampling time and is determined by the internal timer Simplified Block Diagram TLH11108– 9 ADC10461 Only ADC10462 and ADC10464 Only ADC10464 Only 8 Connection Diagrams Dual-In-Line Package Dual-In-Line Package Dual-In-Line Package TLH11108–10 Top View TLH11108– 11 Top View TLH11108– 12 Top View Pin Descriptions VREFb VREF a DVCC AVCC These are the digital and analog positive supply voltage inputs They should always be connected to the same voltage source but are brought out separately to allow for separate bypass capacitors Each supply pin should be bypassed with a 01 mF ceramic capacitor in parallel with a 10 mF tantalum capacitor to ground INT This is the active low interrupt output INT goes low at the end of each conversion and returns to a high state following the rising edge of RD SH This is the SampleHold control input When this pin is forced low (and CS is low) it causes the analog input signal to be sampled and initiates a new conversion RD This is the active low Read control input When this RD and CS are low any data present in the output registers will be placed on the data bus CS This is the active low Chip Select control input When low this pin enables the RD and SH pins On the multiple-input devices (ADC10462 and ADC10464) these pins select the analog input that will be connected to the AD during the conversion The input is selected based on the state of S0 and S1 when SH makes its High-to-Low transition (See the Timing Diagrams) The ADC10464 includes both S0 and S1 The ADC10462 includes just S0 and the ADC10461 includes neither S0 S1 These are the reference voltage inputs They may be placed at any voltage between GND and VCC but VREF a must be greater than VREFb An input voltage equal to VREFb produces an output code of 0 and an input voltage equal to (VREF a b 1 LSB) produces an output code of 1023 VIN VIN0 VIN1 VIN2 VIN3 These are the analog input pins The ADC10461 has one input (VIN) the ADC10462 has two inputs (VIN0 and VIN1) and the ADC10464 has four inputs (VIN0 VIN1 VIN2 and VIN3) The impedance of the source should be less than 500X for best accuracy and conversion speed For accurate conversions no input pin (even one that is not selected) should be driven more than 50 mV above VCC or 50 mV below ground GND AGND These are the power supply ground pins The DGND ADC10461 has a single ground pin (GND) and the ADC10462 and ADC10464 have separate analog and digital ground pins (AGND and DGND) for separate bypassing of the analog and digital supplies The ground pins should be connected to a stable noise-free system ground For the devices with two ground pins both pins should be returned to the same potential DB0 – DB9 These are the TRI-STATE output pins SPEED ADJ 9 (ADC10462 and ADC10464 only) This pin is normally left unconnected but by connecting a resistor between this pin and ground the conversion time can be reduced See the Typical Performance Curves and the table of Electrical Characteristics Functional Description To perform a conversion the estimator compares the input voltage with the tap voltages on the seven resistors on the left The estimator decoder then determines which MSB Ladder tap points will be connected to the sixteen comparators on the right For example assume that the estimator determines that VIN is between 1116 and 1316 of VREF The estimator decoder will instruct the comparator MUX to connect the 16 comparators to the taps on the MSB ladder between 1016 and 1416 of VREF The 16 comparators will then perform the first flash conversion Note that since the comparators are connected to ladder voltages that extend beyond the range indicated by the estimator circuit errors in the estimator as large as 116 of the reference voltage (64 LSBs) will be corrected This first flash conversion produces the six most significant bits of datafour bits in the flash itself and 2 bits in the estimator The remaining four LSBs are now determined using the same sixteen comparators that were used for the first flash conversion The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted from the input voltage and compared with the tap points on the sixteen LSB Ladder resistors The result of this second four-bit flash conversion is then decoded and the full 10-bit result is latched Note that the sixteen comparators used in the first flash conversion are reused for the second flash Thus the multistep conversion technique used in the ADC10461 ADC10462 and ADC10464 needs only a small fraction of the number of comparators that would be required for a traditional flash converter and far fewer than would be used in a conventional half-flash approach This allows the ADC10461 ADC10462 and ADC10464 to perform highspeed conversions without excessive power drain The ADC10461 ADC10462 and ADC10464 digitize an analog input signal to 10 bits accuracy by performing two lowerresolution ‘‘flash’’ conversions The first flash conversion provides the six most significant bits (MSBs) of data and the second flash conversion provides the four least significant bits LSBs) Figure 3 is a simplified block diagram of the converter Near the center of the diagram is a string of resistors At the bottom of the string of resistors are 16 resistors each of which has a value 11024 the resistance of the whole resistor string These lower 16 resistors (the LSB Ladder) therefore have a voltage drop of 161024 or 164 of the total reference voltage (VREF a b VREFb) across them The remainder of the resistor string is made up of eight groups of eight resistors connected in series These comprise the MSB Ladder Each section of the MSB Ladder has  of the total reference voltage across it and each of the LSB resistors has 164 of the total reference voltage across it Tap points across these resistors can be connected in groups of sixteen to the sixteen comparators at the right of the diagram On the left side of the diagram is a string of seven resistors connected between VREF a and VREFb Six comparators compare the input voltage with the tap voltages on this resistor string to provide a low-resolution ‘‘estimate’’ of the input voltage This estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the right Note that the comparators on the left needn’t be very accurate they simply provide an estimate of the input voltage Only the sixteen comparators on the right and the six on the left are necessary to perform the initial six-bit flash conversion instead of the 64 comparators that would be required using conventional half-flash methods TLH11108– 13 FIGURE 3 Block Diagram of the Multistep Converter Architecture 10 Applications Information 1953 mV) Note however that linearity and offset errors become larger when lower reference voltages are used See the Typical Performance Curves for more information For this reason reference voltages less than 2V are not recommended In most applications VREFb will simply be connected to ground but it is often useful to have an input span that is offset from ground This situation is easily accommodated by the reference configuration used in the ADC10461 ADC10462 and ADC10464 VREFb can be connected to a voltage other than ground as long as the voltage source connected to this pin is capable of sinking the converter’s reference current (125 mA Max  VREF e 5V) If VREFb is connected to a voltage other than ground bypass it with multiple capacitors Since the resistance between the two reference inputs can be as low as 400X the voltage source driving the reference inputs should have low output impedance Any noise on either reference input is a potential cause of conversion errors so each of these pins must be supplied with a clean low noise voltage source Each reference pin should be bypassed with a 10 mF tantalum and a 01 mF ceramic 10 MODES OF OPERATION The ADC10461 ADC10462 and ADC10464 have two basic digital interface modes Figure 1 and Figure 2 are timing diagrams for the two modes The ADC10462 and ADC10464 have input multiplexers that are controlled by the logic levels on pins S0 and S1 when SH goes low Table I is a truth table showing how the input channnels are assigned Mode 1 In this mode the SH pin controls the start of conversion SH is pulled low for a minimum of 250 ns This causes the comparators in the ‘‘coarse’’ flash converter to become active When SH goes high the result of the coarse conversion is latched and the ‘‘fine’’ conversion begins After 600 ns (typical) INT goes low indicating that the conversion results are latched and can be read by pulling RD low Note that CS must be low to enable SH or RD CS is internally ‘‘ANDed’’ with SH and RD the input voltage is sampled when CS and SH are low and data is read when CS and RD are low INT is reset high on the rising edge of RD TABLE I Input Multiplexer Programming ADC10464 ADC10462 S1 S0 Channel S0 Channel 0 0 VIN0 0 VIN0 0 1 VIN1 1 1 0 VIN2 1 1 30 THE ANALOG INPUT The ADC10461 ADC10462 and ADC10464 sample the analog input voltage once every conversion cycle When this happens the input is briefly connected to an impedance approximately equal to 600X in series with 35 pF Short-duration current spikes can therefore be observed at the analog input during normal operation These spikes are normal and do not degrade the converter’s performance Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy Therefore only signal sources with output impedances less than 500X should be used if rated accuracy is to be achieved at the minimum sample time (250 ns maximum) If the sampling time is increased the source impedance can be larger If a signal source has a high output impedance its output should be buffered with an operational amplifier The operational amplifier’s output should be well-behaved when driving a switched 35 pF600X load Any ringing or voltage shifts at the op amp’s output during the sampling period can result in conversion errors Correct conversion results will be obtained for input voltages greater than GND b 50 mV and less than V a a 50 mV Do not allow the signal source to drive the analog input pin more than 300 mV higher than AVCC and DVCC or more than 300 mV lower than GND If an analog input pin is forced beyond these voltages the current flowing through the pin should be limited to 5 mA or less to avoid permanent damage to the IC The sum of all the overdrive currents into all pins must be less than 20 mA When the input signal is expected to extend more than 300 mV beyond the power supply limits some sourt of protection scheme should be used A simple network using diodes and resistors is shown in Figure 4  VIN1 (b) VIN3 (a) Mode 2 In Mode 2 also called ‘‘RD mode’’ the SH and RD pins are tied together A conversion is initiated by pulling both pins low The AD converter samples the input voltage and causes the coarse comparators to become active An internal timer then terminates the coarse conversion and begins the fine conversion 850 ns (typical) after SH and RD are pull low INT goes low indicating that the conversion is completed Approximately 20 ns later the data appearing on the TRI-STATE output pins will be valid Note that data will appear on these pins throughout the conversion but until INT goes low the data at the output pins will be the result of the previous conversion 20 REFERENCE CONSIDERATIONS The ADC10461 ADC10462 and ADC10464 each have two reference inputs These inputs VREF a and VREFb are fully differential and define the zero to full-scale range of the input signal The reference inputs can be connected to span the entire supply voltage range (VREFb e 0V VREF a e VCC) for ratiometric applications or they can be connected to different voltages (as long as they are between ground and VCC) when other input spans are required Reducing the overall VREF span to less than 5V increases the sensitivity of the converter (eg if VREF e 2V then 1 LSB e 11 Applications Information (Continued) TLH11108– 14 FIGURE 4 Typical Connection Note the multiple bypass capacitors on the reference and power supply pins If VREFb is not grounded it should also be bypassed to analog ground using multiple capacitors (see 50 ‘‘Power Supply Considerations’’) AGND and DGND should be at the same potential VIN0 is shown with an input protection network Pin 17 is normally left open but optional ‘‘speedup’’ resistor RSA can be used to reduce the conversion time supplies The devices with separate analog and digital ground pins should have their ground pins connected to the same potential and all grounds should be ‘‘clean’’ and free of noise In systems with multiple power supplies careful attention to power supply sequencing may be necessary to avoid overdriving inputs The AD converter’s power supply pins should be at the proper voltage before digital or analog signals are applied to any of the other pins 40 INHERENT SAMPLE-AND-HOLD Because the ADC10461 ADC10462 and ADC10464 sample the input signal once during each conversion they are capable of measuring relatively fast input signals without the help of an external sample-hold In a non-sampling successive-approximation AD converter regardless of speed the input signal must be stable to better than g 12 LSB during each conversion cycle or significant errors will result Consequently even for many relatively slow input signals the signals must be externally sampled and held constant during each conversion if a SAR with no internal sample-andhold is used Because they incorporate a direct samplehold control input the ADC10461 ADC10462 and ADC10464 are suitable for use in DSP-based systems The SH input allows synchronization of the AD converter to the DSP system’s sampling rate and to other ADC10461s ADC10462s and ADC10464s The ADC10461 ADC10462 and ADC10464 can perform accurate conversions of input signals with frequency components from DC to over 250 kHz 60 LAYOUT AND GROUNDING In order to ensure fast accurate conversions from the ADC10461 ADC10462 and ADC10464 it is necessary to use appropriate circuit board layout techniques The analog ground return path should be low-impedance and free of noise from other parts of the system Noise from digital circuitry can be especially troublesome so digital grounds should always be separate from analog grounds For best performance separate ground planes should be provided for the digital and analog parts of the system All bypass capacitors should be located as close to the converter as possible and should connect to the converter and to ground with short traces The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input Any external component (eg a filter capacitor) connected across the converter’s input should be connected to a very clean ground return point Grounding the component at the wrong point will result in reduced conversion accuracy 50 POWER SUPPLY CONSIDERATIONS The ADC10461 ADC10462 and ADC10464 are designed to operate from a a 5V (nominal) power supply There are two supply pins AVCC and DVCC These pins allow separate external bypass capacitors for the analog and digital portions of the circuit To guarantee accurate conversions the two supply pins should be connected to the same voltage source and each should be bypassed with a 01 mF ceramic capacitor in parallel with a 10 mF tantalum capacitor Depending on the circuit board layout and other system considerations more bypassing may be necessary The ADC10461 has a single ground pin and the ADC10462 and ADC10464 each have separate analog and digital ground pins for separate bypassing of the analog and digital 70 DYNAMIC PERFORMANCE Many applications require the AD converter to digitize AC signals but conventional DC integral and differential nonlinearity specifications don’t accurately predict the AD converter’s performance with AC input signals The important specifications for AC applications reflect the converter’s ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal Dynam12 Applications Information (Continued) ic characteristics such as signal-to-noise ratio (SNR) and total harmonic distortion (THD) are quantitative measures of this capability of the AD converter A real AD converter will have some amount of noise and distortion and the effective bits can be found by An AD converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods A sinusoidal waveform is applied to the AD converter’s input and the transform is then performed on the digitized waveform The resulting spectral plot might look like the ones shown in the typical performance curves The large peak is the fundamental frequency and the noise and distortion components (if any are present) are visible above and below the fundamental frequency Harmonic distortion components appear at whole multiples of the input frequency Their amplitudes are combined as the square root of the sum of the squares and compared to the fundamental amplitude to yield the THD specification Guaranteed limits for THD are given in the table of Electrical Characteristics Signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other frequencies excluding any harmonic distortion components Guaranteed limits are given in the Electrical Characteristics table An alternative definition of signal-to-noise ratio includes the distortion components along with the random noise to yield a signal-to-noise-plus-distortion ration or S(N a D) The THD and noise performance of the AD converter will change with the frequency of the input signal with more distortion and noise occurring at higher signal frequencies One way of describing the AD’s performance as a function of signal frequency is to make a plot of ‘‘effective bits’’ versus frequency An ideal AD converter with no linearity errors or self-generated noise will have a signal-to-noise ratio equal to (602n a 18) dB where n is the resolution in bits n (effective) e S(N a D) (dB) b 18 602 where S(N a D) is the ratio of signal to noise and distortion which can vary with frequency As an example an ADC10461 with a 485 VP-P 100 kHz sine wave input signal will typically have a signal-to-noiseplus-distortion ratio of 592 dB which is equivalent to 953 effective bits As the input frequency increases noise and distortion gradually increase yielding a plot of effective bits or S(N a D) as shown in the typical performance curves 80 SPEED ADJUST In applications that require faster conversion times the Speed Adjust pin (pin 14 on the ADC10462 pin 17 on the ADC10464) can significantly reduce the conversion time The speed adjust pin is connected to an on-chip current source that determines the converter’s internal timing By connecting a resistor between the speed adjust pin and ground as shown in Figure 4  the internal programming current is increased which reduces the conversion time As an example an 18k resistor reduces the conversion time of a typical part from 600 ns to 350 ns with no significant effect on linearity Using smaller resistors to further decrease the conversion time is possible as well although the linearity will begin to degrade somewhat (see curves) Note that the resistor value needed to obtain a given conversion time will vary from part to part so this technique will generally require some ‘‘tweaking’’ to obtain satisfactory results For applications that require guaranteed performance using the speed adjust pin the ADC10662 and ADC10664 are tested and guaranteed for static and dynamic performance with a fixed value of speed-up resistor 13 14 Physical Dimensions inches (millimeters) Order Number ADC10461CIWM NS Package Number M20B 15 Physical Dimensions inches (millimeters) (Continued) Order Number ADC10462CIWM NS Package Number M24B Order Number ADC10464CIWM NS Package Number M28B 16 Physical Dimensions inches (millimeters) (Continued) Order Number ADC10461CIN NS Package Number N20A Order Number ADC10462CIN NS Package Number N24A 17 ADC10461ADC10462ADC10464 10-Bit 600 ns AD Converter with Input Multiplexer and SampleHold Physical Dimensions inches (millimeters) (Continued) Order Number ADC10464CIN NS Package Number N28B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive PO Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 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