ADC10734CIWMX

ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference Check for Samples: ADC10731, ADC10732, ADC10734, ADC10738 FEATURES DESCRIPTION • • • • • • • • The ADC10731, ADC10732 and ADC10734 are obsolete or on lifetime buy and included for reference only. 1 2 0V to Analog Supply Input Range Serial I/O (MICROWIRE Compatible) Software or Hardware Power Down Analog Input Sample/Hold Function Ratiometric or Absolute Voltage Referencing No Zero or Full Scale Adjustment Required No Missing Codes Over Temperature TTL/CMOS Input/Output Compatible APPLICATIONS • • • Medical Instruments Portable and Remote Instrumentation Test Equipment KEY SPECIFICATIONS • • • • • • • Resolution 10 Bits Plus Sign Single Supply 5 V Power Consumption 37 mW (Max) In Power Down Mode 18 μW Conversion Time 5 μs (Max) Sampling Rate 74 kHz (Max) Band-Gap Reference 2.5V ±2% (Max) This series of CMOS 10-bit plus sign successive approximation A/D converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The 1-, 2-, 4-, or 8-channel multiplexers can be software configured for singleended or differential mode of operation. An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the analog input to vary during the A/D conversion cycle. In the differential mode, valid outputs are obtained even when the negative inputs are greater than the positive because of the 10-bit plus sign output data format. The serial I/O is configured to comply with the MICROWIRE serial data exchange standard for easy interface to the COPS and HPC families of controllers, and can easily interface with standard shift registers and microprocessors. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com ADC10738 Simplified Block Diagram Connection Diagrams The ADC10731, ADC10732 and ADC10734 are obsolete in all packages. They are in this data sheet for reference only. Top View Figure 1. ADC10731 16-Pin SOIC Package See Package Number DW0016B 2 Submit Documentation Feedback Top View Figure 2. ADC10734 20-Pin SOIC Package See Package Number DW0020B Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Top View Top View Figure 3. ADC10732 20-Pin SOIC Package See Package Number DW0020B Figure 4. ADC10738 24-Pin SOIC Package See Package Number DW0024B Figure 5. SSOP Package See Package Number DB0020A Table 1. Pin Descriptions Pin Name Description CLK The clock applied to this input controls the successive approximation conversion time interval, the acquisition time and the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts the data resulting from the A/D conversion out on DO. CS enables or disables the above functions. The clock frequency applied to this input can be between 5 kHz and 3 MHz DI This is the serial data input pin. The data applied to this pin is shifted by CLK into the multiplexer address register. Table 2, Table 3, Table 4 show the multiplexer address assignment. DO The data output pin. The A/D conversion result (DB0-SIGN) are clocked out by the failing edge of CLK on this pin. CS This is the chip select input pin. When a logic low is applied to this pin, the rising edge of CLK shifts the data on DI into the address register. This low also brings DO out of TRISTATE after a conversion has been completed PD This is the power down input pin. When a logic high is applied to this pin the A/D is powered down. When a low is applied the A/D is powered up. SARS This is the successive approximation register status output pin. When CS is high this pin is in TRI-STATE. With CS low this pin is active high when a conversion is in progress and active low at all other times. CH0–CH7 These are the analog inputs of the MUX. A channel input is selected by the address information at the DI pin, which is loaded on the rising edge of CLK into the address register (see Table 2, Table 3, Table 4). The voltage applied to these inputs should not exceed AV+ or go below GND by more than 50 mV. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 3 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Table 1. Pin Descriptions (continued) Pin Name Description COM This pin is another analog input pin. It can be used as a “pseudo ground” when the analog multiplexer is single-ended. VREF+ This is the positive analog voltage reference input. In order to maintain accuracy, the voltage range VREF (VREF = VREF+–VREF−) is 0.5 VDCto 5.0 VDC and the voltage at VREF+ cannot exceed AV+ +50 mV. VREF− The negative voltage reference input. In order to maintain accuracy, the voltage at this pin must not go below GND − 50 mV or exceed AV+ + 50 mV. AV+, DV+ These are the analog and digital power supply pins. These pins should be tied to the same power supply and bypassed separately. The operating voltage range of AV+ and DV+ is 4.5 VDC to 5.5 VDC. DGND This is the digital ground pin. AGND This is the analog ground pin. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (V+ = AV+ = DV+) 6.5V Total Reference Voltage (VREF+–VREF−) 6.5V + V + 0.3V to −0.3V Voltage at Inputs and Outputs Input Current at Any Pin (4) 30 mA Package Input Current (4) 120 mA Package Dissipation at TA = 25°C (5) ESD Susceptibility (6) 500 mW Human Body Model 2500V Machine Model 150V N packages (10 seconds) Soldering Information SOIC Package 260°C Vapor Phase (60 seconds) 215°C Infrared (15 seconds) 220°C −40°C to +150°C Storage Temperature (1) (2) (3) (4) (5) (6) All voltages are measured with respect to GND, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV+), the current at that pin should be limited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given In the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150°C. The typical thermal resistance (θJA) of these Paris when board mounted can be found in the following Power Dissipation table: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Operating Ratings (1) (2) TMIN ≤ TA ≤ TMAX Operating Temperature Range −40°C ≤ TA ≤ +85°C Supply Voltage (V+ = AV+ = DV+) +4.5V to +5.5V VREF+ AV+ +50 mV to −50 mV VREF− AV+ +50 mV to −50 mV +0.5V to V+ VREF (VREF+–VREF−) (1) (2) 4 Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics table. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND, unless otherwise specified. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Electrical Characteristics The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C. (1) (2) (3) (4) Parameter Test Conditions Typ (5) Limits (6) Units (Limits) SIGNED STATIC CONVERTER CHARACTERISTICS 10 + Sign Bits TUE Resolution with No Missing Codes Total Unadjusted Error (7) ±2.0 LSB (max) INL Positive and Negative Integral Linearity Error ±1.25 LSB (max) Positive and Negative Full-Scale Error ±1.5 LSB (max) Offset Error Offset Error Power Supply Sensitivity V+ = +5.0V ±10% + Full-Scale Error − Full-Scale Error DC Common Mode Error VIN+ = VIN− = VIN where 5.0V ≥ VIN ≥ 0V (8) Multiplexer Chan to Chan Matching ±1.5 LSB (max) ±0.2 ±1.0 LSB (max) ±0.2 ±1.0 LSB (max) ±0.1 ±0.75 LSB (max) ±0.1 ±0.33 LSB (max) ±0.1 LSB UNSIGNED STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 10 Bits TUE Total Unadjusted Error (7) VREF+ = 4.096V ±0.75 INL Integral Linearity Error VREF+ = 4.096V ±0.50 Full-Scale Error VREF+ = 4.096V ±1.25 LSB (max) Offset Error VREF+ = 4.096V ±1.25 LSB (max) + LSB LSB Offset Error V = +5.0V ±10% ±0.1 LSB Full-Scale Error VREF+ = 4.096V ±0.1 LSB DC Common Mode Error (8) VIN+ = VIN− = VIN where +5.0V ≥ VIN ≥ 0V ±0.1 LSB Multiplexer Channel to Channel Matching VREF+ = 4.096V ±0.1 LSB Power Supply Sensitivity DYNAMIC SIGNED CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus Distortion Ratio VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz 67 dB ENOB Effective Number of Bits VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz 10.8 Bits THD Total Harmonic Distortion VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz −78 dB IMD Intermodulation Distortion VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz −85 dB Full-Power Bandwidth VIN = 4.85 VPP, where S/(N + D) Decreases 3 dB 380 kHz Multiplexer Chan to Chan Crosstalk fIN = 15 kHz −80 dB (1) (2) (3) (4) (5) (6) (7) (8) Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V+ supply. Be careful during testing at low V+ levels (+4.5V), as high level analog inputs (+5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. If AV+ and DV+ are minimum (4.5 VDC) and full scale must be ≤+4.55 VDC. See Figure 6 No connection exists between AV+ and DV+ on the chip.To ensure accuracy, it is required that the AV+ and DV+ be connected together to a power supply with separate bypass filter at each V+ pin. One LSB is referenced to 10 bits of resolution. All the timing specifications are tested at the TTL logic levels, VIL = 0.8V for a falling edge and VIH = 2.0V for a rising. TRl-STATE voltage level is forced to 1.4V. Typicals are at TJ = TA = 25°C and represent most likely parametric norm. Tested limits are ensured to AOQL (Average Outgoing Quality Level). Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors. The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 5 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.(1)(2)(3)(4) Parameter Test Conditions Typ (5) Limits (6) Units (Limits) DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC S/(N+D) Signal-to-Noise Plus Distortion Ratio VREF+ = 4.096V, VIN = 4.0 VPP, and fIN =1 kHz to 15 kHz 60 dB ENOB Effective Bits VREF+ = 4.096V, VIN = 4.0 VPP, and fIN = 1 kHz to 15 kHz 9.8 Bits THD Total Harmonic Distortion VREF+ = 4.096V, VIN = 4.0 VPP, and fIN = 1 kHz to 15 kHz −70 dB IMD Intermodulation Distortion VREF+ = 4.096V, VIN = 4.0 VPP, and fIN = 1 kHz to 15 kHz −73 dB Full-Power Bandwidth VIN = 4.0 VPP, VREF+ = 4.096V, where S/(N+D) decreases 3 dB 380 kHz Multiplexer Chan to Chan Crosstalk fIN = 15 kHz, VREF+ = 4.096V −80 dB REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS 7 Reference Input Resistance CREF Reference Input Capacitance MUX Input Capacitance Off Channel Leakage Current On Channel Leakage Current kΩ(min) 9.5 kΩ(max) −50 AV+ + 50mV mV (min) (max) 70 MUX Input Voltage CIM kΩ 5.0 pF 47 (9) (9) pF On Channel = 5V and Off Channel = 0V −0.4 −3.0 μA (max) On Channel = 0V and Off Channel = 5V 0.4 3.0 μA (max) On Channel = 5V and Off Channel = 0V 0.4 3.0 μA (max) On Channel = 0V and Off Channel = 5V −0.4 −3.0 μA (max) 2.5V ±0.5% 2.5V ±2% V (max) REFERENCE CHARACTERISTICS VREFOut Reference Output Voltage ΔVREF/Δ T VREFOut Temperature Coefficient ΔVREF/ΔI Load Regulation, Sourcing 0 mA ≤ IL ≤ +4 mA ±0.003 ±0.05 %/mA (max) Load Regulation, Sinking 0 mA ≤ IL ≤ −1 mA ±0.2 ±0.6 %/mA (max) Line Regulation 5V ±10% ±0.3 ±2.5 mV (max) Short Circuit Current VREFOut = 0V 13 22 mA (max) Noise Voltage 10 Hz to 10 kHz, CL = 100 μF 5 μV ±120 ppm/kHr 100 ms L ΔVREF/ΔI L ISC ±40 ΔVREF/Δt Long-term Stability tSU (9) 6 CL = 100 μF Start-Up Time ppm/°C Channel leakage current is measured after the channel selection. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.(1)(2)(3)(4) Parameter Test Conditions Typ (5) Limits (6) Units (Limits) DIGITAL AND DC CHARACTERISTICS VIN(1) Logical “1” Input Voltage V+ = 5.5V 2.0 V (min) VIN(0) Logical “0” Input Voltage V+ = 4.5V 0.8 V (max) IIN(1) Logical “1” Input Current VIN = 5.0V 0.005 +2.5 μA (max) IIN(0) Logical “0” Input Current VIN = 0V −0.005 −2.5 μA (max) V = 4.5V, IOUT = −360 μA 2.4 V (min) V+ = 4.5V, IOUT = −10 μA 4.5 V (min) + VOUT(1) VOUT(0) IOUT Logical “1” Output Voltage Logical “0” Output Voltage TRI-STATE Output Current + V = 4.5V, IOUT = 1.6 mA VOUT = 0V VOUT = 5V + 0.4 V (min) −0.1 −3.0 μA (max) +0.1 +3.0 μA (max) +ISC Output Short Circuit Source Current VOUT = 0V, V = 4.5V −30 −15 mA(min) −ISC Output Short Circuit Sink Current VOUT= V+ = 4.5V 30 15 mA (min) CS = HIGH, Power Up 0.9 1.3 mA (max) CS = HIGH, Power Down 0.2 0.4 mA (max) CS = HIGH, Power Down, and CLK Off 0.5 50 μA (max) CS = HIGH, Power Up CS = HIGH, Power Down 2.7 3 6.0 15 mA (max) μA (max) 0.6 mA (max) 2.5 MHz (max) kHz (min) 40 60 %(min) %(max) 12 12 Clock Cycles 5 5 μs (max) 4.5 4.5 Clock Cycles 2 2 μs (max) ID+ Digital Supply Current (10) (10) IA+ Analog Supply Current IREF Reference Input Current VREF+ = +2.5V and CS = HIGH, Power Up AC CHARACTERISTICS fCLK 3.0 5 Clock Frequency Clock Duty Cycle tC tA Conversion Time Acquisition Time 14 30 ns (min) (1 tCLK − 14 ns) (1 tCLK − 30 ns) (max) DI Set-Up Time, Set-Up Time from Data Valid on DI to Rising Edge of Clock 16 25 ns (min) tHDI DI Hold Time, Hold Time of DI Data from Rising Edge of Clock to Data not Valid on DI 2 25 ns (min) tAT DO Access Time from Rising Edge of CLK When CS is “Low” during a Conversion 30 50 ns (min) tAC DO or SARS Access Time from CS , Delay from Falling Edge of CS to Data Valid on DO or SARS 30 70 ns (max) tDSARS Delay from Rising Edge of Clock to Falling Edge of SARS when CS is “Low” 100 200 ns (max) tSCS CS Set-Up Time, Set-Up Time from Falling Edge of CS to Rising Edge of Clock tSDI (10) The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low = 0V and logic High = 5V). TTL levels increase the current, during power down, to about 300 μA. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 7 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.(1)(2)(3)(4) Parameter Test Conditions Typ (5) Limits (6) Units (Limits) tHDO DO Hold Time, Hold Time of Data on DO after Falling Edge of Clock 20 35 ns (max) tAD DO Access Time from Clock, Delay from Falling Edge of Clock to Valid Data of DO 40 80 ns (max) t1H, t0H Delay from Rising Edge of CS to DO or SARS TRI-STATE 40 50 ns (max) tDCS Delay from Falling Edge of Clock to Falling Edge of CS 20 30 ns (min) tCS(H) CS “HIGH” Time for A/D Reset after Reading of Conversion Result 1 CLK 1 CLK cycle (min) tCS(L) ADC10731 Minimum CS “Low” Time to Start a Conversion 1 CLK 1 CLK cycle (min) tSC Time from End of Conversion to CS Going “Low” 5 CLK 5 CLK cycle (min) tPD Delay from Power-Down command to 10% of Operating Current 1 tPC Delay from Power-Up Command to Ready to Start a New Conversion 10 CIN Capacitance of Logic Inputs 7 pF COUT Capacitance of Logic Outputs 12 pF μs μs Figure 6. Power Dissipation 8 Part Number Thermal Resistance Package Type ADC10731CIWM 90°C/W M16B ADC10732CIWM 80°C/W M20B ADC10734CIMSA 134°C/W MSA20 ADC10734CIWM 80°C/W M20B ADC10738CIWM 75°C/W M24B Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Figure 7. Transfer Characteristics Figure 8. Simplified Error Curve vs Output Code Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 9 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Test Circuit Figure 9. Leakage Current Test Circuit 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Typical Performance Characteristics Analog Supply Current (IA+) vs. Temperature Analog Supply Current (IA+) vs. Clock Frequency Figure 10. Figure 11. Digital Supply Current (ID+) vs. Temperature Digital Supply Current (ID+) vs. Clock Frequency Figure 12. Figure 13. Offset Error vs. Reference Voltage Offset Error vs. Temperature Figure 14. Figure 15. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 11 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 12 Linearity Error vs. Clock Frequency Linearity Error vs. Reference Voltage Figure 16. Figure 17. Linearity Error vs. Temperature 10-Bit Unsigned Signal-to-Noise + THD Ratio vs. Input Signal Level Figure 18. Figure 19. Spectral Response with 34 kHz Sine Wave Power Bandwidth Response with 380 kHz Sine Wave Figure 20. Figure 21. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Typical Reference Performance Characteristics Load Regulation Line Regulation Figure 22. Figure 23. Output Drift vs. Temperature (3 Typical Parts) Available Output Current vs. Supply Voltage Figure 24. Figure 25. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 13 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com TRI-STATE TEST CIRCUITS AND WAVEFORMS Figure 26. Figure 27. Figure 28. Figure 29. Timing Diagrams Figure 30. DI Timing 14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Figure 31. DO Timing Figure 32. Delayed DO Timing Figure 33. Hardware Power Up/Down Sequence Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 15 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Figure 34. Software Power Up/Down Sequence Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is invalid. The ADC10731 is obsolete. Information shown for reference only. Figure 35. ADC10731 CS Low during Conversion 16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10732 and the ADC10734 are obsolete. Information shown for reference only. Figure 36. ADC10732, ADC10734 and ADC10738 CS Low during Conversion Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10731 is obsolete. Information shown for reference only. Figure 37. ADC10731 Using CS to Delay Output of Data after a Conversion has Completed Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 17 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10732 and the ADC10734 are obsolete. Information shown for reference only. Figure 38. ADC10732, ADC10734 and ADC10738 Using CS to Delay Output of Data After a Conversion has Completed 18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Table 2. ADC10738 Multiplexer Address Assignment MUX Address MA0 MA1 MA2 Channel Number MA3 MA4 PU SING/ DIFF ODD/ SIGN SEL1 SEL0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 X X X X CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 MUX MODE COM − + − + − + − + Single-Ended − + − + − + − + − + + − + − − + − − + Differential + − + − + Power Down (All Channels Disconnected) Table 3. ADC10734 (Obsolete) Multiplexer Address Assignment MUX Address MA0 PU MA1 MA2 SING/ DIFF ODD/ SIGN Channel Number MA3 MA4 SEL1 SEL0 1 1 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 X X X X CH0 CH1 CH2 CH3 MUX MODE COM − + − + − + − + + − − + Single-Ended + − − + Differential Power Down (All Channels Disconnected) Table 4. ADC10732 (Obsolete) Multiplexer Address Assignment MUX Address Channel Number MA0 MA1 MA2 MA3 MA4 PU SlNG/DIFF ODD/SIGN SEL1 SEL0 1 1 0 0 0 1 1 1 0 0 1 0 0 0 0 + − 1 0 1 0 0 0 X X X X Copyright © 1999–2013, Texas Instruments Incorporated CH0 CH1 + COM MUX MODE − Single-Ended − + − Differential + Power Down (All Channels Disconnected) Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 19 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS The ADC10731, ADC10732 and ADC10734 are obsolete and discussed here for reference only. The ADC10731/2/4/8 use successive approximation to digitize an analog input voltage. The DAC portion of the A/D converters uses a capacitive array and a resistive ladder structure. The structure of the DAC allows a very simple switching scheme to provide a versatile analog input multiplexer. This structure also provides a sample/hold. The ADC10731/2/4/8 have a 2.5V CMOS bandgap reference. The serial digital I/O interfaces to MICROWIRE and MICROWIRE+. DIGITAL INTERFACE There are two modes of operation. The fastest throughput rate is obtained when CS is kept low during a conversion. The timing diagrams in Figure 35 and Figure 36 show the operation of the devices in this mode. CS must be taken high for at least tCS(H) (1 CLK) between conversions. This is necessary to reset the internal logic. Figure 37 and Figure 38 show the operation of the devices when CS is taken high while the ADC10731/2/4/8 is converting. CS may be taken high during the conversion and kept high indefinitely to delay the output data. This mode simplifies the interface to other devices while the ADC10731/2/4/8 is busy converting. Getting Started with a Conversion The ADC10731/2/4/8 need to be initialized after the power supply voltage is applied. If CS is low when the supply voltage is applied then CS needs to be taken high for at least tCS(H)(1 clock period). The data output after the first conversion is not valid. Software and Hardware Power Up/Down These devices have the capability of software or hardware power down. Figure 33 and Figure 34 show the timing diagrams for hardware and software power up/down. In the case of hardware power down note that CS needs to be high for tPC after PD is taken low. When PD is high the device is powered down. The total quiescent current, when powered down, is typically 200 μA with the clock at 2.5 MHz and 3 μA with the clock off. The actual voltage level applied to a digital input will effect the power consumption of the device during power down. CMOS logic levels will give the least amount of current drain (3 μA). TTL logic levels will increase the total current drain to 200 μA. These devices have resistive reference ladders which draw 600 μA with a 2.5V reference voltage. The internal band gap reference voltage shuts down when power down is activated. If an external reference voltage is used, it will have to be shut down to minimize the total current drain of the device. ARCHITECTURE Before a conversion is started, during the analog input sampling period, (tA), the sampled data comparator is zeroed. As the comparator is being zeroed the channel assigned to be the positive input is connected to the A/D's input capacitor. (The assignment procedure is explained in the Table 1 section.) This charges the input 32C capacitor of the DAC to the positive analog input voltage. The switches shown in the DAC portion of Figure 39 are set for this zeroing/acquisition period. The voltage at the input and output of the comparator are at equilibrium at this time. When the conversion is started, the comparator feedback switches are opened and the 32C input capacitor is then switched to the assigned negative input voltage. When the comparator feedback switch opens, a fixed amount of charge is trapped on the common plates of the capacitors. The voltage at the input of the comparator moves away from equilibrium when the 32C capacitor is switched to the assigned negative input voltage, causing the output of the comparator to go high (“1”) or low (“0”). The SAR next goes through an algorithm, controlled by the output state of the comparator, that redistributes the charge on the capacitor array by switching the voltage on one side of the capacitors in the array. The objective of the SAR algorithm is to return the voltage at the input of the comparator as close as possible to equilibrium. The switch position information at the completion of the successive approximation routine is a direct representation of the digital output. This data is then available to be shifted on the DO pin. 20 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Figure 39. Detailed Diagram of the ADC10738 DAC and Analog Multiplexer Stages APPLICATIONS INFORMATION Multiplexer Configuration The design of these converters utilizes a sampled-data comparator structure, which allows a differential analog input to be converted by the successive approximation routine. The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal. The polarity of each input terminal or pair of input terminals being converted indicates which line the converter expects to be the most positive. A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be software configured into three modes: differential, single-ended, or pseudo-differential. Analog Input Multiplexer Options illustrates the three modes using the 4-channel MUX of the ADC10734. The eight inputs of the ADC10738 can also be configured in any of the three modes. The single-ended mode has CH0–CH3 assigned as the positive input with COM serving as the negative input. In the differential mode, the ADC10734 channel inputs are grouped in pairs, CH0 with CH1 and CH2 with CH3. The polarity assignment of each channel in the pair is interchangeable. Finally, in the pseudo-differential mode CH0–CH3 are positive inputs referred to COM which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the input common-mode range of the converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground-referred inputs and true differential inputs as well as signals referred to a specific voltage. The analog input voltages for each channel can range from 50 mV below GND to 50 mV above V+ = DV+ = AV+ without degrading conversion accuracy. If the voltage on an unselected channel exceeds these limits it may corrupt the reading of the selected channel. Reference Considerations The voltage difference between the VREF+ and VREF− inputs defines the analog input voltage span (the difference between VIN(Max) and VIN(Min)) over which 1023 positive and 1024 negative possible output codes apply. The value of the voltage on the VREF+ or VREF− inputs can be anywhere between AV+ + 50 mV and −50 mV, so long as VREF+ is greater than VREF−. The ADC10731/2/4/8 can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable of driving the minimum reference input resistance of 5 kΩ. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 21 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com The internal 2.5V bandgap reference in the ADC10731/2/4/8 is available as an output on the VREFOut pin. To ensure optimum performance this output needs to be bypassed to ground with 100 μF aluminum electrolytic or tantalum capacitor. The reference output can be unstable with capacitive loads greater than 100 pF and less than 100 μF. Any capacitive loading less than 100 pF and greater than 100 μF will not cause oscillation. Lower output noise can be obtained by increasing the output capacitance. A 100 μF capacitor will yield a typical noise floor of (1) The pseudo-differential and differential multiplexer modes allow for more flexibility in the analog input voltage range since the “zero” reference voltage is set by the actual voltage applied to the assigned negative input pin. In a ratiometric system (Figure 40), the analog input voltage is proportional to the voltage used for the A/D reference. This voltage may also be the system power supply, so VREF+ can also be tied to AV+. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy (Figure 41), where the analog input varies between very specific voltage limits, the reference pin can be biased with a time- and temperature-stable voltage source that has excellent initial accuracy. The LM4040, LM4041 and LM185 references are suitable for use with the ADC10731/2/4/8. The minimum value of VREF (VREF = VREF+–VREF−) can be quite small (see Typical Performance Characteristics) to allow direct conversion of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/1024). The Analog Inputs Due to the sampling nature of the analog inputs, at the clock edges short duration spikes of current will be seen on the selected assigned negative input. Input bypass capacitors should not be used if the source resistance is greater than 1 kΩ since they will average the AC current and cause an effective DC current to flow through the analog input source resistance. An op amp RC active lowpass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. Bypass capacitors may be used when the source impedance is very low without any degradation in performance. In a true differential input stage, a signal that is common to both “+” and “−” inputs is canceled. For the ADC10731/2/4/8, the positive input of a selected channel pair is only sampled once before the start of a conversion during the acquisition time (tA). The negative input needs to be stable during the complete conversion sequence because it is sampled before each decision in the SAR sequence. Therefore, any AC common-mode signal present on the analog inputs will not be completely canceled and will cause some conversion errors. For a sinusoid common-mode signal this error is: VERROR(max) = VPEAK (2 π fCM) (tC) (2) where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value, and tC is the A/D's conversion time (tC = 12/fCLK). For example, for a 60 Hz common-mode signal to generate a ¼ LSB error (0.61 mV) with a 4.8 μs conversion time, its peak value would have to be approximately 337 mV. 22 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Analog Input Multiplexer Options 4 Single-Ended 2 Differential 4 Psuedo-Differential 2 Single-Ended and 1 Differential Different Reference Configurations Figure 40. Ratiometric Using the Internal Reference Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 23 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com Figure 41. Absolute Using a 4.096V Span Optional Adjustments Zero Error The zero error of the A/D converter relates to the location of the first riser of the transfer function (see Figure 7 Figure 8) and can be measured by grounding the minus input and applying a small magnitude voltage to the plus input. Zero error is the difference between actual DC input voltage which is necessary to just cause an output digital code transition from 000 0000 0000 to 000 0000 0001 and the ideal ½ LSB value (½ LSB = 1.22 mV for VREF = + 2.500V). The zero error of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(Min), is not ground, the effective “zero” voltage can be adjusted to a convenient value. The converter can be made to output an all zeros digital code for this minimum input voltage by biasing any minus input to VIN(Min). This is useful for either the differential or pseudo-differential input channel configurations. Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 1½ LSB down from the desired analog full-scale voltage range and then adjusting the VREF voltage (VREF = VREF+– VREF−) for a digital output code changing from 011 1111 1110 to 011 1111 1111. In bipolar signed operation this only adjusts the positive full scale error. Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A plus input voltage which equals this desired zero reference plus ½ LSB is applied to selected plus input and the zero reference voltage at the corresponding minus input should then be adjusted to just obtain the 000 0000 0000 to 000 0000 0001 code transition. The full-scale adjustment should be made [with the proper minus input voltage applied] by forcing a voltage to the plus input which is given by: (3) where VMAX equals the high end of the analog input range, VMIN equals the low end (the offset zero) of the analog range. Both VMAX and VMIN are ground referred. The VREF (VREF = VREF+ − VREF−) voltage is then adjusted to provide a code change from 011 1111 1110 to 011 1111 1111. Note, when using a pseudo-differential or differential multiplexer mode where VREF+ and VREF− are placed within the V+ and GND range, the individual values of VREF and VREF− do not matter, only the difference sets the analog input voltage span. This completes the adjustment procedure. 24 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 The Input Sample and Hold The ADC10731/2/4/8's sample/hold capacitor is implemented in the capacitor array. After the channel address is loaded, the array is switched to sample the selected positive analog input. The sampling period for the assigned positive input is maintained for the duration of the acquisition time (tA) 4.5 clock cycles. This acquisition window of 4.5 clock cycles is available to allow the voltage on the capacitor array to settle to the positive analog input voltage. Any change in the analog voltage on a selected positive input before or after the acquisition window will not effect the A/D conversion result. In the simplest case, the array's acquisition time is determined by the RON (3 kΩ) of the multiplexer switches, the stray input capacitance CS1 (3.5 pF) and the total array (CL) and stray (CS2) capacitance (48 pF). For a large source resistance the analog input can be modeled as an RC network as shown in Figure 42. The values shown yield an acquisition time of about 1.1 μs for 10-bit unipolar or 10-bit plus sign accuracy with a zero-to-full-scale change in the input voltage. External source resistance and capacitance will lengthen the acquisition time and should be accounted for. Slowing the clock will lengthen the acquisition time, thereby allowing a larger external source resistance. Figure 42. Analog Input Model The signal-to-noise ratio of an ideal A/D is the ratio of the RMS value of the full scale input signal amplitude to the value of the total error amplitude (including noise) caused by the transfer function of the ideal A/D. An ideal 10-bit plus sign A/D converter with a total unadjusted error of 0 LSB would have a signal-to-(noise + distortion) ratio of about 68 dB, which can be derived from the equation: S/(N + D) = 6.02(n) + 1.76 (4) where S/(N + D) is in dB and n is the number of bits. Note: Diodes are 1N914. Note: The protection diodes should be able to withstand the output current of the op amp under current limit. Figure 43. Protecting the Analog Inputs Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 25 ADC10731, ADC10732, ADC10734, ADC10738 SNAS081D – MAY 1999 – REVISED MARCH 2013 www.ti.com *1% resistors Figure 44. Zero-Shift and Span-Adjust for Signed or Unsigned, Single-Ended Multiplexer Assignment, Signed Analog Input Range of 0.5V ≤ VIN ≤ 4.5V 26 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 26 Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 27 PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC10738CIWM/NOPB ACTIVE SOIC DW 24 30 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC10738 CIWM ADC10738CIWMX/NOPB ACTIVE SOIC DW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC10738 CIWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC10738CIWMX/NOPB Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.9 3.2 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10738CIWMX/NOPB SOIC DW 24 1000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated