ADC108S102
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SNAS336B – SEPTEMBER 2005 – REVISED MARCH 2013
ADC108S102 8-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter
Check for Samples: ADC108S102
FEATURES
DESCRIPTION
•
•
•
•
•
The ADC108S102 is a low-power, eight-channel
CMOS 10-bit analog-to-digital converter specified for
conversion throughput rates of 500 kSPS to 1 MSPS.
The converter is based on a successiveapproximation register architecture with an internal
track-and-hold circuit. It can be configured to accept
up to eight input signals at inputs IN0 through IN7.
1
23
Eight Input Channels
Variable Power Management
Independent Analog and Digital Supplies
SPI/QSPI/MICROWIRE/DSP Compatible
Packaged in 16-Lead TSSOP
KEY SPECIFICATIONS
•
•
•
•
Conversion Rate: 500 kSPS to 1 MSPS
DNL (VA = VD = 5.0 V): ±0.5 LSB (max)
INL (VA = VD = 5.0 V): ±0.5 LSB (max)
Power Consumption:
– 3V Supply 2.1 mW (typ)
– 5V Supply 9.4 mW (typ)
APPLICATIONS
•
•
•
•
•
Automotive Navigation
Portable Systems
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
The output serial data is straight binary and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE, and many common DSP
serial interfaces.
The ADC108S102 may be operated with independent
analog and digital supplies. The analog supply (VA)
can range from +2.7V to +5.25V, and the digital
supply (VD) can range from +2.7V to VA. Normal
power consumption using a +3V or +5V supply is 2.1
mW and 9.4 mW, respectively. The power-down
feature reduces the power consumption to 0.09 µW
using a +3V supply and 0.30 µW using a +5V supply.
The ADC108S102 is packaged in a 16-lead TSSOP
package. Operation over the extended industrial
temperature range of −40°C to +105°C is ensured.
Connection Diagram
CS
1
16
SCLK
VA
2
15
DOUT
AGND
3
14
DIN
IN0
4
13
VD
IN1
5
12
DGND
IN2
6
11
IN7
IN3
7
10
IN6
IN4
8
9
IN5
ADC108S102
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc..
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
ADC108S102
SNAS336B – SEPTEMBER 2005 – REVISED MARCH 2013
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Block Diagram
IN0
.
.
.
T/H
MUX
10-BIT
SUCCESSIVE
APPROXIMATION
ADC
VA
AGND
AGND
IN7
VD
SCLK
ADC108S102
CONTROL
LOGIC
CS
DIN
DOUT
DGND
PIN DESCRIPTIONS and EQUIVALENT CIRCUITS
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
4 - 11
IN0 to IN7
Analog inputs. These signals can range from 0V to VREF.
DIGITAL I/O
16
SCLK
Digital clock input. The specified performance range of frequencies
for this input is 8 MHz to 16 MHz. This clock directly controls the
conversion and readout processes.
15
DOUT
Digital data output. The output samples are clocked out of this pin on
the falling edges of the SCLK pin.
14
DIN
Digital data input. The ADC108S102's Control Register is loaded
through this pin on rising edges of the SCLK pin.
1
CS
Chip select. On the falling edge of CS, a conversion process begins.
Conversions continue as long as CS is held low.
2
VA
Positive analog supply pin. This voltage is also used as the
reference voltage. This pin should be connected to a quiet +2.7V to
+5.25V source and bypassed to GND with 1 µF and 0.1 µF
monolithic ceramic capacitors located within 1 cm of the power pin.
13
VD
Positive digital supply pin. This pin should be connected to a +2.7V
to VA supply, and bypassed to GND with a 0.1 µF monolithic ceramic
capacitor located within 1 cm of the power pin.
POWER SUPPLY
2
3
AGND
The ground return for the analog supply and signals.
12
DGND
The ground return for the digital supply and signals.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Analog Supply Voltage VA
−0.3V to 6.5V
Digital Supply Voltage VD
−0.3V to VA + 0.3V, max 6.5V
−0.3V to VA +0.3V
Voltage on Any Pin to GND
Input Current at Any Pin
(3)
±10 mA
Package Input Current (3)
±20 mA
Power Dissipation at TA = 25°C
ESD Susceptibility
See
(5)
Human Body Model
(4)
2500V
Machine Model
250V
For soldering specifications, see product folder at http://www.ti.com/lit/SNOA549
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. In the 16-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum
operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12
mW. The values for maximum power dissipation listed above will be reached only when the ADC108S102 is operated in a severe fault
condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms
Operating Ratings (1) (2)
−40°C ≤ TA ≤ +105°C
Operating Temperature
VA Supply Voltage
+2.7V to +5.25V
VD Supply Voltage
+2.7V to VA
Digital Input Voltage
0V to VA
Analog Input Voltage
0V to VA
Clock Frequency
(1)
(2)
8 MHz to 16 MHz
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package
θJA
16-lead TSSOP on 4-layer, 2 oz. PCB
96°C / W
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ADC108S102 Converter Electrical Characteristics (1)
The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz,
fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX:
all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
(2)
Units
10
Bits
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non-Linearity (End Point
Method)
±0.2
±0.5
LSB (max)
DNL
Differential Non-Linearity
±0.2
±0.5
LSB (max)
VOFF
Offset Error
+0.3
±0.7
LSB (max)
OEM
Offset Error Match
±0.07
±0.4
LSB (max)
FSE
Full Scale Error
+0.2
±0.4
LSB (max)
FSEM
Full Scale Error Match
±0.07
±0.4
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth (−3dB)
SINAD
Signal-to-Noise Plus Distortion Ratio
fIN = 40.2 kHz, −0.02 dBFS
61.8
61.3
SNR
Signal-to-Noise Ratio
fIN = 40.2 kHz, −0.02 dBFS
61.8
61.4
dB (min)
THD
Total Harmonic Distortion
fIN = 40.2 kHz, −0.02 dBFS
−87.0
−73.8
dB (max)
SFDR
Spurious-Free Dynamic Range
fIN = 40.2 kHz, −0.02 dBFS
83.1
76.0
dB (min)
ENOB
Effective Number of Bits
fIN = 40.2 kHz
9.98
9.89
Bits (min)
ISO
Channel-to-Channel Isolation
fIN = 20 kHz
79.7
dB
Intermodulation Distortion, Second
Order Terms
fa = 19.5 kHz, fb = 20.5 kHz
−83.9
dB
Intermodulation Distortion, Third Order
Terms
fa = 19.5 kHz, fb = 20.5 kHz
−82.4
dB
IMD
8
MHz
dB (min)
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
IDCL
DC Leakage Current
CINA
Input Capacitance
0 to VA
V
±1
µA (max)
Track Mode
33
pF
Hold Mode
3
pF
DIGITAL INPUT CHARACTERISTICS
VA = VD = +2.7V to +3.6V
2.1
VA = VD = +4.75V to +5.25V
2.4
V (min)
VA = VD = +2.7V to +5.25V
0.8
V (max)
±0.01
±1
µA (max)
2
4
pF (max)
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
VIN = 0V or VD
CIND
Digital Input Capacitance
V (min)
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
ISOURCE = 200 µA
VOL
Output Low Voltage
ISINK = 200 µA to 1.0 mA,
IOZH, IOZL
Hi-Impedance Output Leakage Current
COUT
Hi-Impedance Output Capacitance (1)
2
Output Coding
(1)
(2)
4
VD − 0.5
V (min)
0.4
V (max)
±1
µA (max)
4
pF (max)
Straight (Natural) Binary
Data sheet min/max specification limits are specified by design, test, or statistical analysis.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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ADC108S102 Converter Electrical Characteristics(1) (continued)
The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz,
fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX:
all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
(2)
Units
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
VA, VD
Analog and Digital Supply Voltages
Total Supply Current
Normal Mode ( CS low)
IA + ID
Total Supply Current
Shutdown Mode (CS high)
Power Consumption
Normal Mode ( CS low)
PC
Power Consumption
Shutdown Mode (CS high)
VA ≥ VD
2.7
V (min)
5.25
V (max)
VA = VD = +2.7V to +3.6V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
0.70
1.4
mA (max)
VA = VD = +4.75V to +5.25V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
1.88
2.7
mA (max)
VA = VD = +2.7V to +3.6V,
fSCLK = 0 kSPS
30
nA
VA = VD = +4.75V to +5.25V,
fSCLK = 0 kSPS
60
nA
VA = VD = +3.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
2.1
4.2
mW (max)
VA = VD = +5.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
9.4
13.6
mW (max)
VA = VD = +3.0V
fSCLK = 0 kSPS
0.09
µW
VA = VD = +5.0V
fSCLK = 0 kSPS
0.30
µW
AC ELECTRICAL CHARACTERISTICS
fSCLKMIN
Minimum Clock Frequency
fSCLK
Maximum Clock Frequency
fS
Sample Rate
Continuous Mode
tCONVERT
Conversion (Hold) Time
DC
SCLK Duty Cycle
tACQ
Acquisition (Track) Time
Throughput Time
tAD
0.8
50
MHz (min)
MHz (max)
500
kSPS (min)
1
MSPS (max)
13
SCLK cycles
30
40
% (min)
70
60
% (max)
3
SCLK cycles
16
SCLK cycles
Acquisition Time + Conversion Time
Aperture Delay
8
16
4
ns
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ADC108S102 Timing Specifications
The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE =
500 kSPS to 1 MSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
6
Conditions
Typical
Limits
(1)
Units
tCSH
CS Hold Time after SCLK Rising Edge
0
10
ns (min)
tCSS
CS Setup Time prior to SCLK Rising
Edge
5
10
ns (min)
tEN
CS Falling Edge to DOUT enabled
5
30
ns (max)
tDACC
DOUT Access Time after SCLK Falling
Edge
17
27
ns (max)
tDHLD
DOUT Hold Time after SCLK Falling
Edge
4
tDS
DIN Setup Time prior to SCLK Rising
Edge
3
10
ns (min)
tDH
DIN Hold Time after SCLK Rising Edge
3
10
ns (min)
tCH
SCLK High Time
0.4 x tSCLK
ns (min)
tCL
SCLK Low Time
0.4 x tSCLK
ns (min)
tDIS
(1)
Parameter
CS Rising Edge to DOUT HighImpedance
ns (typ)
DOUT falling
2.4
20
ns (max)
DOUT rising
0.9
20
ns (max)
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Timing Diagrams
Power
Down
Power Up
Track
Power Up
Hold
Track
Hold
CS
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
SCLK
Control register
DIN
ADD2
DOUT
ADD1
ADD0
ADD2
DB9
FOUR ZEROS
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADD1
ADD0
DB9
SIX ZEROS
DB8
DB7
Figure 1. ADC108S102 Operational Timing Diagram
CS
tCONVERT
tACQ
tCH
SCLK
1
2
3
5
DB9
FOUR ZEROS
DOUT
6
7
14
8
15
16
tDACC
tDHLD
tCL
tEN
DB8
DB7
DB6
tDIS
B1
DB0
TWO ZEROS
tDH
tDS
DIN
4
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Figure 2. ADC108S102 Serial Timing Diagram
SCLK
tCSS
CS
tCSH
CS
Figure 3. SCLK and CS Timing Parameters
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Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another
channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-toChannel Isolation, except for the sign of the data.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the
power in either the second or the third order intermodulation products to the sum of the power in both of the
original frequencies. Second order products are fa ± fb, where fa and fb are the two sine wave input frequencies.
Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC108S102 is
ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum
that is not present at the input, including harmonics but excluding d.c.
8
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TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic
components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated
as
THD = 20 x log10
A f22 +
+ A f62
A f12
where
•
Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5
harmonic frequencies.
(1)
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion time.
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Typical Performance Characteristics
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
10
DNL
DNL
Figure 4.
Figure 5.
INL
INL
Figure 6.
Figure 7.
DNL vs. Supply
INL vs. Supply
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR vs. Supply
THD vs. Supply
Figure 10.
Figure 11.
ENOB vs. Supply
DNL vs. VD with VA = 5.0 V
Figure 12.
Figure 13.
INL vs. VD with VA = 5.0 V
DNL vs. SCLK Duty Cycle
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
12
INL vs. SCLK Duty Cycle
SNR vs. SCLK Duty Cycle
Figure 16.
Figure 17.
THD vs. SCLK Duty Cycle
ENOB vs. SCLK Duty Cycle
Figure 18.
Figure 19.
DNL vs. SCLK
INL vs. SCLK
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR vs. SCLK
THD vs. SCLK
Figure 22.
Figure 23.
ENOB vs. SCLK
DNL vs. Temperature
Figure 24.
Figure 25.
INL vs. Temperature
SNR vs. Temperature
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
14
THD vs. Temperature
ENOB vs. Temperature
Figure 28.
Figure 29.
SNR vs. Input Frequency
THD vs. Input Frequency
Figure 30.
Figure 31.
ENOB vs. Input Frequency
Power Consumption vs. SCLK
Figure 32.
Figure 33.
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FUNCTIONAL DESCRIPTION
The ADC108S102 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter.
ADC108S102 OPERATION
Simplified schematics of the ADC108S102 in both track and hold operation are shown in Figure 34 and Figure 35
respectively. In Figure 34, the ADC108S102 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC108S102 is in this state for the first three SCLK cycles after CS is brought low.
Figure 35 shows the ADC108S102 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC108S102 is in this state for the last thirteen SCLK cycles
after CS is brought low.
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
IN7
SW2
+
-
CONTRO
L
LOGI
C
AGND
VA /2
Figure 34. ADC108S102 in Track Mode
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
IN7
SAMPLING
CAPACITOR
+
SW1
SW2
-
CONTROL
LOGIC
AGND
VA /2
Figure 35. ADC108S102 in Hold Mode
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SERIAL INTERFACE
An operational timing diagram and a serial interface timing diagram for the ADC108S102 are shown in the
Timing Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial
clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin,
where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC108S102's
Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros, falling edges 5 through 14 clock out the conversion result, MSB first, and falling edges 15 and
16 clock out trailing zeros. If there is more than one conversion in a frame (continuous conversion mode), the
ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter
the hold/convert mode on the N*16+4th falling edge of SCLK. "N" is an integer value.
The ADC108S102 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters
track mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 3
for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of
SCLK after the fall of CS. The control register is loaded with data indicating the input channel to be converted on
the subsequent conversion (see , Table 1, Table 2 , and Table 3).
The user does not need to incorporate a power-up delay or dummy conversions as the ADC108S102 is able to
acquire the input signal to full resolution in the first conversion immediately following power-up. The first
conversion result after power-up will be that of IN0.
Table 1. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Table 2. Control Register Bit Descriptions
Bit #:
Symbol:
Description
7, 6, 2, 1, 0
DONTC
Don't care. The values of these bits do not affect the device.
5
ADD2
4
ADD1
These three bits determine which input channel will be sampled and converted at the next
conversion cycle. The mapping between codes and channels is shown in Table 3.
3
ADD0
Table 3. Input Channel Selection
16
ADD2
ADD1
ADD0
Input Channel
0
0
0
IN0 (Default)
0
0
1
IN1
0
1
0
IN2
0
1
1
IN3
1
0
0
IN4
1
0
1
IN5
1
1
0
IN6
1
1
1
IN7
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ADC108S102 TRANSFER FUNCTION
The output format of the ADC108S102 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC108S102 is VA / 1024. The ideal transfer characteristic is shown
in Figure 36. The transition from an output code of 00 0000 0000 to a code of 00 0000 0001 is at 1/2 LSB, or a
voltage of VA / 2048. Other code transitions occur at steps of one LSB.
111...111
111...000
|
|
ADC CODE
111...110
1 LSB = VA / 1024
011...111
000...010
|
000...001
000...000
0V
+VA - 1.5LSB
0.5LSB
ANALOG INPUT
Figure 36. Ideal Transfer Characteristic
ANALOG INPUTS
An equivalent circuit for one of the ADC108S102's input channels is shown in Figure 37. Diodes D1 and D2
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going
beyond this range will cause the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 37 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the
ADC108S102 sampling capacitor, and is typically 30 pF. The ADC108S102 will deliver best performance when
driven by a low-impedance source (less than 100 ohms). This is especially important when using the
ADC108S102 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or lowpass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing
filters.
VA
D1
R1
C2
30 pF
VIN
C1
3 pF
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 37. Equivalent Input Circuit
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DIGITAL INPUTS AND OUTPUTS
The ADC108S102's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone
to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT)
operating range is controlled by VD. The output high voltage is VD - 0.5V (min) while the output low voltage is
0.4V (max).
Applications Information
TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 38. The split analog and digital supply pins are both powered in this
example by the Texas Instruments LP2950 low-dropout voltage regulator. The analog supply is bypassed with a
capacitor network located close to the ADC108S102. The digital supply is separated from the analog supply by
an isolation resistor and bypassed with additional capacitors. The ADC108S102 uses the analog supply (VA) as
its reference voltage, so it is very important that VA be kept as clean as possible. Due to the low power
requirements of the ADC108S102, it is also possible to use a precision reference as a power supply.
To minimize the error caused by the changing input capacitance of the ADC108S102, a capacitor is connected
from each input pin to ground. The capacitor, which is much larger than the input capacitance of the
ADC108S102 when in track mode, provides the current to quickly charge the sampling capacitor of the
ADC108S102. An isolation resistor is added to isolate the load capacitance from the input source.
51:
LP2950
0.1 PF
VD
22:
INPUT
0.1 PF
1.0 PF
VA
IN0
1 nF
.
.
.
1.0 PF
ADC108S102
IN7
5V
0.1 PF
1 PF
SCLK
CS
DIN
MICROPROCESSOR
DSP
DOUT
AGND
DGND
Figure 38. Typical Application Circuit
18
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POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this product: power supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
Power Supply Sequence
The ADC108S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital
supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, not even on a transient basis.
Therefore, VA must ramp up before or concurrently with VD.
Power Management
The ADC108S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with
one exception. If operating in continuous conversion mode, the ADC108S102 automatically enters power-down
mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent
conversion (see Figure 1).
In continuous conversion mode, the ADC108S102 can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC108S102 will perform conversions continuously as long as CS
is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical
specifications. The Power Consumption vs. SCLK curve in the Typical Performance Characteristics section
shows the typical power consumption of the ADC108S102. To calculate the power consumption (PC), simply
multiply the fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN), and add
the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as
shown in Figure 39.
PC =
tN
tN + tS
u PN +
tS
tN + tS
u PS
Figure 39. Power Consumption Equation
Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if
the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly
into the analog supply, causing greater performance degradation than would noise on the digital supply alone.
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will
dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise
in the substrate that will degrade noise performance if that current is large enough. The larger the output
capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog
channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance. Since the series resistor and the load
capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
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LAYOUT AND GROUNDING
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have
significant impact upon system noise performance. To avoid performance degradation of the ADC108S102 due
to supply noise, do not use the same supply for the ADC108S102 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes
should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be
placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal
chain that are connected to ground should be connected together with short traces and enter the analog ground
plane at a single, quiet point.
20
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADC108S102CIMT/NOPB
ACTIVE
TSSOP
PW
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
108S102
CIMT
ADC108S102CIMTX/NOPB
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
108S102
CIMT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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