ADC1175CIMTCX/NOPB

ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 ADC1175 8-Bit, 20MHz, 60mW A/D Converter Check for Samples: ADC1175 FEATURES DESCRIPTION • • • • • The ADC1175 is a low power, 20 Msps analog-todigital converter that digitizes signals to 8 bits while consuming just 60 mW of power (typ). The ADC1175 uses a unique architecture that achieves 7.5 Effective Bits. Output formatting is straight binary coding. 1 2 Internal Sample-and-Hold Function Single +5V Operation Internal Reference Bias Resistors Industry Standard Pinout TRI-STATE Outputs The excellent DC and AC characteristics of this device, together with its low power consumption and +5V single supply operation, make it ideally suited for many video, imaging and communications applications, including use in portable equipment. Furthermore, the ADC1175 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC1175's reference ladder is available for connections, enabling a wide range of input possibilities. APPLICATIONS • • • • • Video Digitization Digital Still Cameras Personal Computer Video Cameras CCD Imaging Electro-Optics KEY SPECIFICATIONS • • • • • • Resolution 8Bits Maximum Sampling Frequency 20Msps (min) DNL 0.75 LSB (max) ENOB 7.5 Bits (typ) Ensured No Missing Codes Power Consumption (excluding IREF) 60mW (typ) The ADC1175 is offered in a TSSOP. It is designed to operate over the commercial temperature range of -20°C to +75°C. PIN CONFIGURATION ADC1175 Pin Configuration TSSOP Package See Package Number PW 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com BLOCK DIAGRAM Figure 1. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. 2 Symbol 19 VIN 16 VRTS Equivalent Circuit Description Analog signal input. Conversion range is VRB to VRT. Reference Top Bias with internal pull-up resistor. Short this pin to VRT to self bias the reference ladder. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175 ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to AVDD. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See REFERENCE INPUTS for more information. 23 VRB Analog Input that is the low (bottom) side of the reference ladder of the ADC. Nominal range is 0V to 4.0V. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See REFERENCE INPUTS for more information. 22 VRBS Reference Bottom Bias with internal pull down resistor. Short to VRB to self bias the reference ladder. 17 DVDD 1 OE CMOS/TTL compatible Digital input that, when low, enables the digital outputs of the ADC1175. When high, the outputs are in a high impedance state. 1 DVSS Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175 3 ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description DVDD 12 CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input. CLK 12 DVSS DVDD 3 thru 10 D0-D7 Dn Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. These pins are enabled by bringing the OE pin low. DVSS 4 13 DVDD Positive digital supply pin. Connect to a clean voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10µF capacitor and a 0.1µF ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. 11 DVDD This digital supply pin supplies power for the digital output drivers. This pin should be connected to a supply source in the range of 2.5V to the Pin 13 potential. 2, 24 DVSS The ground return for the digital supply. AVSS and DVSS should be connected together close to the ADC1175. 14, 15, 18 AVDD Positive analog supply pin. Connected to a quiet voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. 20, 21 AVSS The ground return for the analog supply. AVSS and DVSS should be connected together close to the ADC1175 package. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175 ADC1175 www.ti.com SNAS012H – JANUARY 2000 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) AVDD, DVDD 6.5V Voltage on Any Pin −0.3V to 6.5V VRT, VRB AVSS to AVDD −0.5 to (AVDD + 0.5V) CLK, OE Voltage Digital Output Voltage Input Current DVSS to DVDD (4) ±25mA Package Input Current (4) ±50mA Package Dissipation at 25°C ESD Susceptibility (6) See Human Body Model 2000V Machine Model 200V Soldering Temp., Infrared, 10 sec. 300°C −65°C to +150°C Storage Temperature (1) (2) (3) (4) (5) (6) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see CONVERTER ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperatures (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance θJA, and the ambient temperature, TA, and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the ADC1175 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω. OPERATING RATINGS (1) (2) −20°C ≤ TA ≤ +75°C Operating Temperature Range Supply voltage (AVDD, DVDD) +4.75V to +5.25V AVDD − DVDD