ADC11DS105CISQ/NOPB

ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 ADC11DS105 Dual 11-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs Check for Samples: ADC11DS105 FEATURES DESCRIPTION • • • • • • The ADC11DS105is a high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 11-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. The ADC11DS105 may be operated from a single +3.0 or +3.3V power supply. A powerdown feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC11DS105 can be operated with an external 1.2V reference. The selectable duty cycle stabilizer maintains performance over a wide range of clock duty cycles. A serial interface allows access to the internal registers for full control of the ADC11DS105's functionality. The ADC11DS105 is available in a 60lead WQFN package and operates over the industrial temperature range of −40°C to +85°C. 1 2 Clock Duty Cycle Stabilizer Single +3.0 or +3.3V Supply Operation Serial LVDS Outputs Serial Control Interface Overrange Outputs 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch) APPLICATIONS • • • • • High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment Communications Instrumentation Portable Instrumentation KEY SPECIFICATIONS • • • • • • Resolution 11 Bits Conversion Rate 105 MSPS SNR (fIN = 240 MHz) 66 dBFS (typ) SFDR (fIN = 240 MHz) 82 dBFS (typ) Full Power Bandwidth 1 GHz (typ) Power Consumption 1 W (typ) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com PD_A SPI_EN SCSb SDI SDO SCLK DRGND VDR N/C DLC WAM ORA 57 56 55 54 53 52 51 49 48 47 46 50 VREF VA 58 VA 59 60 Connection Diagram AGND VINA- 1 45 OUTCLK+ 2 44 OUTCLK- VINA+ 3 43 FRAME+ AGND VRPA 4 42 FRAME- 5 41 VRNA 6 40 N/C VDR VCMOA 7 39 DRGND VA 8 38 SD1_A+ VCMOB 9 37 SD1_A- VRNB 10 36 SD0_A+ VRPB 11 35 SD0_A- AGND VINB+ 12 34 SD1_B+ 13 33 SD1_B- VINB- 14 32 SD0_B+ AGND 15 31 SD0_B- ADC11DS105 (top view) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VA CLK PD_B N/C N/C N/C DLL_Lock DRGND VDR TEST Reset_DLL LVDS_Bias ORB OF/DCS 16 VA * Exposed Pad Block Diagram ORA 2 2 VINA Ref.Outputs VREF 12-Bit Pipelined ADC Core Parallel -toSerial 2 Reference A 3 Reference B 2 12-Bit Pipelined ADC Core DLL & Timing Generation 2 CHANNEL A SD1_A FRAME 2 OUTCLK 2 VINB SD0_A 3 CLK Ref.Outputs 12 12 Parallel -toSerial 2 SD0_B CHANNEL B SD1_B ORB SCSb SCLK SPI_EN SDI SDO 2 SPI Interface & Control Registers Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 3 13 VINA+ VINB+ 2 14 VINAVINB- 5 11 VRPA VRPB 7 9 VCMOA VCMOB VA Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. AGND VA VA VA 6 10 VRNA VRNB VA These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. It is recommended to use VCMO to provide the common mode voltage, VCM, for the differential analog inputs. AGND AGND 59 VREF 29 LVDS_Bias Reference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, VREF should be decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series inductance (ESL) capacitor. This pin may be driven with an external 1.2V reference voltage. This pin should not be used to source or sink current. VA LVDS Driver Bias Resistor is applied from this pin to Analog Ground. The nominal value is 3.6KΩ AGND DIGITAL I/O 18 CLK VA 28 The clock input pin. The analog inputs are sampled on the rising edge of the clock input. Reset_DLL input. This pin is normally low. If the input clock frequency is changed abruptly, the internal timing circuits may become unlocked. Cycle this pin high for 1 microsecond to re-lock the DLL. The DLL will lock in several microseconds after Reset_DLL is asserted. Reset_DLL AGND Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 3 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Pin No. Symbol www.ti.com Equivalent Circuit VA 19 OF/DCS AGND 57 20 This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. PD_A PD_B TEST Test Mode. When this signal is asserted high, a fixed test pattern (101001100011 msb->lsb) is sourced at the data outputs. With this signal deasserted low, the device is in normal operation mode. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. WAM Word Alignment Mode. In single-lane mode this pin must be set to logic-0. In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this signal at logic-1 the serial data words are aligned with each other. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. VA 27 47 AGND 48 Dual-Lane Configuration. The dual-lane mode is selected when this signal is at logic-0. With this signal at logic-1, all data is sourced on a single lane (SD1_x) for each channel. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. DLC VDR 45 44 OUTCLK+ OUTCLK- - 43 42 FRAME+ FRAME- + - + DRGND 4 Description This is a four-state pin controlling the input clock mode and output data format. OF/DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock. OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the input clock. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Serial Clock. This pair of differential LVDS signals provides the serial clock that is synchronous with the Serial Data outputs. A bit of serial data is provided on each of the active serial data outputs with each falling and rising edge of this clock. This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Frame. This pair of differential LVDS signals transitions at the serial data word boundaries. The SD1_A+/- and SD1_B+/output words always begin with the rising edge of the Frame signal. The falling edge of the Frame signal defines the start of the serial data word presented on the SD0_A+/- and SD0_B+/- signal pairs in the Dual-Lane mode. This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com Pin No. 38 37 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Symbol Equivalent Circuit SD1_A+ SD1_A- VDR 34 33 SD1_B+ SD1_B- + - + 36 35 SD0_A+ SD0_A- DRGND 32 31 56 Description Serial Data Output 1 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s output in serialized form. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode each sample’s output is provided in succession. In Dual-Lane mode every other sample output is provided on this output. This differential output is always enabled while the device is powered up. In power-down mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 1 for Channel B. This is a differential LVDS pair of signals that carries channel B ADC’s output in serialized form. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode each sample’s output is provided in succession. In Dual-Lane mode every other sample output is provided on this output. This differential output is always enabled while the device is powered up. In power-down mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 0 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s alternating samples’ output in serialized form in Dual-Lane mode. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode this differential output is held in high impedance state. This differential output is always enabled while the device is powered up. In powerdown mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 0 for Channel B. This is a differential LVDS pair of signals that carries channel B ADC’s alternating samples’ output in serialized form in Dual-Lane mode. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode this differential output is held in high impedance state. This differential output is always enabled while the device is powered up. In powerdown mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. SD0_B+ SD0_B- VA SPI_EN SPI Enable: The SPI interface is enabled when this signal is asserted high. In this case the direct control pins have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are enabled. 55 SCSb Serial Chip Select: While this signal is asserted SCLK is used to accept serial data present on the SDI input and to source serial data on the SDO output. When this signal is deasserted, the SDI input is ignored and the SDO output is in tri-state mode. 52 SCLK Serial Clock: Serial data are shifted into and out of the device synchronous with this clock signal. 54 SDI Serial Data-In: Serial data are shifted into the device on this pin while SCSb signal is asserted. AGND Serial Data-Out: Serial data are shifted out of the device on this pin while SCSb signal is asserted. This output is in tri-state mode when SCSb is deasserted. 53 SDO 46 30 ORA ORB Overrange. These CMOS outputs are asserted logic-high when their respective channel’s data output is out-of-range in either high or low direction. 24 DLL_Lock DLL_Lock Output. When the internal DLL is locked to the input CLK, this pin outputs a logic high. If the input CLK is changed abruptly, the internal DLL may become unlocked and this pin will output a logic low. Cycle Reset_DLL (pin 28) to re-lock the DLL to the input CLK. VDR DRGND VA DGND Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 5 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Pin No. Symbol www.ti.com Equivalent Circuit Description ANALOG POWER 8, 16, 17, 58, 60 VA Positive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. 1, 4, 12, 15, Exposed Pad AGND The ground return for the analog supply. The exposed pad on back of package must be soldered to ground plane to ensure rated performance. 26, 40, 50 VDR Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. 25, 39, 51 DRGND DIGITAL POWER The ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 4.2V Supply Voltage (VA, VDR) −0.3V to (VA +0.3V) Voltage on Any Pin (Not to exceed 4.2V) Input Current at Any Pin other than Supply Pins Package Input Current (4) ±5 mA (4) ±50 mA Max Junction Temp (TJ) +150°C Thermal Resistance (θJA) (5) 30°C/W ESD Rating Human Body Model Machine Model (6) 2500V (6) 250V −65°C to +150°C Storage Temperature Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (7) (1) (2) (3) (4) (5) (6) (7) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10. The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω Reflow temperature profiles are different for lead-free and non-lead-free packages. Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Supply Voltages Clock Duty Cycle (1) (2) 6 +2.7V to +3.6V (DCS Enabled) 30/70 % (DCS disabled) 45/55 % Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Operating Ratings (1) (2) (continued) VCM 1.4V to 1.6V ≤100mV |AGND-DRGND| Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symbol Parameter Conditions Typical (3) Limits Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes (4) ±0.25 11 Bits (min) +0.75 LSB (max) -0.75 LSB (min) +0.5 LSB (max) INL Integral Non Linearity DNL Differential Non Linearity PGE Positive Gain Error NGE Negative Gain Error VOFF Offset Error Under Range Output Code 0 0 Over Range Output Code 2047 2047 ±0.20 -0.5 LSB (min) ±1 %FS (max) 0.1 ±1 %FS (max) 0.13 ±0.55 %FS (max) 0.1 REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO Common Mode Output Voltage 1.5 1.4 1.5 V (min) V (max) VCM Analog Input Common Mode Voltage 1.5 1.4 1.6 V (min) V (max) VIN Input Capacitance (each pin to GND) CIN (5) VREF Internal Reference Voltage TC VREF Internal Reference Voltage Tempco VRP VRN (1) (CLK LOW) 8.5 (CLK HIGH) 3.5 1.20 −40°C ≤ TA ≤ +85°C pF pF 1.17 1.22 V (min) V (max) 18 ppm/°C Internal Reference Top 2.0 V Internal Reference Bottom 1.0 Internal Reference Accuracy Ext VREF VIN = 1.5 Vdc ± 0.5 V (VRP-VRN) External Reference Voltage V 1.0 0.89 1.06 V (min) V (max) 1.20 1.176 1.224 V (min) V (max) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. VA I/O To Internal Circuitry AGND (2) (3) (4) (5) With a full scale differential input of 2VP-P , the 11-bit LSB is 976 µV. Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 7 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symbol Parameter Conditions Typical (3) Limits Units (Limits) (4) DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS FPBW SNR SFDR ENOB THD H2 Signal-to-Noise Ratio Spurious Free Dynamic Range Effective Number of Bits Total Harmonic Disortion Second Harmonic Distortion H3 Third Harmonic Distortion SINAD (1) Full Power Bandwidth Signal-to-Noise and Distortion Ratio -1 dBFS Input, −3 dB Corner 1.0 GHz fIN = 10 MHz 67.5 dBFS fIN = 70 MHz 67 dBFS fIN = 240 MHz 66 fIN = 10 MHz 88 dBFS fIN = 70 MHz 86 dBFS 64.9 fIN = 240 MHz 82 fIN = 10 MHz 10.9 Bits fIN = 70 MHz 10.8 Bits fIN = 240 MHz 10.6 fIN = 10 MHz −86 fIN = 70 MHz −85 fIN = 240 MHz −80 fIN = 10 MHz −95 fIN = 70 MHz −90 fIN = 240 MHz −85 fIN = 10 MHz −88 fIN = 70 MHz −86 fIN = 240 MHz −82 fIN = 10 MHz 67.4 fIN = 70 MHz 66.9 fIN = 240 MHz 65.8 76.5 dBFS 10.4 dBFS Bits dBFS dBFS -74 dBFS dBFS dBFS -76.5 dBFS dBFS dBFS -76.5 dBFS dBFS dBFS 64.4 dBFS The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. VA I/O To Internal Circuitry AGND (2) (3) (4) 8 With a full scale differential input of 2VP-P , the 11-bit LSB is 976 µV. Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symbol Parameter Conditions Typical (3) Limits Units (Limits) DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC) VIN(1) Logical “1” Input Voltage VD = 3.6V 2.0 V (min) VIN(0) Logical “0” Input Voltage VD = 3.0V 0.8 V (max) IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN = 0V −10 µA CIN Digital Input Capacitance 5 pF DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO,DLL_Lock) VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA +ISC Output Short Circuit Source Current VOUT = 0V −10 mA −ISC Output Short Circuit Sink Current VOUT = VDR 10 mA COUT Digital Output Capacitance 5 pF 1.2 V (min) 0.4 V (max) POWER SUPPLY CHARACTERISTICS IA Analog Supply Current Full Operation 240 270 mA (max) IDR Digital Output Supply Current Full Operation 70 80 mA 1 1.13 W (max) Clock disabled 33 Power Consumption Power Down Power Consumption (1) mW The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. VA I/O To Internal Circuitry AGND (2) (3) With a full scale differential input of 2VP-P , the 11-bit LSB is 976 µV. Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 9 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symb Parameter Conditions Typical (3) Limits Units (Limits) Maximum Clock Frequency In Single-Lane Mode In Dual-Lane Mode 65 105 MHz (max) Minimum Clock Frequency In Single-Lane Mode In Dual-Lane Mode 25 52.5 MHz (min) tCONV Conversion Latency Single-Lane Mode Dual-Lane, Offset Mode Dual-Lane, Word Aligned Mode 7.5 8 9 Clock Cycles tAD Aperture Delay 0.6 ns tAJ Aperture Jitter 0.1 ps rms (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. VA I/O To Internal Circuitry AGND (2) (3) With a full scale differential input of 2VP-P , the 11-bit LSB is 976 µV. Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Serial Control Interface Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symb fSCLK Parameter Serial Clock Frequency Conditions Typical fSCLK = fCLK/10 (3) Limits Units (Limits) 10.5 MHz (max) % (min) % (max) tPH SCLK Pulse Width - High % of SCLK Period 40 60 tPL SCLK Pulse Width - Low % of SCLK Period 40 60 % (min) % (max) tSU SDI Setup Time 5 ns (min) tH SDI Hold Time 5 ns (min) tODZ SDO Driven-to-Tri-State Time 15 20 ns (max) tOZD SDO Tri-State-to-Driven Time 40 50 ns (max) (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. VA I/O To Internal Circuitry AGND (2) (3) 10 With a full scale differential input of 2VP-P , the 11-bit LSB is 976 µV. Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Serial Control Interface Timing and AC Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symb Parameter Conditions Typical (3) Limits Units (Limits) tOD SDO Output Delay Time 15 20 ns (max) tCSS SCSb Setup Time 5 10 ns (min) tCSH SCSb Hold Time 5 10 tIAG Inter-Access Gap Minimum time SCSb must be deasserted between accesses ns (min) Cycles of SCLK 3 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V,VA = 3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Symbol Parameter Conditions Limits Units (Limits) 350 250 450 mV (min) mV (max) 1.25 Typical (3) LVDS DC CHARACTERISTICS Output Differential Voltage (SDO+) - (SDO-) RL = 100Ω delta VOD Output Differential Voltage Unbalance RL = 100Ω ±25 mV (max) Offset Voltage RL = 100Ω 1.125 1.375 V (min) V (max) delta VOS Offset Voltage Unbalance RL = 100Ω ±25 mV (max) IOS DO = 0V, VIN = 1.1V, VOD VOS Output Short Circuit Current -10 mA (max) ns LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS tDP Output Data Bit Period Dual-Lane Mode 1.59 tHO Output Data Edge to Output Clock Edge Hold Time (4) Dual-Lane Mode 760 450 ps (min) tSUO Output Data Edge to Output Clock Edge Set-Up Time (4) Dual-Lane Mode 800 500 ps (min) tFP Frame Period Dual-Lane Mode 19.05 45 55 % (min) % (max) tFDC Frame Clock Duty Cycle (4) tODOR Output Delay of OR output (1) 50 From rising edge of CLK to ORA/ORB valid ns 4 ns The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. VA I/O To Internal Circuitry AGND (2) (3) (4) With a full scale differential input of 2VP-P , the 11-bit LSB is 976 µV. Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 11 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error (1) It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error (2) INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. VD+ VDVOS VOD GND VOD = | VD+ - VD- | (3) LVDS Differential Output Voltage (VOD) is the absolute value of the difference between the differential output pair voltages (VD+ and VD-), each measured with respect to ground. LVDS Output Offset Voltage (VOS) is the midpoint between the differential output pair voltages. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is ensured not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale. 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition from code 1023 to 1024. OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as (4) where f1 is the RMS power of the fundamental (output) frequency and f2 through f7are the RMS power of the first six harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. Timing Diagrams tDP tDP OUTCLK tSUO SData tHO Valid Data Valid Data Valid Data Figure 1. Serial Output Data Timing Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 13 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com Sample N+1 Sample N VINA Sample N+2 VINB tSAMPLE = 1/fCLK CLK tSD tDP = tSAMPLE/12 OUTCLK tFP = tSAMPLE Sample N-1 ORA, ORB D0 D11 D0 D11 D2 D1 D3 D4 D5 D6 D7 D8 D9 D10 D0 SD1_A, SD1_B D11 FRAME Sample N Sample N+1 Sample N Sample N+1 NOTE: The ADC11DS105 output data word is 12 bits, however, D0 (LSB) is always logic 0. Figure 2. Serial Output Data Format in Single-Lane Mode 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Sample N+1 Sample N VINA Sample N+2 VINB tSAMPLE = 1/fCLK CLK tSD tDP = tSAMPLE/6 OUTCLK tFP = 2 x tSAMPLE FRAME OFFSET MODE : tDP Sample N Sample N-2 SD1_A, SD1_B D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Sample N-1 SD0_A, SD0_B D7 D6 D5 D0 D11 D10 D9 D4 D3 Sample N+1 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 NOTE: The ADC11DS105 output data word is 12 bits, however, D0 (LSB) is always logic 0. ORA, ORB Sample N Sample N+1 WORD-ALIGNED MODE : SD1_A, SD1_B D1 D0 D11 D10 D9 D8 D7 Sample N-1 SD0_A, SD0_B D1 Sample N+2 Sample N Sample N-2 D6 D5 D4 D3 D2 D1 D0 D11 D10 Sample N+3 Sample N+1 D0 D11 D10 D9 D8 D7 D6 D5 D9 D4 D3 D2 D1 D0 D11 D10 D9 NOTE: The ADC11DS105 output data word is 12 bits, however, D0 (LSB) is always logic 0. ORA, ORB Sample N Sample N+1 Figure 3. Serial Output Data Format in Dual-Lane Mode Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 15 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com Transfer Characteristic Figure 4. Transfer Characteristic 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION Operating on a single +3.0 or +3.3V supply, the ADC11DS105 digitizes two differential analog input signals to 11 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin. Duty cycle stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 19). The output data can be set for offset binary or two's complement. Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC11DS105: 2.7V ≤ VA ≤ 3.6V 2.7V ≤ VDR ≤ VA 25 MHz ≤ fCLK ≤ 105 MHz 1.2V internal reference VREF = 1.2V (for an external reference) VCM = 1.5V (from VCMO) ANALOG INPUTS Signal Inputs Differential Analog Input Pins The ADC11DS105 has a pair of analog signal input pins for each of two channels. VIN+ and VIN− form a differential input pair. The input signal, VIN, is defined as VIN = (VIN+) – (VIN−) (5) Figure 5 shows the expected input signal range. Note that the common mode input voltage, VCM, should be 1.5V. Using VCMO (pins 7,9) for VCM will ensure the proper input common mode level for the analog input signal. The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or the output data will be clipped. Figure 5. Expected Input Signal Range For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 2048( 1 - sin (90° + dev)) (6) Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 17 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see Figure 6). For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. Figure 6. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source impedance for the differential inputs will improve even ordered harmonic performance (particularly second harmonic). Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC11DS105 have an internal sample-and-hold circuit which consists of an analog switch followed by a switched-capacitor amplifier. Figure 7 and Figure 8 show examples of single-ended to differential conversion circuits. The circuit in Figure 7 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 8 works well above 70MHz. VIN 0.1 PF 20: ADT1-1WT 18 pF 50: ADC Input 0.1 PF 0.1 PF 20: VCMO Figure 7. Low Input Frequency Transformer Drive Circuit VIN 0.1 PF ETC1-1-13 100: 3 pF 0.1 PF ADC Input 100: ETC1-1-13 VCMO 0.1 PF Figure 8. High Input Frequency Transformer Drive Circuit One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed to the ADC core. Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 1.4V to 1.6V and be a value such that the peak excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is recommended to use VCMO (pins 7,9) as the input common mode voltage. 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Reference Pins The ADC11DS105 is designed to operate with an reference is the default condition when no external applied to the VREF pin, then that voltage is used for ground with a 0.1 µF capacitor close to the reference internal or external 1.2V reference. The internal 1.2 Volt reference input is applied to the VREF pin. If a voltage is the reference. The VREF pin should always be bypassed to input pin. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The Reference Bypass Pins (VRP, VCMO, and VRN) for channels A and B are made available for bypass purposes. These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. This configuration is shown in Figure 9. It is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. The remaining pins should not be loaded. Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. Loading any of these pins, other than VCMO may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VCMO = 1.5 V VRP = 2.0 V VRN = 1.0 V OF/DCS Pin Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate a stable internal clock, improving the performance of the part. With OF/DCS = VA the output data format is 2's complement and duty cycle stabilization is not used. With OF/DCS = AGND the output data format is offset binary and duty cycle stabilization is not used. With OF/DCS = (2/3)*VA the output data format is 2's complement and duty cycle stabilization is applied to the clock. If OF/DCS is (1/3)*VA the output data format is offset binary and duty cycle stabilization is applied to the clock. While the sense of this pin may be changed "on the fly," doing this is not recommended as the output data could be erroneous for a few clock cycles after this change is made. NOTE This signal has no effect when SPI_EN is high and the serial control interface is enabled. DIGITAL INPUTS Digital CMOS compatible inputs consist of CLK, and PD_A, PD_B, Reset_DLL, DLC, TEST, WAM, SPI_EN, SCSb, SCLK, and SDI. Clock Input The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90°. The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the minimum sample rate. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 (SNLA035) for information on setting characteristic impedance. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 19 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is (7) where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC11DS105 has a Duty Cycle Stabilizer. Power-Down (PD_A and PD_B) The PD_A and PD_B pins, when high, hold the respective channel of the ADC11DS105 in a power-down mode to conserve power when that channel is not being used. The channels may be powereed down individually or together. The data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the components on the reference bypass pins ( VRP, VCMO and VRN ). These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance. NOTE This signal has no effect when SPI_EN is high and the serial control interface is enabled. Reset_DLL This pin is normally low. If the input clock frequency is changed abruptly, the internal timing circuits may become unlocked. Cycle this pin high for 1 microsecond to re-lock the DLL. The DLL will lock in several microseconds after Reset_DLL is asserted. DLC This pin sets the output data configuration. With this signal at logic-1, all data is sourced on a single lane (SD1_x) for each channel. When this signal is at logic-0, the data is sourced on dual lanes (SD0_x and SD1_x) for each channel. This simplifies data capture at higher data rates. NOTE This signal has no effect when SPI_EN is high and the SPI interface is enabled. TEST When this signal is asserted high, a fixed test pattern (101001100011 msb->lsb) is sourced at the data outputs. When low, the ADC is in normal operation. The user may specify a custom test pattern via the serial control interface. NOTE This signal has no effect when SPI_EN is high and the SPI interface is enabled. WAM In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this signal at logic-1 the serial data words are aligned with each other. In single lane mode this pin must be set to logic-0. 20 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 NOTE This signal has no effect when SPI_EN is high and the SPI interface is enabled. SPI_EN The SPI interface is enabled when this signal is asserted high. In this case the direct control pins (OF/DCS, PD_A, PD_B, DLC, WAM, TEST) have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are enabled. SCSb, SDI, SCLK These pins are part of the SPI interface. See Serial Control Interface for more information. DIGITAL OUTPUTS Digital outputs consist of six LVDS signal pairs (SD0_A, SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS logic outputs ORA, ORB, DLL_Lock, and SDO. LVDS Outputs The digital output data word for each channel is 12 bits long where D11 is the MSB and D0 is the LSB. D0 is always a logic 0. The digital data for each channel is provided in a serial format. Two modes of operation are available for the serial data format. Single-lane serial format (shown in Figure 2) uses one set of differential data signals per channel. Dual-lane serial format (shown in Figure 3) uses two sets of differential data signals per channel in order to slow down the data and clock frequency by a factor of 2. At slower rates of operation (typically below 65 MSPS) the single-lane mode may the most efficient to use. At higher rates the user may want to employ the dual-lane scheme. In either case DDR-type clocking is used. For each data channel, an overrange indication is also provided. The OR signal is updated with each frame of data. ORA, ORB These CMOS outputs are asserted logic-high when their respective channel’s data output is out-of-range in either high or low direction. DLL_Lock When the internal DLL is locked to the input CLK, this pin outputs a logic high. If the input CLK is changed abruptly, the internal DLL may become unlocked and this pin will output a logic low. Cycle Reset_DLL to re-lock the DLL to the input CLK. SDO This pin is part of the SPI interface. See Serial Control Interface for more information. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 21 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com +3.3V +3.0V 3x 0.1 PF 5x 0.1 PF + 7 0.1 PF 0.1 PF 0.1 PF 1 PF 20 SDO 11 0.1 PF 1 PF VCMOB 0.1 PF 2 VINA+ VINA- OUTCLK+ OUTCLK- 50 FRAME+ FRAME- 20 0.1 PF 0.1 PF 2 20 45 44 43 42 SD1_A+ 38 SD1_A- 37 18 pF 0.1 PF 55 13 14 To capture device (ASIC or FPGA). Note, all signal pairs should be routed with 100 ohm differential impedance, and should be terminated with a 100 ohm resistor near the input of the capture device. SD0_A+ 36 SD0_A- 35 VINB+ VINB- SD1_B+ 34 ADT1-1WT 57 20 These control pins are ignored when SPI_EN is high 27 47 56 OF/DCS PD_A PD_B TEST LVDS_Bias 29 3.6k WAM SPI_EN 1 4 12 15 SPI_EN SD1_B- 33 SD0_B+ 32 SD0_B- 31 DR GND DR GND DR GND Crystal Oscillator 19 CLK AGND AGND AGND AGND 18 25 39 51 1 SPI Interface 54 ADC11DS105 3 2 ADT1-1WT VIN_B 53 VRNB 18 pF 20 SCSb 52 VRPB 0.1 PF 0.1 PF SCLK SDI 0.1 PF 10 0.1 PF 26 40 50 5 V A RP 6 VRNA 9 0.1 PF 1 VREF VCMOA 0.1 PF 50 VIN_A V DR V DR V DR 59 8 16 17 58 60 0.1 PF VA VA VA VA VA 10 PF Figure 9. Application Circuit Serial Control Interface The ADC11DS105 has a serial interface that allows access to the control registers. The serial interface is a generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers and DSP controllers. The ADC's input clock must be running for the Serial Control Interface to operate. It is enabled when the SPI_EN (pin 56) signal is asserted high. In this case the direct control pins (OF/DCS, PD_A, PD_B, DLC, WAM, TEST) have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are enabled. Each serial interface access cycle is exactly 16 bits long. Figure 10 shows the access protocol used by this interface. Each signal's function is described below. The Read Timing is shown in Figure 11, while the Write Timing is shown in Figure 12 22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D2 D1 D0 (LSB) D2 D1 17 SCLK SCSb COMMAND FIELD SDI C7 C6 C5 C4 R/Wb 0 0 0 Reserved (3-bits) DATA FIELD C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 (MSB) D5 D4 D3 Write DATA Address (4-bits) D7 D6 (MSB) D5 D4 D3 D0 (LSB) Hi-Z Read DATA SDO Data (8-bits) Single Access Cycle Figure 10. Serial Interface Protocol SCLK: Used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. User may disable clock and hold it in the low-state, as long as clock pulse-width min spec is not violated when clock is enabled or disabled. SCSb: Serial Interface Chip Select. Each assertion starts a new register access - i.e., the SDATA field protocol is required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the deasserted pulse - which is specified in the Electrical Specifications section. SDI: Serial Data. Must observe setup/hold requirements with respect to the SCLK. Each cycle is 16-bits long. R/Wb: A value of '1' indicates a read operation, while a value of '0' indicates a write operation. Reserved: Reserved for future use. Must be set to 0. ADDR: Up to 3 registers can be addressed. DATA: In a write operation the value in this field will be written to the register addressed in this cycle when SCSb is deasserted. In a read operation this field is ignored. SDO: This output is normally at TRI-STATE and is driven only when SCSb is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. Upon power-up, the default register address is 00h. st 1 clock th th 8 clock 16 clock SCLK tCSH tCSS tCSH tCSS CSb tOZD SDO tODZ tOD D7 D1 D0 Figure 11. Read Timing Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 23 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com tPL tPH 16th clock SCLK tSU SDI tH Valid Data Valid Data Figure 12. Write Timing Table 1. Device Control Register, Address 0h 7 6 OM 5 4 3 2 1 0 DLC DCS OF WAM PD_A PD_B Reset State : 08h Bits (7:6) Operational Mode 0 0 Normal Operation. 0 1 Test Output mode. A fixed test pattern (1010011000111msb->lsb) is sourced at the data outputs. 1 0 Test Output mode. Data pattern defined by user in registers 01h and 02h is sourced at data outputs. 1 1 Reserved. Bit 5 Data Lane Configuration. When this bit is set to '0', the serial data interface is configured for dual-lane mode where the data words are output on two data outputs (SD1 and SD0) at half the rate of the single-lane interface. When this bit is set to ‘1’, serial data is output on the SD1 output only and the SD0 outputs are held in a high-impedance state Bit 4 Duty Cycle Stabilizer. When this bit is set to '0' the DCS is off. When this bit is set to ‘1’, the DCS is on. Bit 3 Output Data Format. When this bit is set to ‘1’ the data output is in the “twos complement” form. When this bit is set to ‘0’ the data output is in the “offset binary” form. Bit 2 Word Alignment Mode. This bit must be set to '0' in the single-lane mode of operation. In dual-lane mode, when this bit is set to '0' the serial data words are offset by half-word. This gives the least latency through the device. When this bit is set to '1' the serial data words are in word-aligned mode. In this mode the serial data on the SD1 lane is additionally delayed by one CLK cycle. (Refer to Figure 3). Bit 1 Power-Down Channel A. When this bit is set to '1', Channel A is in power-down state and Normal operation is suspended. Bit 0 Power-Down Channel B. When this bit is set to '1', Channel B is in power-down state and Normal operation is suspended. Table 2. User Test Pattern Register 0, Address 1h 7 6 5 4 Reserved 3 2 1 0 User Test Pattern (13:6) Reset State : 00h Bits (7:6) Reserved. Must be set to '0'. Bits (5:0) User Test Pattern. Most-significant 6 bits of the 12-bit pattern that will be sourced out of the data outputs in Test Output Mode. Table 3. User Test Pattern Register 1, Address 2h 7 6 5 4 3 User Test Pattern (5:0) 24 Submit Documentation Feedback 2 1 0 Reserved Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 Reset State : 00h Bits (7:2) User Test Pattern. Least-significant 6 bits of the 12-bit pattern that will be sourced out of the data outputs in Test Output Mode. Bits (1:0) Reserved. Must be set to '0'. POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor close to each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC11DS105 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC11DS105 between these areas, is required to achieve specified performance. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane area. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. Be especially careful with the layout of inductors and transformers. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog input and the clock input at 90° to one another to avoid magnetic coupling. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The ADC11DS105 should be between these two areas. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single, quiet point. All ground connections should have a low inductance path to ground. DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 13. The gates used in the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be prevented. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 25 ADC11DS105 SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 www.ti.com As mentioned in POWER SUPPLY CONSIDERATIONS, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line. Figure 13. Isolating the ADC Clock from other Circuitry with a Clock Tree 26 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 26 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC11DS105 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADC11DS105CISQE/NOPB ACTIVE WQFN NKA 60 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 11DS105 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of