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ADC12062
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ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter
with Input Multiplexer and Sample/Hold
Check for Samples: ADC12062
FEATURES
DESCRIPTION
•
•
•
Using an innovative multistep conversion technique,
the 12-bit ADC12062 CMOS analog-to-digital
converter digitizes signals at a 1 MHz sampling rate
while consuming a maximum of only 75 mW on a
single +5V supply. The ADC12062 performs a 12-bit
conversion
in
three
lower-resolution
“flash”
conversions, yielding a fast A/D without the cost and
power dissipation associated with true flash
approaches.
1
2
•
Built-In Sample-and-Hold
Single +5V Supply
Single Channel or 2 Channel Multiplexer
Operation
Low Power Standby Mode
APPLICATIONS
•
•
•
•
•
Digital Signal Processor Front Ends
Instrumentation
Disk Drives
Mobile Telecommunications
Waveform Digitizers
KEY SPECIFICATIONS
•
•
•
•
•
Sampling rate: 1 MHz (min)
Conversion time: 740 ns (typ)
Signal-to-Noise Ratio, fIN = 100 kHz: 69.5 dB
(min)
Power consumption (fs = 1 MHz): 75 mW (max)
No missing codes over temperature: Ensured
The analog input voltage to the ADC12062 is tracked
and held by an internal sampling circuit, allowing high
frequency input signals to be accurately digitized
without the need for an external sample-and-hold
circuit. The multiplexer output is available to the user
in order to perform additional external signal
processing before the signal is digitized.
When the converter is not digitizing signals, it can be
placed in the Standby mode; typical power
consumption in this mode is 100 μW.
BLOCK DIAGRAM
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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OBSOLETE
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2) (3)
−0.3V to +6V
Supply Voltage (VCC = DVCC = AVCC)
−0.3V to VCC + 0.3V
Voltage at Any Input or Output
Input Current at Any Pin
Package Input Current
(4)
25 mA
(4)
50 mA
Power Dissipation
(5)
875 mW
ESD Susceptibility
(6)
2000V
Soldering Information
FNH Package, Infrared, 15 seconds
PGB Package
+300°C
Vapor Phase (60 seconds)
+215°C
Infrared (15 seconds)
+220°C
−65°C to +150°C
Storage Temperature Range
Maximum Junction Temperature
(1)
(2)
(3)
(4)
(5)
(6)
(TJMAX)
150°C
All voltages are measured with respect to GND (GND = AGND = DGND), unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. These ratings do not ensure specific performance limits, however. For specifications and test conditions,
see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that
pin should be limited to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power
supplies with an input current of 25 mA to two.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature
TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute
Maximum Ratings, whichever is lower. θJA for the FNH (PLCC) package is 55°C/W. θJA for the PGB (PQFP) package is 62°C/W. In
most cases the maximum derated power dissipation will be reached only during fault conditions.
Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model ESD rating is 200V.
OPERATING RATINGS
(1) (2)
TMIN ≤ TA ≤ TMAX
Temperature Range
ADC12062CIV,
Supply Voltage Range
(1)
(2)
2
−40°C ≤ TA ≤ +85°C
ADC12062BIVF, ADC12062CIVF
(DVCC = AVCC)
4.5V to 5.5V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. These ratings do not ensure specific performance limits, however. For specifications and test conditions,
see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND (GND = AGND = DGND), unless otherwise specified.
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CONVERTER CHARACTERISTICS
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1 MHz,
unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C.
Symbol
Parameter
Conditions
Typ (1)
Limit (2)
12
Bits
±0.4
±0.8
LSB (max)
Resolution
TA = 25°C
Differential Linearity Error
TMIN to TMAX
Integral Linearity Error
(3)
±0.95
LSB (max)
TMIN to TMAX (BIV Suffix)
±0.4
±1.0
LSB (max)
TA = +25°C (CIV Suffix)
±0.4
±1.0
LSB (max)
±1.5
LSB (max)
TMIN to TMAX (CIV Suffix)
Offset Error
TMIN to TMAX (BIV Suffix)
±0.3
±1.25
LSB (max)
TA = +25°C (CIV Suffix)
±0.3
±1.25
LSB (max)
±2.0
LSB (max)
TMIN to TMAX (CIV Suffix)
Full Scale Error
Power Supply Sensitivity
(4)
Units
(Limit)
TMIN to TMAX (BIV Suffix)
±0.2
±1.0
LSB (max)
TA = +25°C (CIV Suffix)
±0.2
±1.0
LSB (max)
TMIN to TMAX (CIV Suffix)
±1.5
LSB (max)
DVCC = AVCC = 5V ±10%
±1.0
LSB (max)
600
Ω (min)
RREF
Reference Resistance
1300
Ω (max)
VREF(+)
VREF+(SENSE) Input Voltage
AVCC
V (max)
VREF(−)
VREF−(SENSE) Input Voltage
AGND
V (min)
VIN
Input Voltage Range
To VIN1, VIN2, or ADC IN
AVCC + 0.05V
V (max)
ADC IN Input Leakage
AGND to AVCC − 0.3V
0.1
MUX On-Channel Leakage
AGND to AVCC − 0.3V
MUX Off-Channel Leakage
AGND to AVCC − 0.3V
CADC
CMUX
ADC IN Input Capacitance
AGND − 0.05V
V (min)
3
μA (max)
0.1
3
μA (max)
0.1
3
μA (max)
25
Multiplexer Input Cap
MUX Off Isolation
(1)
(2)
(3)
(4)
1000
fIN = 100 kHz
pF
7
pF
92
dB
Typicals are at +25°C and represent most likely parametric norm.
Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
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DYNAMIC CHARACTERISTICS
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(1)
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, RS = 25Ω, fIN =
100 kHz, 0 dB from fullscale, and fs = 1 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to
TMAX; all other limits TA = TJ = +25°C.
Symbol
Distortion Ratio
SNR
Signal-to-Noise Ratio
(4)
Total Harmonic Distortion
THD
Units
(Limit)
TMIN to TMAX
71
68.0
dB (min)
TMIN to TMAX
72
69.5
dB (min)
−74
dBc (max)
−70
dBc (max)
11.0
Bits (min)
TA = +25°C
(5)
−82
TMIN to TMAX
ENOB
Effective Number of Bits
IMD
Intermodulation Distortion
(1)
Limit (3)
Conditions
Signal-to-Noise Plus
SINAD
Typ (2)
Parameter
(6)
TMIN to TMAX
11.5
fIN = 102.3 kHz, 102.7 kHz
−80
dBc
Dynamic testing of the ADC12062 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies.
See the graph in the TYPICAL PERFORMANCE CHARACTERISTICS for a typical graph of THD performance vs input frequency with
and without the input multiplexer.
Typicals are at +25°C and represent most likely parametric norm.
Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included
in its calculation.
The contributions from the first nine harmonics are used in the calculation of the THD.
Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB
= (SINAD − 1.76)/6.02.
(2)
(3)
(4)
(5)
(6)
DC ELECTRICAL CHARACTERISTICS
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1 MHz,
unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C.
Symbol
Parameter
Typ (1)
Conditions
Limit (2)
Units
(Limit)
VIN(1)
Logical “1” Input Voltage
DVCC = AVCC = +5.5V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
DVCC = AVCC = +4.5V
0.8
V (max)
IIN(1)
Logical “1” Input Current
0.1
1.0
μA (max)
IIN(0)
Logical “0” Input Current
0.1
1.0
μA (max)
IOUT = −360 μA
2.4
V (min)
IOUT = −100 μA
4.25
V (min)
DVCC = AVCC = +4.5V,
0.4
V (max)
3
μA (max)
DVCC = AVCC = +4.5V,
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
TRI-STATE Output
IOUT
Leakage Current
IOUT = 1.6 mA
Pins DB0–DB11
0.1
Pins DB0–DB11
5
pF
4
pF
COUT
TRI-STATE Output Capacitance
CIN
Digital Input Capacitance
DICC
DVCC Supply Current
2
3
mA (max)
AICC
AVCC Supply Current
10
12
mA (max)
ISTANDBY
Standby Current (DICC + AICC)
(1)
(2)
4
PD = 0V
20
μA
Typicals are at +25°C and represent most likely parametric norm.
Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
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AC ELECTRICAL CHARACTERISTICS
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1 MHz,
unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C.
Symbol
Parameter
Conversion Time
S/H Low to EOC Low
Access Time
tACC
(RD Low or OE High to Data Valid)
t1H, t0H
tINTH
TRI-STATE Control
(RD High or OE Low to Databus TRI-STATE)
Delay from RD Low to INT High
tINTL
Delay from EOC High to INT Low
tUPDATE
EOC High to New Data Valid
tWU
(1)
(2)
95
(2)
Units
(Limits)
MHz (min)
600
ns (min)
980
ns (max)
20
S/H Pulse Width
tEOC
tCSH
740
(S/H Low to EOC High)
(S/H Low to Input Voltage Held)
tS/H
Limit
1
Aperture Delay
tAD
tCSS
(1)
(1/tTHROUGHPUT)
tCONV
tMH
Typ
Maximum Sampling Rate
fs
tMS
Conditions
ns
5
ns (min)
550
ns (max)
60
ns (min)
185
ns (max)
CL = 100 pF
10
20
ns (max)
RL = 1k, CL = 10 pF
25
40
ns (max)
CL = 100 pF
35
60
ns (max)
CL = 100 pF
−25
5
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
CS Hold Time
(CS High after RD High, S/H High, or OE Low)
Wake-Up Time
1
(PD High to First S/H Low)
−35
ns (min)
−5
ns (max)
30
ns (max)
50
ns (min)
50
ns (min)
20
ns (min)
20
ns (min)
μs
Typicals are at +25°C and represent most likely parametric norm.
Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
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TRI-STATE TEST CIRCUIT AND WAVEFORMS
6
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TYPICAL PERFORMANCE CHARACTERISTICS
Offset and Fullscale
Error Change vs
Reference Voltage
Linearity Error Change
vs Reference Voltage
Figure 1.
Figure 2.
Mux ON Resistance vs
Input Voltage
Digital Supply Current
vs Temperature
Figure 3.
Figure 4.
Analog Supply Current
vs Temperature
Current Consumption in
Standby Mode
vs
Voltage
on Digital Input Pins
Figure 5.
Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
8
Conversion Time (tCONV)
vs Temperature
EOC Delay Time (tEOC)
vs Temperature
Figure 7.
Figure 8.
Spectral Response
SINAD
vs
Input Frequency
(ADC IN)
Figure 9.
Figure 10.
SNR
vs
Input Frequency
(ADC IN)
THD
vs
Input Frequency
(ADC IN)
Figure 11.
Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
SINAD
vs
Input Frequency
(Through Mux)
SNR
vs
Input Frequency
(Through Mux)
Figure 13.
Figure 14.
THD
vs
Input Frequency
(Through Mux)
SNR and THD
vs
Source
Impedance
Figure 15.
Figure 16.
SNR and THD vs
Reference Voltage
Figure 17.
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TIMING DIAGRAMS
Figure 18. Interrupt Interface Timing (MODE = 1, OE = 1)
(MODE = 1, OE = 1, CS = 0, RD = 0)
Figure 19. High Speed Interface Timing
10
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Figure 20. CS Setup and Hold Timing for S/H, RD, and OE
Connection Diagram
Figure 21. Top View
Figure 22. Top View
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PIN DESCRIPTIONS
12
AVCC
These are the two positive analog supply inputs. They should always be connected to the same
voltage source, but are brought out separately to allow for separate bypass capacitors. Each
supply pin should be bypassed to AGND with a 0.1 µF ceramic capacitor in parallel with a 10 µF
tantalum capacitor.
DVCC
This is the positive digital supply input. It should always be connected to the same voltage as the
analog supply, AVCC. It should be bypassed to DGND2 with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor.
AGND, DGND1, DGND2
These are the power supply ground pins. There are separate analog and digital ground pins for
separate bypassing of the analog and digital supplies. The ground pins should be connected to a
stable, noise-free system ground. All of the ground pins should be returned to the same potential.
AGND is the analog ground for the converter. DGND1 is the ground pin for the digital control
lines. DGND2 is the ground return for the output databus. See LAYOUT AND GROUNDING for
more information.
DB0–DB11
These are the TRI-STATE output pins, enabled by RD, CS, and OE.
VIN1, VIN2
These are the analog input pins to the multiplexer. For accurate conversions, no input pin (even
one that is not selected) should be driven more than 50 mV below ground or 50 mV above VCC.
MUX OUT
This is the output of the on-board analog input multiplexer.
ADC IN
This is the direct input to the 12-bit sampling A/D converter. For accurate conversions, this pin
should not be driven more than 50 mV below AGND or 50 mV above AVCC.
S0
This pin selects the analog input that will be connected to the ADC12062 during the conversion.
The input is selected based on the state of S0 when EOC makes its high-to-low transition. Low
selects VIN1, high selects VIN2.
MODE
This pin should be tied to DVCC.
CS
This is the active low Chip Select control input. When low, this pin enables the RD, S/H, and OE
inputs. This pin can be tied low.
INT
This is the active low Interrupt output. When using the Interrupt Interface Mode (Figure 18), this
output goes low when a conversion has been completed and indicates that the conversion result
is available in the output latches. This output is always high when RD is held low (Figure 19).
EOC
This is the End-of-Conversion control output. This output is low during a conversion.
RD
This is the active low Read control input. When RD is low (and CS is low), the INT output is reset
and (if OE is high) data appears on the data bus. This pin can be tied low.
OE
This is the active high Output Enable control input. This pin can be thought of as an inverted
version of the RD input (see Figure 25). Data output pins DB0–DB11 are TRI-STATE when OE is
low. Data appears on DB0–DB11 only when OE is high and CS and RD are both low. This pin
can be tied high.
S/H
This is the Sample/Hold control input. The analog input signal is held and a new conversion is
initiated by the falling edge of this control input (when CS is low).
PD
This is the Power Down control input. This pin should be held high for normal operation. When
this pin is pulled low, the device goes into a low power standby mode.
VREF+(FORCE), VREF-(FORCE)
These are the positive and negative voltage reference force inputs, respectively. See
REFERENCE INPUTS for more information.
VREF+(SENSE), VREF-(SENSE)
These are the positive and negative voltage reference sense pins, respectively. See
REFERENCE INPUTS for more information.
VREF/16
This pin should be bypassed to AGND with a 0.1 µF ceramic capacitor.
TEST
This pin should be tied to DVCC.
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FUNCTIONAL DESCRIPTION
The ADC12062 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash
determines the six most significant bits, the second flash generates four more bits, and the final flash resolves
the two least significant bits. Figure 23 shows the major functional blocks of the converter. It consists of a 2½-bit
Voltage Estimator, a resistor ladder with two different resolution voltage spans, a sample/hold capacitor, a 4-bit
flash converter with front end multiplexer, a digitally corrected DAC, and a capacitive voltage divider.
The resistor string near the center of the block diagram in Figure 23 generates the 6-bit and 10-bit reference
voltages for the first two conversions. Each of the 16 resistors at the bottom of the string is equal to 1/1024 of the
total string resistance. These resistors form the LSB Ladder (The weight of each resistor on the LSB ladder is
actually equivalent to four 12-bit LSBs. It is called the LSB ladder because it has the highest resolution of all the
ladders in the converter) and have a voltage drop of 1/1024 of the total reference voltage (VREF+ − VREF−) across
each of them. The remaining resistors form the MSB Ladder. It is comprised of eight groups of eight resistors
each connected in series (the lowest MSB ladder resistor is actually the entire LSB ladder). Each MSB Ladder
section has ⅛ of the total reference voltage across it. Within a given MSB ladder section, each of the eight MSB
resistors has 1/64 of the total reference voltage across it. Tap points are found between all of the resistors in
both the MSB and LSB ladders. The Comparator MultipIexer can connect any of these tap points, in two adjacent
groups of eight, to the sixteen comparators shown at the right of Figure 23. This function provides the necessary
reference voltages to the comparators during the first two flash conversions.
The six comparators, seven-resistor string (Estimator DAC ladder), and Estimator Decoder at the left of Figure 23
form the Voltage Estimator. The Estimator DAC, connected between VREF+ and VREF−, generates the reference
voltages for the six Voltage Estimator comparators. The comparators perform a very low resoIution A/D
conversion to obtain an “estimate” of the input voltage. This estimate is used to control the placement of the
Comparator Multiplexer, connecting the appropriate MSB ladder section to the sixteen flash comparators. A total
of only 22 comparators (6 in the Voltage Estimator and 16 in the flash converter) is required to quantize the input
to 6 bits, instead of the 64 that would be required using a traditional 6-bit flash.
Prior to a conversion, the Sample/Hold switch is closed, allowing the voltage on the S/H capacitor to track the
input voItage. Switch 1 is in position 1. A conversion begins by opening the Sample/Hold switch and latching the
output of the Voltage Estimator. The estimator decoder then selects two adjacent banks of tap points aIong the
MSB ladder. These sixteen tap points are then connected to the sixteen flash converters. For exampIe, if the
input voltage is between 5/16 and 7/16 of VREF (VREF = VREF+ − VREF−), the estimator decoder instructs the
comparator multiplexer to select the sixteen tap points between 2/8 and 4/8 (4/16 and 8/16) of VREF and connects
them to the sixteen comparators. The first flash conversion is now performed, producing the first 6 MSBs of data.
At this point, Voltage Estimator errors as large as 1/16 of VREF will be corrected since the comparators are
connected to ladder voltages that extend beyond the range specified by the Voltage Estimator. For example, if
(7/16)VREF < VIN < (9/16)VREF, the Voltage Estimator's comparators tied to the tap points below (9/16)VREF will
output “1”s (000111). This is decoded by the estimator decoder to “10”. The 16 comparators will be placed on the
MSB ladder tap points between (⅜)VREF and (⅝)VREF. This overlap of (1/16)VREF will automatically cancel a
Voltage Estimator error of up to 256 LSBs. If the first flash conversion determines that the input voltage is
between (⅜)VREF and ((4/8)VREF − LSB/2), the Voltage Estimator's output code will be corrected by subtracting
“1”, resulting in a corrected value of “01” for the first two MSBs. If the first flash conversion determines that the
input voltage is between (4/8)VREF − LSB/2) and (⅝)VREF, the voltage estimator's output code is unchanged.
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Figure 23. Functional Block Diagram
The results of the first flash and the Voltage Estimator's output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to the error of the MSB ladder at that tap. This code is
converted to a voltage by the Correction DAC. To generate the next four bits, SW1 is moved to position 2, so the
ladder voltage and the correction voltage are subtracted from the input voltage. The remainder is applied to the
sixteen flash converters and compared with the 16 tap points from the LSB ladder.
The result of this second conversion is accurate to 10 bits and describes the input remainder as a voltage
between two tap points (VH and VL) on the LSB ladder. To resolve the last two bits, the voltage across the ladder
resistor (between VH and VL) is divided up into 4 equal parts by the capacitive voltage divider, shown in
Figure 24. The divider also creates 6 LSBs below VL and 6 LSBs above VH to provide overlap used by the digital
error correction. SW1 is moved to position 3, and the remainder is compared with these 16 new voltages. The
output is combined with the results of the Voltage Estimator, first flash, and second flash to yield the final 12-bit
result.
By using the same sixteen comparators for all three flash conversions, the number of comparators needed by the
multi-step converter is significantly reduced when compared to standard multi-step techniques.
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APPLICATIONS INFORMATION
MODES OF OPERATION
The ADC12062 has two interface modes: An interrupt/read mode and a high speed mode. Figure 18 and
Figure 19 show the timing diagrams for these interfaces.
In order to clearly show the relationship between S/H, CS, RD, and OE, the control logic decoding section of the
ADC12062 is shown in Figure 25.
Interrupt Interface
As shown in Figure 18, the falling edge of S/H holds the input voltage and initiates a conversion. At the end of
the conversion, the EOC output goes high and the INT output goes low, indicating that the conversion results are
latched and may be read by pulling RD low. The falling edge of RD resets the INT line. Note that CS must be low
to enable S/H or RD.
High Speed Interface
This is the fastest interface, shown in Figure 19. Here the output data is always present on the databus, and the
INT to RD delay is eliminated.
Figure 24. The Capacitive Voltage Divider
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Figure 25. ADC Control Logic
THE ANALOG INPUT
The analog input of the ADC12062 can be modeled as two small resistances in series with the capacitance of
the input hold capacitor (CIN), as shown in Figure 26. The S/H switch is closed during the Sample period, and
open during Hold. The source has to charge CIN to the input voltage within the sample period. Note that the
source impedance of the input voltage (RSOURCE) has a direct effect on the time it takes to charge CIN. If RSOURCE
is too large, the voltage across CIN will not settle to within 0.5 LSBs of VSOURCE before the conversion begins, and
the conversion results will be incorrect. From a dynamic performance viewpoint, the combination of RSOURCE,
RMUX, RSW, and CIN form a low pass filter. Minimizing RSOURCE will increase the frequency response of the input
stage of the converter.
Typical values for the components shown in Figure 26 are: RMUX = 100Ω, RSW = 100Ω, and CIN = 25 pF. The
settling time to n bits is:
tSETTLE = (RSOURCE + RMUX + RSW) * CIN * n * ln (2).
(1)
The bandwidth of the input circuit is:
f−3dB = 1/(2 * 3.14 * (RSOURCE + RMUX + RSW) * CIN)
(2)
For maximum performance, the impedance of the source driving the ADC12062 should be made as small as
possible. A source impedance of 100Ω or less is recommended. A plot of dynamic performance vs. source
impedance, Figure 16, is given in TYPICAL PERFORMANCE CHARACTERISTICS.
If the signal source has a high output impedance, its output should be buffered with an operational amplifier
capable of driving a switched 25 pF/100Ω load. Any ringing or instabilities at the op amp's output during the
sampling period can result in conversion errors. The LM6361 high speed op amp is a good choice for this
application due to its speed and its ability to drive large capacitive loads. Figure 27 shows the LM6361 driving the
ADC IN input of an ADC12062. The 100 pF capacitor at the input of the converter absorbs some of the high
frequency transients generated by the S/H switching, reducing the op amp transient response requirements. The
100 pF capacitor should only be used with high speed op amps that are unconditionally stable driving capacitive
loads.
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Figure 26. Simplified ADC12062 Input Stage
Figure 27. Buffering the Input with an LM6361 High Speed Op Amp
Another benefit of using a high speed buffer is improved THD performance when using the multiplexer of the
ADC12062. The MUX on-resistance is somewhat non-linear over input voltage, causing the RC time constant
formed by CIN, RMUX, and RSW to vary depending on the input voltage. This results in increasing THD with
increasing frequency. Inserting the buffer between the MUX OUT and the ADC IN terminals as shown in
Figure 27 will eliminate the loading on RMUX, significantly reducing the THD of the multiplexed system.
Correct converter operation will be obtained for input voltages greater than AGND − 50 mV and less than AVCC +
50 mV. Avoid driving the signal source more than 300 mV higher than AVCC, or more than 300 mV below AGND.
If an analog input pin is forced beyond these voltages, the current flowing through that pin should be limited to 25
mA or less to avoid permanent damage to the IC. The sum of all the overdrive currents into all pins must be less
than 50 mA. When the input signal is expected to extend more than 300 mV beyond the power supply limits for
any reason (unknown/uncontrollable input voltage range, power-on transients, fault conditions, etc.) some form of
input protection, such as that shown in Figure 28, should be used.
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Figure 28. Input Protection
ANALOG MULTIPLEXER
The ADC12062 has an input multiplexer that is controlled by the logic level on pin S0 when EOC goes low, as
shown in Figure 18 and Figure 19. Multiplexer setup and hold times with respect to the S/H input can be
determined by these two equations:
tMS (wrt S/H) = tMS − tEOC (min) = 50 − 60 = −10 ns
tMH (wrt S/H) = tMH + tEOC (max) = 50 + 125 = 175 ns
(3)
(4)
Note that tMS (wrt S/H) is a negative number; this indicates that the data on S0 must become valid within 10 ns after
S/H goes low in order to meet the setup time requirements. S0 must be valid for a length of
(tMH + tEOC (max)) − (tMS − tEOC (min)) = 185 ns.
(5)
Table 1 shows how the input channels are assigned:
Table 1. ADC12062 Input
Multiplexer Programming
S0
Channel
0
VIN1
1
VIN2
The output of the multiplexer is available to the user via the MUX OUT pin. This output allows the user to perform
additional signal processing, such as filtering or gain, before the signal is returned to the ADC IN input and
digitized. If no additional signal processing is required, the MUX OUT pin should be tied directly to the ADC IN
pin.
See APPLICATIONS for a simple circuit that will alternate between the two inputs while converting at full speed.
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REFERENCE INPUTS
In addition to the fully differential VREF+ and VREF− reference inputs used on most National Semiconductor ADCs,
the ADC12062 has two sense outputs for precision control of the ladder voltage. These sense inputs
compensate for errors due to IR drops between the reference source and the ladder itself. The resistance of the
reference ladder is typically 750Ω. The parasitic resistance (RP) of the package leads, bond wires, PCB traces,
etc. can easily be 0.5Ω to 1.0Ω or more. This may not be significant at 8-bit or 10-bit resolutions, but at 12 bits it
can introduce voltage drops causing offset and gain errors as large as 6 LSBs.
The ADC12062 provides a means to eliminate this error by bringing out two additional pins that sense the exact
voltage at the top and bottom of the ladder. With the addition of two op amps, the voltages on these internal
nodes can be forced to the exact value desired, as shown in Figure 29.
Figure 29. Reference Ladder Force and Sense Inputs
Since the current flowing through the SENSE lines is essentially zero, there is negligible voltage drop across RS
and the 1 kΩ resistor, so the voltage at the inverting input of the op amp accurately represents the voltage at the
top (or bottom) of the ladder. The op amp drives the FORCE input and forces the voltage at the ends of the
ladder to equal the voltage at the op amps's non-inverting input, plus or minus its input offset voltage. For this
reason op amps with low VOS, such as the LM627 or LM607, should be used for this application. When used in
this configuration, the ADC12062 typically has less than 0.5 LSB of offset and gain error without any user
adjustments.
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The 0.1 μF and 10 μF capacitors on the force inputs provide high frequency decoupling of the reference ladder.
The 500Ω force resistors isolate the op amps from this large capacitive load. The 0.01 μF/1 kΩ network provides
zero phase shift at high frequencies to ensure stability. Note that the op amp supplies in this example must be
±10V to ±15V to meet the input/output voltage range requirements of the LM627 and supply the sub-zero voltage
to the VREF− (FORCE) pin. The VREF/16 output should be by-passed to analog ground with a 0.1 μF ceramic
capacitor.
The reference inputs are fully differential and define the zero to full-scale range of the input signal. They can be
configured to span up to 5V (VREF− = 0V, VREF+ = 5V), or they can be connected to different voltages (within the
0V to 5V limits) when other input spans are required. The ADC12062 is tested at VREF− (SENSE) = 0V, VREF+ (SENSE)
= 4.096V. Reducing the reference voltage span to less than 4V increases the sensitivity (reduces the LSB size)
of the converter; however noise performance degrades when lower reference voltages are used. A plot of
dynamic performance vs reference voltage, Figure 17 is given in TYPICAL PERFORMANCE
CHARACTERISTICS.
If the converter will be used in an application where DC accuracy is secondary to dynamic performance, then a
simpler reference circuit may suffice. The circuit shown in Figure 30 will introduce several LSBs of offset and
gain error, but INL, DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the ADC12062 as possible to minimize noise on the
reference ladder. The VREF/16 output should be bypassed to analog ground with a 0.1 μF ceramic capacitor.
The LM4040 shunt voltage reference is available with a 4.096V output voltage. With initial accuracies as low as
±0.1%, it makes an excellent reference for the ADC12062.
Figure 30. Using the VREF Force Pins Only
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POWER SUPPLY CONSIDERATIONS
The ADC12062 is designed to operate from a single +5V power supply. There are two analog supply pins (AVCC)
and one digital supply pin (DVCC). These pins allow separate external bypass capacitors for the analog and
digital portions of the circuit. To ensure proper operation of the converter, all three supply pins should be
connected to the same voltage source. In systems with separate analog and digital supplies, the converter
should be powered from the analog supply.
The ground pins are AGND (analog ground), DGND1 (digital input ground), and DGND2 (digital output ground).
These pins allow for three separate ground planes for these sections of the chip. Isolating the analog section
from the two digital sections reduces digital interference in the analog circuitry, improving the dynamic
performance of the converter. Separating the digital outputs from the digital inputs (particularly the S/H input)
reduces the possibility of ground bounce from the 12 data lines causing jitter on the S/H input. The analog
ground plane should be connected to the Digital2 ground plane at the ground return for the power supply. The
Digital1 ground plane should be tied to the Digital2 ground plane at the DGND1 and DGND2 pins.
Both AVCC pins should be bypassed to the AGND ground plane with 0.1 μF ceramic capacitors. One of the two
AVCC pins should also be bypassed with a 10 μF tantalum capacitor. DVCC should be bypassed to the DGND2
ground pIane with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor.
LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the ADC12062, it is necessary to use appropriate circuit board
layout techniques. Separate analog and digital ground planes are required to meet datasheet AC and DC limits.
The analog ground plane should be low-impedance and free of noise from other parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the
converter and to ground with short traces. The analog input should be isolated from noisy signal traces to avoid
having spurious signals couple to the input. Any external component (e.g., a filter capacitor) connected across
the converter's input should be connected to a very clean analog ground return point. Grounding the component
at the wrong point will result in increased noise and reduced conversion accuracy.
Figure 31 gives an example of a suitable layout, including power supply routing, ground plane separation, and
bypass capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.) should be
placed on the analog ground plane. All digital circuitry and I/O lines (excluding the S/H input) should use the
digital2 ground plane as ground. The digital1 ground plane should only be used for the S/H signal generation.
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Figure 31. PC Board Layout
DYNAMIC PERFORMANCE
The ADC12062 is AC tested and its dynamic performance is ensured. In order to meet these specifications, the
clock source driving the S/H input must be free of jitter. For the best AC performance, a crystal oscillator is
recommended. For operation at or near the ADC12062's 1 MHz maximum sampling rate, a 1 MHz squarewave
will provide a good signal for the S/H input. As long as the duty cycle is near 50%, the waveform will be low for
about 500 ns, which is within the 550 ns limit. When operating the ADC12062 at a sample rate of 910 kHz or
below, the pulse width of the S/H signal must be smaller than half the sample period.
Figure 32. Crystal Clock Source
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Figure 32 is an example of a low jitter S/H pulse generator that can be used with the ADC12062 and allow
operation at sampling rates from DC to 1 MHz. A standard 4-pin DIP crystal oscillator provides a stable 1 MHz
squarewave. Since most DIP oscillators have TTL outputs, a 4.7k pullup resistor is used to raise the output high
voltage to CMOS input levels. The output is fed to the trigger input (falling edge) of an MM74HC4538 one-shot.
The 1k resistor and 12 pF capacitor set the pulse length to approximately 100 ns. The S/H pulse stream for the
converter appears on the Q output of the HC4538. This is the S/H clock generator used on the ADC12062EVAL
evaluation board. For lower power, a CMOS inverter-based crystal oscillator can be used in place of the DIP
crystal oscillator. See Application Note AN-340 in the Texas Instruments CMOS Logic Databook for more
information on CMOS crystal oscillators.
COMMON APPLICATION PITFALLS
Driving inputs (analog or digital) outside power supply rails. The Absolute Maximum Ratings state that all
inputs must be between GND − 300 mV and VCC + 300 mV. This rule is most often broken when the power
supply to the converter is turned off, but other devices connected to it (op amps, microprocessors) still have
power. Note that if there is no power to the converter, DGND = AGND = DVCC = AVCC = 0V, so all inputs should
be within ±300 mV of AGND and DGND.
Driving a high capacitance digital data bus. The more capacitance the data bus has to charge for each
conversion, the more instantaneous digital current required from DVCC and DGND. These large current spikes
can couple back to the analog section, decreasing the SNR of the converter. While adequate supply bypassing
and separate analog and digital ground planes will reduce this problem, buffering the digital data outputs (with a
pair of MM74HC541s, for example) may be necessary if the converter must drive a heavily loaded databus.
APPLICATIONS
Figure 33. 2's Compliment Output
Figure 34. Ping-Ponging between VIN1 and VIN2
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Figure 35. AC Coupling Bipolar Inputs
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
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