ADC121S021CIMFX/NOPB

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 ADC121S021 Single-Channel, 50- to 200-ksps, 12-Bit A/D Converter 1 Features 3 Description • • • • The ADC121S021 device is a low-power, singlechannel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S021 is fully specified over a sample rate range of 50 ksps to 200 ksps. The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit. 1 • Specified Over a Range of Sample Rates Variable Power Management Single Power Supply With 2.7-V to 5.25-V Range Compatible With the SPI, QSPI, MICROWIRE, and DSP Key Specifications: – DNL: 0.45 and –0.25 LSB (Typical) – INL: 0.45 and –0.4 LSB (Typical) – SNR: 72.3 dB (Typical) – Power Consumption – 3.6-V Supply: 1.5 mW (Typical) – 5.25-V Supply: 7.9 mW (Typical) 2 Applications • • • Portable Systems Remote Data Acquisition Instrumentation and Control Systems The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The ADC121S021 operates with a single supply that can range from 2.7 V to 5.25 V. Normal power consumption using a 3.6-V or 5.25-V supply is 1.5 mW and 7.9 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a 5.25-V supply. The ADC121S021 is packaged in 6-pin WSON and SOT-23 packages. Operation over the industrial temperature range of –40°C to 85°C is ensured. Device Information(1) PART NUMBER ADC121S021 PACKAGE BODY SIZE (NOM) SOT-23 (6) 2.90 mm × 1.60 mm WSON (6) 2.50 mm × 2.20 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Key Graphic VA CS GND VIN SDATA SAR ADC MCU SCLK 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 5 5 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 9.1 Overview ................................................................. 10 9.2 Functional Block Diagram ....................................... 10 9.3 Feature Description................................................. 10 9.4 Device Functional Modes........................................ 10 10 Applications Information .................................... 12 10.1 Application Information.......................................... 12 10.2 Typical Application ................................................ 15 11 Power Supply Recommendations ..................... 17 11.1 Power Supply Noise Considerations..................... 17 12 Layout................................................................... 17 12.1 Layout Guidelines ................................................. 17 12.2 Layout Example .................................................... 17 13 Device and Documentation Support ................. 18 13.1 13.2 13.3 13.4 13.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 19 19 19 19 14 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (January 2014) to Revision J • Added ESD Ratings table,Feature Descriptionsection, Device Functional Modes, Application and Implementation section, Power Supply Recommendationssection, Layoutsection, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section ............................................................................................ 1 Changes from Revision H (March 2013) to Revision I • 2 Page Changed sentence in the "Using the ADC121S021" section ............................................................................................... 13 Changes from Revision G (March 2013) to Revision H • Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 17 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 5 Device Comparison Table (1) SPECIFIED FOR SAMPLE RATE RANGE OF: RESOLUTION (1) 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps 12-bit ADC121S021 ADC121S051 ADC121S101 10-bit ADC101S021 ADC101S051 ADC101S101 8-bit ADC081S021 ADC081S051 ADC081S101 All devices are fully pin and function compatible. 6 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View NGF Package 6-Pin WSON Top View V ! A 1 6 CS GND 2 5 SDATA 3 4 SCLK V IN ! V ! A 1 GND 2 V IN ! PAD 3 6 CS 5 SDATA 4 SCLK See package number DBV0006A. See package number NGF0006A. Pin Functions PIN NAME NO. TYPE DESCRIPTION CS 6 Digital I/O GND 2 PWR Chip select. On the falling edge of CS, a conversion process begins. SCLK 4 Digital I/O Digital clock input. This clock directly controls the conversion and readout processes. SDATA 5 Digital I/O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. VA 1 PWR VIN 3 Analog I/O PAD — PWR The ground return for the supply and signals. Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin. Analog input. This signal can range from 0 V to VA. For package suffix CISD(X) only, TI recommends connecting the center pad to ground. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 3 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Analog supply voltage, VA –0.3 6.5 V Voltage on any digital pin to GND –0.3 6.5 V Voltage on any analog pin to GND –0.3 VA + 0.3 V ±10 mA mA ±20 mA mA Input current at any pin (4) Package input current (4) Power consumption at TA = 25°C See (5) Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) (5) –65 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. All voltages are measured with respect to GND = 0 V, unless otherwise specified. When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The absolute maximum rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax – TA) / RθJA. The values for maximum power dissipation listed above is reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions must always be avoided. 7.2 ESD Ratings VALUE V(ESD) (1) (2) (3) (4) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) ±3500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (3) ±1250 Machine mode (MM) (4) ±300 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. HBM is 100-pF capacitor discharged through a 1.5-kΩ resistor. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Machine model is 220-pF discharged through 0 Ω. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Operating temperature, TA –40 85 °C Supply voltage, VA 2.7 5.25 V –0.3 5.25 V 0 VA V 0.025 20 MHz 1 Msps Digital input pins voltage (2) Analog input pins voltage Clock frequency Sample rate (1) (2) 4 All voltages are measured with respect to GND = 0 V, unless otherwise specified. Regardless of supply voltage Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 7.4 Thermal Information ADC121S021 THERMAL METRIC (1) (2) DBV (SOT-23) NGF (WSON) 6 PINS 6 PINS UNIT 185 83.7 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 156.5 72.1 °C/W RθJB Junction-to-board thermal resistance 29.6 24.8 °C/W ψJT Junction-to-top characterization parameter 33.8 3.4 °C/W ψJB Junction-to-board characterization parameter 29.1 24.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 14.8 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Soldering process must comply with Reflow Temperature Profile specifications. See http://www.ti.com/lit/SNOA549. Reflow temperature profiles are different for lead-free and non-lead-free packages. 7.5 Electrical Characteristics VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 15 pF, unless otherwise noted. Typical limits apply for TA = 25°C; minimum and maximum limits apply for TA = –40°C to 85°C, unless otherwise noted. All limits (1) (2) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CONVERTER CHARACTERISTICS Resolution with no missing codes INL Integral non-linearity TA = –40°C to 85°C VA = 2.7 V to 3.6 V VA = 4.75 V to 5.25 V DNL Differential non-linearity VA = 2.7 V to 3.6 V VA = 4.75 V to 5.25 V VOFF Offset error GE Gain error 12 TA = 25°C –0.4 0.45 –1 1 TA = 25°C –0.4 0.55 TA = 25°C –0.25 0.45 TA = –40°C to 85°C –0.8 1 TA = 25°C –0.3 TA = –40°C to 85°C VA = 2.7 V to 3.6 V VA = 4.75 V to 5.25 V 0.6 –0.18 TA = 25°C ±1.2 –0.26 VA = 2.7 V to 3.6 V VA = 4.75 V to 5.25 V Bits –0.75 TA = 25°C ±1.5 –1.6 LSB LSB LSB LSB LSB LSB DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-noise plus distortion ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 70 72 dBFS SNR Signal-to-noise ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 70.8 72.3 dBFS THD Total harmonic distortion VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS –83 dBFS SFDR Spurious-free dynamic range VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 85 dB ENOB Effective number of bits VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 11.7 Bits Intermodulation distortion, second order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –83 dBFS Intermodulation distortion, third order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –82 dBFS IMD FPBW –3-dB full power bandwidth 11.3 VA = 5 V 11 VA = 3 V 8 MHz ANALOG INPUT CHARACTERISTICS VIN Input range IDCL DC leakage current CINA (1) (2) Input capacitance TA = 25°C 0 –1 Track Mode 30 Hold Mode 4 VA V 1 µA pF Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). Data sheet min/max specification limits are ensured by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 5 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com Electrical Characteristics (continued) VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 15 pF, unless otherwise noted. Typical limits apply for TA = 25°C; minimum and maximum limits apply for TA = –40°C to 85°C, unless otherwise noted. All limits(1)(2)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT CHARACTERISTICS VIH Input high voltage VIL Input low voltage IIN Input current CIND Digital input capacitance VA = 5.25 V TA = –40°C to 85°C 2.4 VA = 3.6 V TA = –40°C to 85°C 2.1 VA = 5 V TA = –40°C to 85°C 0.8 VA = 3 V TA = –40°C to 85°C 0.4 VIN = 0 V or VA V V ±0.1 ±1 µA 2 4 pF DIGITAL OUTPUT CHARACTERISTICS VOH Output high voltage VOL Output low voltage ISOURCE = 200 µA VA – 0.2 ISOURCE = 1 mA ISINK = 200 µA 0.03 ISINK = 1 mA 0.4 V ±0.1 ±10 µA 2 4 pF 5.25 V 0.1 TRI-STATE output capacitance Output coding V VA – 0.1 IOZH, IOZL TRI-STATE® leakage current COUT VA – 0.07 Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS VA Supply voltage Supply current, normal mode (operational, CS low) VA = 5.25 V, fSAMPLE = 200 ksps 1.5 2.8 VA = 3.6 V, fSAMPLE = 200 ksps 0.4 1.2 Supply current, shutdown (CS high) fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 500 fSCLK = 4 MHz, VA = 5.25 V, fSAMPLE= 0 ksps 60 Power consumption, normal mode (operational, CS low) VA = 5.25 V 7.9 14.7 VA = 3.6 V 1.5 4.3 Power consumption, shutdown (CS high) fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 2.6 VA = 5.25 V, fSCLK = 4 MHz, fSAMPLE= 0 ksps 315 IA PD 2.7 mA nA µA mW µW AC ELECTRICAL CHARACTERISTICS fSCLK Clock frequency (3) fS Sample rate (3) DC SCLK duty cycle tACQ Minimum acquisition time tQUIET Minimum quiet time (4) tAD Aperture delay 3 ns tAJ Aperture jitter 30 ps (3) (4) 6 fSCLK = 4 MHz 1 4 MHz 50 200 ksps 40% 50% 60% 350 50 ns ns This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified under Operating Ratings. Required by bus relinquish and the start of the next conversion. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 7.6 Timing Requirements The following specifications apply for VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 1 MHz to 4 MHz, CL = 25 pF, fSAMPLE = 50 ksps to 200 ksps, all limits TA = –40°C to 85°C unless otherwise noted. MIN tCS Minimum CS pulse width 10 tSU CS to SCLK setup time 10 tEN Delay from CS until SDATA TRI-STATE disabled (1) MAX ns VA = 2.7 V to 3.6 V 40 VA = 4.75 V to 5.25 V 20 Data access time after SCLK falling edge (2) tCL SCLK low pulse width 0.4 × tSCLK tCH SCLK high pulse width 0.4 × tSCLK tH SCLK to data valid hold time tDIS tPOWER-UP UNIT ns 20 tACC (1) (2) (3) TYP ns ns ns VA = 2.7 V to 3.6 V 7 VA = 4.75 V to 5.25 V 5 SCLK falling edge to SDATA high impedance (3) VA = 2.7 V to 3.6 V 6 25 VA = 4.75 V to 5.25 V 5 25 Power-up time from full power-down TA = 25°C ns 1 ns µs Measured with the timing test circuit shown in Figure 12 and defined as the time taken by the output signal to cross 1 V. Measured with the timing test circuit shown in Figure 12 and defined as the time taken by the output signal to cross 1 V or 2 V. tDIS is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit shown in Figure 12. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading. Hold Track | CS tCS tSU tACQ tCL 1 2 3 4 12 13 14 15 16 Z1 Z0 DB11 3 leading zero bits 17 18 19 20 tQUIET tCH | Z2 5 tACC tEN SDATA | SCLK tH tDIS TRI-STATE DB3 DB2 DB1 DB0 12 data bits Figure 1. ADC121S021 Serial Timing Diagram Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 7 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com 7.7 Typical Characteristics TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz unless otherwise stated. 8 fSCLK = 1 MHz fSCLK = 1 MHz Figure 2. DNL Figure 3. INL fSCLK = 4 MHz fSCLK = 4 MHz Figure 4. DNL Figure 5. INL Figure 6. DNL vs Clock Frequency Figure 7. INL vs Clock Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 Typical Characteristics (continued) TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz unless otherwise stated. Figure 8. SNR vs Clock Frequency Figure 9. SFDR vs Clock Frequency fSCLK = 4 MHz Figure 10. THD vs Clock Frequency Figure 11. Power Consumption vs Throughput 8 Parameter Measurement Information IOL 200 PA To Output Pin 1.6 V CL 25 pF IOH 200 PA Figure 12. Timing Test Circuit Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 9 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com 9 Detailed Description 9.1 Overview The ADC121S021 is a low-power, single-channel, 12-bit analog-to-digital converter which is based upon a successive-approximation register architecture with an internal track-and-hold circuit. It operates with a single‑supply voltage that can range from 2.7 V to 5.25 V. The ADC121S021 is packaged in 6-pin WSON and SOT-23 package. Operation over the industrial temperature range of –40⁰C to 85⁰C is ensured. 9.2 Functional Block Diagram VIN T/H 12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA 9.3 Feature Description The ADC121S021 is fully specified over a sample rate range of 50 ksps to 200 ksps. Normal power consumption of the device using a 3.6-V or 5.25-V supply is 1.5 mW and 7.9 mW, respectively. The power-down feature helps reduce the power consumption to as low as 2.6 µW using a 5.25-V supply. The output serial data is straight binary, and is compatible with several standards such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces. 9.4 Device Functional Modes The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is pulled high before the 10th falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains low. When in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade off throughput for power consumption, with a sample rate as low as zero. 9.4.1 Normal Mode The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low). If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device remains in normal mode, but the current conversion aborts, and SDATA returns to TRI-STATE (truncating the output word). Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again. 10 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 Device Functional Modes (continued) 9.4.2 Shutdown Mode Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off. To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and 10th falling edges of SCLK, as shown in Figure 13. Once CS has been brought high in this manner, the device enters shutdown mode; the current conversion is aborted and SDATA enters TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device does not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line. Figure 13. Entering Shutdown Mode Figure 14. Entering Normal Mode To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC begins powering up (power-up time is specified in Timing Requirements). This power-up delay results in the first conversion result being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 14. If CS is brought back high before the 10th falling edge of SCLK, the device returns to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC is fully powered up after 16 SCLK cycles. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 11 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com 10 Applications Information NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The ADC121S021 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC121S021 in both track and hold modes are shown in Figure 15 and Figure 16, respectively. In Figure 15, the device is in track mode: switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to the hold mode. Figure 16 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the chargeredistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK. CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 SW2 GND + - CONTROL LOGIC VA 2 Figure 15. ADC121S021 in Track Mode CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 SW2 GND + - CONTROL LOGIC VA 2 Figure 16. ADC121S021 in Hold Mode 10.1.1 Using the ADC121S021 The serial interface timing diagram for the ADC is shown in Figure 1. CS is chip select, which initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream. Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK is labeled with reference to the falling edge of CS; for example, the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low. 12 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 Application Information (continued) At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 1). It is at this point that the interval for the tACQ specification begins. At least 350 ns must pass between the 13th rising edge of SCLK and the next falling edge of CS. The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time (tQUIET) must be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent rising edges of SCLK. The ADC produces three leading zero bits on SDATA, followed by twelve data bits, most significant first. If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK. 10.1.1.1 Determining Throughput Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one conversion and the start of another. At the maximum specified SCLK frequency, the maximum ensured throughput is obtained by using a 20 SCLK frame. As shown in Figure 1, the minimum allowed time between CS falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum required time for Track mode (tACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls. For example, at the fastest rate for this family of parts, SCLK is 20 MHz and 2.5 SCLKs are 125 ns, so the minimum time between CS falling edges is calculated in Equation 1: 12.5 SCLKs + tACQ + 1/2 SCLK = 12.5 × 50 ns + 350 ns + 0.5 × 50 ns = 1000 ns (1) Which corresponds to a maximum throughput of 1 MSPS. At the slowest rate for this family, SCLK is 1 MHz. Using a 20 cycle conversion frame as shown in Figure 1 yields a 20 μs time between CS falling edges for a throughput of 50 KSPS. It is possible, however, to use fewer than 20 clock cycles provided the timing parameters are met. With a 1-MHz SCLK, there are 2500 ns in 2.5 SCLK cycles, which is greater than tACQ. After the last data bit has come out, the clock needs one full cycle to return to a falling edge. Thus the total time between falling edges of CS is 12.5 × 1 μs + 2.5 × 1 μs + 1 × 1 μs = 16 μs which is a throughput of 62.5 ksps. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 13 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com Application Information (continued) 10.1.2 ADC121S021 Transfer Function The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC is VA / 4096. The ideal transfer characteristic is shown in Figure 17. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA / 8192. Other code transitions occur at steps of one LSB. 111...111 111...000 | | ADC CODE 111...110 1 LSB = VA/4096 011...111 000...010 | 000...001 000...000 0V 0.5 LSB ANALOG INPUT +VA-1.5 LSB Figure 17. Ideal Transfer Characteristic 10.1.3 Analog Inputs An equivalent circuit for the ADC's input is shown in Figure 18. Diodes D1 and D2 provide ESD protection for the analog inputs. The analog input must at no time go beyond (VA + 300 mV) or (GND – 300 mV), as these ESD diodes begins to conduct, which could result in erratic operation. For this reason, the ESD diodes must not be used to clamp the input signal. The capacitor C1 in Figure 18 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor R1 is the ON-resistance of the track / hold switch, and is typically 500 Ω. Capacitor C2 is the ADC sampling capacitor and is typically 26 pF. The ADC delivers best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter. VA D1 R1 C2 26 pF VIN C1 4 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure 18. Equivalent Input Circuit 10.1.4 Digital Inputs And Outputs The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The digital input pins are instead limited to 5.25 V with respect to GND, regardless of VA, the supply voltage. This allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage. 14 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 Application Information (continued) 10.1.5 Power Management The ADC takes time to power-up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC performs conversions properly. NOTE The tQUIET time must still be included between the first dummy conversion and the second valid conversion. When the VA supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As such, one dummy conversion must be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode. When the ADC is operated continuously in normal mode, the maximum ensured throughput is fSCLK / 20 at the maximum specified fSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in Typical Characteristics. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. NOTE The curve of power consumption vs throughput is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. 10.2 Typical Application A typical application of the ADC is shown in Figure 19. Power is provided in this example by the Texas Instruments LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply degrades the noise performance of the device. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The three-wire interface is shown connected to a microprocessor or DSP. LP2950 1 PF 0.1 PF 5V 1 PF 0.1 PF VA SCLK VIN ADC121S021 CS SDATA MICROPROCESSOR DSP GND Figure 19. Typical Application Circuit 10.2.1 Design Requirements A positive supply only data acquisition system capable of digitizing signals ranging from 0 V to 5 V and interfacing through SPI with an MCU whose supply is set at 3.3 V. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 15 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com Typical Application (continued) 10.2.2 Detailed Design Procedure The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from the fact that VA is also a reference potential for the ADC. Sampling is in fact a modulation process which may result in aliasing of the input signal if the input signal is not adequately band limited. The maximum sampling rate (fS) of the ADC121S021 when it is enabled is: fS = fSCLK / 16 (2) In order to avoid aliasing, the Nyquist criterion has to be met: BWsignal < fS / 2 (3) Therefore it is necessary to place an anti-aliasing filter at the input of the ADC. This filter may be a single-pole low-pass filter. The pole location need to satisfy Equation 4: 1 / (π × R ×C) < fSCLK / 16 (4) With fSCLK = 4 MHz, a good choice for the single pole filter is: • R = 100 Ω • C = nF This reduces the input BWsignal = 250 kHz. The capacitor at the VIN input of the device provides not only the filtering of the input signal, but it also absorbs the charge kick-back from the ADC. The kick-back is the result of the internal switches opening at the end of the acquisition period. Take care when the signal source is capable of producing voltages beyond VA. In such instances the internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the desired clamping action use Schottky diodes. 10.2.3 Application Curves VA = 5.25 V Figure 20. SINAD vs Clock Frequency 16 Submit Documentation Feedback fSCLK = 4 MHz Figure 21. Spectral Response Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 11 Power Supply Recommendations The ADC requires a single voltage supply within 2.7 V and 5.25 V. 11.1 Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance causes voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, which is resistive. Load discharge currents causes ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100-Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and improve noise performance. 12 Layout 12.1 Layout Guidelines Ground must be a low impedance connection for return currents to flow undisturbed back to their respective sources. Keep connections to the ground plane as short and direct as possible. When using vias to connect to the ground layer, use multiple vias in parallel to reduce impedance to ground. A mixed-signal layout sometimes incorporates separate analog and digital ground planes that are tied together at one location; however, separating the ground planes is not necessary when analog, digital, and power supply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog circuitry. For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. If ground plane separation is necessary, then make the connection at the ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. A single plane for analog and digital ground avoids ground loops. If isolation is required in the application, isolate the digital signals between the ADC and controller, or provide the isolation form the controller to the remaining system. If an external crystal is used to provide the ADC clock, place the crystal and load capacitors directly to the ADC pins using short direct traces. Supply pins must be bypassed with a low-ESR ceramic capacitor. Place the bypass capacitors as close as possible to the supply pins using short, direct traces. For optimum performance, use low-impedance connections on the ground-side connections of the bypass capacitors. Flow the supply current through the bypass capacitor pin first and then to the supply pin to make the bypassing most effective (also known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power supply traces or dedicated power-supply planes to minimize the potential of crosstalk between ADCs. It is important that the SCLK input of the serial interface is free from noise and glitches. Even with relatively slow SCLK frequencies, short digital-signal rise and fall times may cause excessive ringing and noise. For best performance, keep the digital signal traces short, use termination resistors as needed, and ensure all digital signals are routed directly above the ground plane with minimal use of vias. 12.2 Layout Example VA C1 CS SDATA GND VIN SCLK R C2 Figure 22. ADC1210S21 Layout Example Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 17 ADC121S021 SNAS305J – JULY 2005 – REVISED MARCH 2016 www.ti.com 13 Device and Documentation Support 13.1 Device Support 13.1.1 Device Nomenclature ACQUISITION TIME The time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge of CS when the signal is sampled and the part moves from track to hold. The start of the time interval that contains tACQ is the 13th rising edge of SCLK of the previous conversion when the part moves from hold to track. The user must ensure that the time between the 13th rising edge of SCLK and the falling edge of the next CS is not less than tACQ to meet performance specifications. APERTURE DELAY The time after the falling edge of CS to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) The variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CONVERSION TIME The time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. This is from the falling edge of CS when the input signal is sampled to the 16th falling edge of SCLK when the SDATA output goes into TRI-STATE. DIFFERENTIAL NON-LINEARITY (DNL) The measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE The ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) Another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH A measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR The deviation of the last code transition (111...110) to (111...111) from the ideal (VREF – 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) A measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) The creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. MISSING CODES Output codes that never appears at the ADC outputs. The ADC121S021 is ensured not to have any missing codes. OFFSET ERROR The deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) The ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) The ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding DC 18 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 ADC121S021 www.ti.com SNAS305J – JULY 2005 – REVISED MARCH 2016 Device Support (continued) SPURIOUS FREE DYNAMIC RANGE (SFDR) The difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) The ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as: 2 THD = 20 ‡ log10 Af2 + Af1 2 + Af6 2 where • • Af1 is the RMS power of the input frequency at the output Af2 through Af6 are the RMS power in the first 5 harmonic frequencies (5) THROUGHPUT TIME The minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks SPI, QSPI, E2E are trademarks of Texas Instruments. TRI-STATE is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC121S021 19 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC121S021CIMF NRND SOT-23 DBV 6 1000 TBD Call TI Call TI -40 to 85 X07C ADC121S021CIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 X07C ADC121S021CIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 X07C ADC121S021CISD/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 X7C ADC121S021CISDX/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 X7C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of