ADC121S705CIMM

ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 ADC121S705 12-Bit, 500 kSPS to 1 MSPS, Differential Input, Micro Power A/D Converter Check for Samples: ADC121S705 FEATURES DESCRIPTION • • The ADC121S705 is a 12-bit, 500 kSPS to 1 MSPS sampling Analog-to-Digital (A/D) converter that features a fully differential, high impedance analog input and an external reference. The reference voltage can be varied from 1.0V to VA, with a corresponding resolution between 244µV and VA divided by 4096. 1 2 • • • True Differential Inputs Ensured performance from 500 kSPS to 1 MSPS External Reference Wide Input Common-Mode Voltage Range SPI™/QSPI™/MICROWIRE/DSP Compatible Serial Interface APPLICATIONS • • • • • • Automotive Navigation Portable Systems Medical Instruments Instrumentation and Control Systems Motor Control Direct Sensor Interface Operating from a single 5V supply, the supply current when operating at 1 MSPS is typically 2.3 mA. The supply current drops down to 0.3 µA typically when the ADC121S705 enters power-down mode. The ADC121S705 is available in the VSSOP-8 package. Operation is ensured over the industrial temperature range of −40°C to +105°C and clock rates of 8 MHz to 16 MHz. KEY SPECIFICATIONS • • • • • • • The output serial data is binary 2's complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The differential input, low power consumption, and small size make the ADC121S705 ideal for direct connection to transducers in battery operated systems or remote data acquisition applications. Conversion Rate: 500 kSPS to 1 MSPS INL: ± 0.95 LSB (Max) DNL: ±0.95 LSB (Max) Offset Error: ±3.0 LSB (Max) Gain Error: ±6.5 LSB (Max) SINAD: 69.5 db (Min) Power Consumption at VA = 5V – Active, 1 MSPS: 11.5 mW (Typ) – Active, 500 kSPS: 9.0 mW (Typ) – Power-Down: 1.5 µW (Typ) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Connection Diagram VA VREF 1 8 +IN 2 7 SCLK - IN 3 6 DOUT GND 4 5 CS ADC121S705 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Block Diagram SAR CONTROL VREF SERIAL INTERFACE +IN S/H CDAC -IN COMPARATOR PIN DESCRIPTIONS Pin No. 2 Symbol Description 1 VREF Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for enhanced performance. 2 +IN Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the ADC121S705. 3 −IN Inverting Input. −IN is the negative analog input for the differential signal applied to the ADC121S705. 4 GND Ground. GND is the ground reference point for all signals applied to the ADC121S705. 5 CS 6 DOUT Serial Data Output. The conversion result is provided on DOUT. The serial data output word is comprised of 4 null bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of SCLK and is valid on the rising edges. 7 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock. 8 VA Chip Select Bar. CS is active low. The ADC121S705 is in Normal Mode when CS is LOW and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS. Power Supply input. A voltage source between 4.5V and 5.5V must be applied to this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to (VA +0.3V) Voltage on Any Pin to GND Input Current at Any Pin (4) ±10 mA Package Input Current (4) ±50 mA See (5) Power Consumption at TA = 25°C Human Body Model ESD Susceptibility (6) 2500V Machine Model 250v Charge Device Model 750V Junction Temperature +150°C Storage Temperature −65°C to +150°C (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. All voltages are measured with respect to GND = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC121S705 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Operating Ratings (1) (2) −40°C ≤ TA ≤ +105°C Operating Temperature Range Supply Voltage, VA +4.5V to +5.5V Reference Voltage, VREF 1.0V to VA Input Common-Mode Voltage, VCM See Figure 59 Digital Input Pins Voltage Range 0 to VA Clock Frequency 8 MHz to 16 MHz −VREF to +VREF Differential Analog Input Voltage (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. All voltages are measured with respect to GND = 0V, unless otherwise specified. Package Thermal Resistance (1) (2) (1) (2) Package θJA 8-lead VSSOP 200°C / W Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. Reflow temperature profiles are different for lead-free packages. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 3 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com ADC121S705 Converter Electrical Characteristics (1) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 8 to 16 MHz, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Units (2) Typical Limits 12 Bits ±0.6 ±0.95 LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non-Linearity DNL Differential Non-Linearity ±0.4 ±0.95 LSB (max) OE Offset Error −0.4 ±3 LSB (max) Positive Full-Scale Error +0.1 ±2 LSB (max) Negative Full-Scale Error -1.0 ±6 LSB (max) Gain Error +1.0 ±6.5 LSB (max) FSE GE DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz, −0.1 dBFS 72.2 69.5 dBc (min) SNR Signal-to-Noise Ratio fIN = 100 kHz, −0.1 dBFS 72.8 71 dBc (min) THD Total Harmonic Distortion fIN = 100 kHz, −0.1 dBFS −81.6 −72 dBc (max) SFDR Spurious-Free Dynamic Range fIN = 100 kHz, −0.1 dBFS 83.9 72 dBc (min) ENOB Effective Number of Bits fIN = 100 kHz, −0.1 dBFS 11.7 11.25 bits (min) −3 dB Full Power Bandwidth Output at 70.7%FS Differential Input with FS Input Single-Ended Input FPBW 26 MHz 22 MHz ANALOG INPUT CHARACTERISTICS VIN Differential Input Range IDCL DC Leakage Current CINA Input Capacitance CMRR Common Mode Rejection Ratio VREF Reference Voltage Range IREF Reference Current −VREF VIN = VREF or VIN = -VREF V (min) +VREF V (max) ±1 µA (max) In Track Mode 17 pF In Hold Mode 3 pF See Specification Definitions for the test condition 76 dB 1.0 V (min) VA V (max) CS low, fSCLK = 16 MHz, fS = 1 MSPS, output = FF8h 55 µA CS low, fSCLK = 8 MHz, fS = 500 kSPS, output = FF8h 28 µA CS high, fSCLK = 0 0.2 µA DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage 2.6 3.6 V (min) VIL Input Low Voltage 2.5 1.5 V (max) IIN Input Current ±1 µA (max) CIND Input Capacitance 2 4 pF (max) ISOURCE = 200 µA VA − 0.12 VA − 0.2 V (min) ISOURCE = 1 mA VA − 0.16 ISINK = 200 µA 0.01 0.4 V (max) ISINK = 1 mA 0.05 ±1 µA (max) 4 pF (max) VIN = 0V or VA DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA COUT Force 0V or VA TRI-STATE Output Capacitance 2 Output Coding (1) (2) 4 V V Binary 2'S Complement Data sheet min/max specification limits are specified by design, test, or statistical analysis. Tested limits are specified to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 ADC121S705 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 8 to 16 MHz, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units (2) POWER SUPPLY CHARACTERISTICS VA Analog Supply Voltage IVA (Normal) Supply Current, Normal Mode (Operational) IVA (PD) Supply Current, Power Down Mode (CS high) PWR (Normal) Power Consumption, Normal Mode (Operational) PWR (PD) Power Consumption, Power Down Mode (CS high) PSRR Power Supply Rejection Ratio 4.5 V (min) 5.5 V (max) 3 mA (max) fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz 2.3 fSCLK = 8 MHz, fS = 500 kSPS, fIN = 100 kHz 1.8 mA fSCLK = 16 MHz 56 µA (max) fSCLK = 0 (3) 0.3 2 µA (max) fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz, VA = 5.0V 11.5 mW fSCLK = 8 MHz, fS = 500 kSPS, fIN = 100 kHz, VA = 5.0V 9.0 mW fSCLK = 16 MHz, VA = 5.0V 280 µW fSCLK = 0, VA = 5.0V 1.5 µW See the Specification Definitions for the test condition −85 dB AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency fSCLK fS tACQ 20 16 Minimum Clock Frequency 0.8 8 MHz (max) Maximum Sample Rate (4) 1.25 1 MSPS (min) 2.5 SCLK cycles (min) 3.0 SCLK cycles (max) 13 SCLK cycles Track/Hold Acquisition Time tCONV Conversion Time tAD Aperture Delay (3) (4) See Specification Definitions 6 MHz (min) ns Data sheet min/max specification limits are specified by design, test, or statistical analysis. While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/16. ADC121S705 Timing Specifications (1) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 8 MHz to 16 MHz, CL = 25 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol (1) (2) Parameter Conditions Typical Limits Units 5 ns (min) 5 ns (min) 2.5 ns (min) tCSH CS Hold Time after an SCLK rising edge tCSSU CS Setup Time prior to an SCLK rising edge tDH DOUT Hold time after an SCLK Falling edge 7 18 22 ns (max) 20 ns (max) 20 ns (max) tDA DOUT Access time after an SCLK Falling edge tDIS DOUT Disable Time after the rising edge of CS (2) tEN DOUT Enable Time after the falling edge of CS tCH SCLK High Time 25 ns (min) tCL SCLK Low Time 25 ns (min) tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns 8 Data sheet min/max specification limits are specified by design, test, or statistical analysis. tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 5 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Timing Diagrams tCONV tACQ tPWRDWN CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK tCH tCL tDIS tEN DB11 DB10 DB9 DOUT DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HI-Z HI-Z LSB MSB Figure 1. ADC121S705 Single Conversion Timing Diagram tACQ tCONV tACQ tPD tCONV CS 1 2 3 4 5 6 7 8 9 DB8 DB7 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 SCLK DOUT DB11 DB10 DB9 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 LSB MSB DB8 HI-Z MSB Figure 2. ADC121S705 Continuous Conversion Timing Diagram 3.5V DOUT IOL 2 mA 1.0V tf tr TO OUTPUT PIN 1.6V CL 25 pF IOH 2 mA Figure 3. Timing Test Circuit Figure 4. Rise and Fall Times SCLK SCLK 1 2 VIL tCSH tDA tCSSU 3.5V DOUT CS 1.0V tDH Figure 5. Hold and Access Times Figure 6. Valid CS Assertion Times CS VIH 90% 90% DOUT 10% tDIS 90% DOUT 10% 10% Figure 7. Voltage Waveform for tDIS 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. CMRR = 20 LOG ( Δ Common Input / Δ Output Offset) (1) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive Full-Scale Error and Negative Full-Scale Error and can be calculated as: Gain Error = Positive Full-Scale Error − Negative Full-Scale Error (2) INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S705 is ensured not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from negative full scale to the next code and −VREF + 0.5 LSB OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 000h to 001h and 1/2 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and VREF minus 1.5 LSB. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the ADC121S705, VA is changed from 4.5V to 5.5V. PSRR = 20 LOG (ΔOffset / ΔVA) (3) SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 7 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as THD = 20 ‡ log10 A f 22 + + A f 62 A f 12 (4) where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. 8 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. DNL - 1 MSPS INL - 1 MSPS Figure 8. Figure 9. DNL vs. VA INL vs. VA Figure 10. Figure 11. OFFSET ERROR vs. VA GAIN ERROR vs. VA Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 9 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. 10 DNL vs. VREF INL vs. VREF Figure 14. Figure 15. OFFSET ERROR vs. VREF GAIN ERROR vs. VREF Figure 16. Figure 17. DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. OFFSET ERROR vs. SCLK FREQUENCY GAIN ERROR vs. SCLK FREQUENCY Figure 20. Figure 21. DNL vs. SCLK DUTY CYCLE INL vs. SCLK DUTY CYCLE Figure 22. Figure 23. OFFSET ERROR vs. SCLK DUTY CYCLE GAIN ERROR vs. SCLK DUTY CYCLE Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 11 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. 12 DNL vs. TEMPERATURE INL vs. TEMPERATURE Figure 26. Figure 27. OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE Figure 28. Figure 29. SNR vs. VA THD vs. VA Figure 30. Figure 31. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. SINAD vs. VA SFDR vs. VA Figure 32. Figure 33. SNR vs. VREF THD vs. VREF Figure 34. Figure 35. SINAD vs. VREF SFDR vs. VREF Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 13 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. 14 SNR vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY Figure 38. Figure 39. SINAD vs. SCLK FREQUENCY SFDR vs. SCLK FREQUENCY Figure 40. Figure 41. SNR vs. SCLK DUTY CYCLE THD vs. SCLK DUTY CYCLE Figure 42. Figure 43. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. SINAD vs. SCLK DUTY CYCLE SFDR vs. SCLK DUTY CYCLE Figure 44. Figure 45. SNR vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY Figure 46. Figure 47. SINAD vs. INPUT FREQUENCY SFDR vs. INPUT FREQUENCY Figure 48. Figure 49. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 15 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. 16 SNR vs. TEMPERATURE THD vs. TEMPERATURE Figure 50. Figure 51. SINAD vs. TEMPERATURE SFDR vs. TEMPERATURE Figure 52. Figure 53. SUPPLY CURRENT vs. SCLK FREQUENCY SUPPLY CURRENT vs. TEMPERATURE Figure 54. Figure 55. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 100 kHz unless otherwise stated. REF. CURRENT vs. SCLK FREQUENCY REF. CURRENT vs. TEMPERATURE Figure 56. Figure 57. SPECTRAL RESPONSE - 1 MSPS Figure 58. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 17 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Functional Description The ADC121S705 analog-to-digital converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sample/hold function. The architecture and process allow the ADC121S705 to acquire and convert an analog signal at sample rates up to 1 MSPS while consuming very little power. The ADC121S705 requires an external reference, external clock, and a single +5V power source that can be as low as +4.5V. The external reference can be any voltage between 1V and VA. The value of the reference voltage determines the range of the analog input, while the reference input current depends upon the conversion rate. The external clock can take on values as indicated in the Electrical Characteristics of this data sheet. The duty cycle of the clock is essentially unimportant, provided the minimum clock high and low times are met. The minimum clock frequency is set by internal capacitor leakage. Each conversion requires 16 SCLK cycles to complete. If less than 12 bits of conversion data are required, CS can be brought high at any point during the conversion. This procedure of terminating a conversion prior to completion is often referred to as short cycling. The analog input is presented to the two input pins: +IN and –IN. Upon initiation of a conversion, the differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry while a conversion is in progress. The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in progress. With CS held low after the conversion is complete, the ADC121S705 continuously converts the analog input. The digital data on DOUT can be clocked into the receiving device on the SCLK rising edges. See Serial Digital Interface and Timing Diagrams for more information. REFERENCE INPUT The externally supplied reference voltage sets the analog input range. The ADC121S705 will operate with a reference voltage in the range of 1V to VA. As the reference voltage is reduced, the range of input voltages corresponding to each digital output code is reduced. That is, a smaller analog input range corresponds to one LSB (Least Significant Bit). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes below the noise floor of the ADC121S705, the noise will span an increasing number of codes and overall performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D converter will increase in terms of LSB size as the reference voltage is reduced. The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the input is sampled. Hence, the only current required at the reference and at the analog inputs is a series of transient spikes. Lower reference voltages will decrease the current pulses at the reference input and will slightly decrease the average input current. The reference current changes only slightly with temperature. See Figure 56 and Figure 57 in Typical Performance Characteristics for additional details. 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 ANALOG SIGNAL INPUTS The ADC121S705 has a differential input, and the effective input voltage that is digitized is (+IN) − (−IN). As is the case with all differential input A/D converters, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. Yet, the ADC121S705 can be presented with a single-ended input. The current required to recharge the input sampling capacitor will cause voltage spikes at +IN and −IN. Do not try to filter out these noise spikes. Rather, ensure that the transient settles out during the acquisition period (three SCLK cycles after the fall of CS). Differential Input Operation With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be obtained when (+IN) − (−IN) ≥ VREF − 1.5 LSB. A negative full scale code (1000 0000 0000b or 800h) will be obtained when (+IN) − (−IN) ≤ −VREF + 0.5 LSB. This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will determine any given output code. Single-Ended Input Operation For single-ended operation, the non-inverting input (+IN) of the ADC121S705 should be driven with a signal or voltages that have a maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting input (−IN) should be biased at a stable voltage that is halfway between these maximum and minimum values. Since the design of the ADC121S705 is optimized for a differential input, the performance degrades slightly when driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and dynamic characteristics such as SINAD typically degrades by 2 dB. Note that single-ended operation should only be used if the performance degradation (compared with differential operation) is acceptable. Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC121S705. The ranges of VCM are depicted in Figure 59 and Figure 60. The minimum and maximum common mode voltages for differential and single-ended operation are shown in Table 1. 6 6 Single-Ended Input 5 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) Differential Input VA = 5.0V 3.75 2.5 1.25 0 -1 0.0 1.0 2.0 2.5 3.0 4.0 5 VA = 5.0V 3.75 2.5 1.25 0 -1 0.0 5.0 0.75 VREF (V) 1.25 1.75 2.5 VREF (V) Figure 59. VCM range for Differential Input operation Figure 60. VCM range for single-ended operation Table 1. Allowable VCM Range Input Signal Differential Single-Ended Minimum VCM Maximum VCM VREF / 2 VA − VREF / 2 VREF VA − VREF Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 19 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com SERIAL DIGITAL INTERFACE The ADC121S705 communicates via a synchronous 3-wire serial interface as shown in Timing Diagrams. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC121S705's DOUT pin is in a high impedance state when CS is high and is active when CS is low; thus CS acts as an output enable. During the first three cycles of SCLK, the ADC121S705 is in acquisition mode (tACQ), acquiring the input voltage. For the next thirteen SCLK cycles (tCONV), the conversion is accomplished and the data is clocked out. SCLK falling edges one through four clock out leading zeros while falling edges five through sixteen clock out the conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the ADC121S705 will re-enter acquisition mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter the conversion mode on the N*16+4th falling edge of SCLK as shown in Figure 2. "N" is an integer value. The ADC121S705 can enter acquisition mode under three different conditions. The first condition involves CS going low (asserted) with SCLK high. In this case, the ADC121S705 enters acquisition mode on the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the ADC121S705 automatically enters acquisition mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC121S705 enters acquisition mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 6 for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. CS Input The CS (chip select bar) input is CMOS compatible and is active low. The ADC121S705 is in normal mode when CS is low and power-down mode when CS is high. CS frames the conversion window. The falling edge of CS marks the beginning of a conversion and the rising of CS marks the end of a conversion window. Multiple conversions can occur within a given conversion frame with each conversion requiring sixteen SCLK cycles. SCLK Input The SCLK (serial clock) is used as the conversion clock and to clock out the conversion results. This input is CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC121S705 offers ensured performance with the clock rates indicated in the electrical table. Data Output The output data format of the ADC121S705 is two’s complement, as shown in Table 2. This table indicates the ideal output code for the given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data output bit is sent on the falling edge of SCLK. While most receiving systems will capture the digital output bits on the rising edge of SCLK, the falling edge of SCLK may be used to capture each bit if the minimum hold time (tDH) for DOUT is acceptable. See Figure 5 for DOUT hold and access times. DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new conversion will begin when CS is taken LOW. Table 2. Ideal Output Code vs. Input Voltage Description Analog Input, (+IN) − (−IN) 2's Complement Binary Output 2's Comp. Hex Code VREF − 1.5 LSB 0111 1111 1111 7FF + Full Scale Midscale Midscale − 1 LSB − Full Scale 20 0V 0000 0000 0000 000 0V − 1 LSB 1111 1111 1111 FFF −VREF − 0.5 LSB 1000 0000 0000 800 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 APPLICATIONS INFORMATION OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC121S705: −40°C ≤ TA ≤ +105°C +4.5V ≤ VA ≤ +5.5V 1V ≤ VREF ≤ VA 8 MHz ≤ fCLK ≤ 16 MHz VCM: See Input Common Mode Voltage POWER CONSUMPTION The architecture, design, and fabrication process allow the ADC121S705 to operate at conversion rates up to 1 MSPS while consuming very little power. The ADC121S705 consumes the least amount of power while operating in power down mode. For applications where power consumption is critical, the ADC121S705 should be operated in power down mode as often as the application will tolerate. To further reduce power consumption, stop the SCLK while CS is high. Short Cycling Another way of saving power is to short cycle the conversion process. This is done by pulling CS high after the last required bit is received from the ADC121S705 output. This is possible because the ADC121S705 places the latest converted data bit on DOUT as it is generated. If only 8-bits of the conversion result are needed, for example, the conversion can be terminated by pulling CS high after the 8th bit has been clocked out. Halting the conversion after the last needed bit is outputted is called short cycling. Short cycling can be used to lower the power consumption in those applications that do not need a full 12-bit resolution, or where an analog signal is being monitored until some condition occurs. For example, it may not be necessary to use the full 12-bit resolution of the ADC121S705 as long as the signal being monitored is within certain limits. In some circumstances, the conversion could be terminated after the first few bits. This will lower power consumption in the converter since the ADC121S705 spends more time in power down mode and less time in the conversion mode. Burst Mode Operation Normal operation of the ADC121S705 requires the SCLK frequency to be sixteen times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 500 kSPS, the ADC121S705 should be run with an SCLK frequency of 16 MHz and a CS rate as slow as the system requires. When this is accomplished, the ADC121S705 is operating in burst mode. The ADC121S705 enters into power down mode at the end of each conversion, minimizing power consumption. This causes the converter to spend the longest possible time in power down mode. Since power consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. TIMING CONSIDERATIONS Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and characteristics of the individual device. To ensure that the data is always clocked out at a given time (the 5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the Timing Specifications. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 21 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com PCB LAYOUT AND CIRCUIT CONSIDERATIONS For best performance, care should be taken with the physical layout of the printed circuit board. This is especially true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out before the conversion begins. Power Supply Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the ADC121S705 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor should be used to bypass the ADC121S705 supply, with the 0.1 µF capacitor placed as close to the ADC121S705 package as possible. Voltage Reference The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the ADC121S705 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference input that must settle out while SCLK is high. Since these transient spikes can be as high as 20 mA, it is important that the reference circuit be capable of providing this much current and settle out during the first three clock periods (acquisition time). The reference input of the ADC121S705, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results. The use of an active reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are excellent choices for a reference source. Power and Ground Planes A single ground plane and the use of two or more power planes is recommended. The power planes should all be in the same board layer and will define the analog, digital, and high power board areas. Lines associated with these areas should always be routed within their respective areas. The GND pin on the ADC121S705 should be connected to the ground plane at a quiet point. Avoid connecting the GND pin too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device. 22 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 ADC121S705 www.ti.com SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 APPLICATION CIRCUITS The following figures are examples of the ADC121S705 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. Data Acquisition Figure 61 shows a basic low cost, low power data acquisition circuit. Maximum clock rate with a minimum sample rate can reduce the power consumption further. +5V 5: to 10: + 2 k: ADC121S705 + LM4040-2.5 10 PF VREF VA + 1.0 PF to 4.7 PF 0.1 PF 4.7 PF +IN SCLK - IN DOUT GND CSB Microcontroller Figure 61. Low cost, low power Data Acquisition System Pressure Sensor Figure 62 shows an example of interfacing a pressure sensor to the ADC121S705. A digital-to-analog converter (DAC) is used to bias the pressure sensor. The DAC081S101 provides a means for dynamically adjusting the sensitivity of the sensor. A shunt reference voltage of 2.5V is used as the reference for the ADC121S705. The ADC121S705, DAC081S101, and the LM4040 are all powered from the same voltage source. VA LMP7701 DAC081S101 + - 470 pF 200 k: VA SCLK ADC121S705 REF Pressure Sensor 0.2 mV/PSI + LMP7701 DIN 180 : 2 k: 200 k: SYNCB 180 : DOUT CSB VA 470 pF AV = 100 V/V MicroController SCLK 2 k: 1 uF LM4040-2.5 Figure 62. Interfacing the ADC121S705 for a Pressure Sensor Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 23 ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision A (March 2013) to Revision B • 24 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADC121S705CIMM/NOPB NRND VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM 0 to 0 X1AC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of