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ADC128S102
SNAS298G – AUGUST 2005 – REVISED JANUARY 2015
ADC128S102 8-Channel, 500-ksps to 1-Msps, 12-Bit A/D Converter
1 Features
3 Description
•
•
•
•
•
•
The ADC128S102 is a low-power, eight-channel
CMOS 12-bit analog-to-digital converter specified for
conversion throughput rates of 500 ksps to 1 MSPS.
The converter is based on a successiveapproximation register architecture with an internal
track-and-hold circuit. It can be configured to accept
up to eight input signals at inputs IN0 through IN7.
1
Eight Input Channels
Variable Power Management
Independent Analog and Digital Supplies
SPI/QSPI™/MICROWIRE™/DSP Compatible
Packaged in 16-Lead TSSOP
Key Specifications
– Conversion Rate 500 ksps to 1 MSPS
– DNL (VA = VD = 5.0 V) +1.5 / −0.9
– LSB (maximum) INL (VA = VD = 5.0 V) ±1.2
LSB (maximum)
– Power Consumption
– 3V Supply 2.3 mW (typical)
– 5V Supply 10.7 mW (typical)
The output serial data is straight binary and is
compatible with several standards, such as SPI,
QSPI, MICROWIRE, and many common DSP serial
interfaces.
The ADC128S102 may be operated with independent
analog and digital supplies. The analog supply (VA)
can range from +2.7 V to +5.25 V, and the digital
supply (VD) can range from +2.7 V to VA. Normal
power consumption using a +3-V or +5-V supply is
2.3 mW and 10.7 mW, respectively. The power-down
feature reduces the power consumption to 0.06 µW
using a +3-V supply and 0.25 µW using a +5-V
supply.
2 Applications
•
•
•
•
•
Automotive Navigation
Portable Systems
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
The ADC128S102 is packaged in a 16-lead TSSOP
package. Operation over the extended industrial
temperature range of −40°C to +105°C is ensured.
Device Information(1)
PART NUMBER
ADC128S102
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
“Analog” Supply Rail
VA is used as the Reference
for the ADC
VD can be set independently
of VA
VA
VIN7
“Digital” Supply Rail
VD
IN7
IN6
IN4
VIN3
CONTROLLER
IN5
SAR
ADC
IN3
4-wire SPI
MCU
IN2
IN1
VIN0
IN0
AGND
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC128S102
SNAS298G – AUGUST 2005 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Specifications ...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
7.5 Programming........................................................... 16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9
Power Supply Recommendations...................... 20
9.1 Power Supply Sequence......................................... 20
9.2 Power Supply Noise Considerations....................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2013) to Revision G
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision D (March 2013) to Revision E
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 20
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
CS
1
16
SCLK
VA
2
15
DOUT
AGND
3
14
DIN
IN0
4
13
VD
IN1
5
12
DGND
ADC128S102
IN2
6
11
IN7
IN3
7
10
IN6
IN4
8
9
IN5
Pin Functions
PIN
NO.
NAME
3
AGND
1
CS
12
DGND
14
DIN
15
DOUT
4 - 11
I/O
Supply
IN
Supply
DESCRIPTION
The ground return for the analog supply and signals.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long
as CS is held low.
The ground return for the digital supply and signals.
IN
Digital data input. The ADC128S102's Control Register is loaded through this pin on rising edges of
the SCLK pin.
OUT
Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK
pin.
IN0 to IN7
IN
Analog inputs. These signals can range from 0 V to VREF.
16
SCLK
IN
Digital clock input. The ensured performance range of frequencies for this input is 8 MHz to 16 MHz.
This clock directly controls the conversion and readout processes.
2
VA
Supply
Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be
connected to a quiet +2.7-V to +5.25-V source and bypassed to GND with 1-µF and 0.1-µF
monolithic ceramic capacitors located within 1 cm of the power pin.
13
VD
Supply
Positive digital supply pin. This pin should be connected to a +2.7 V to VA supply, and bypassed to
GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1) (2)
.
MIN
MAX
UNIT
Analog Supply Voltage VA
−0.3
6.5
V
Digital Supply Voltage VD
−0.3
VA + 0.3, max 6.5
V
Voltage on Any Pin to GND
−0.3
VA +0.3
V
(3)
–10
10
mA
Input Current at Any Pin
Package Input Current (3)
–20
20
Power Dissipation at TA = 25°C
See
Junction Temperature
−65
Storage temperature, Tstg
mA
(4)
150
°C
150
°C
For soldering specifications: see product folder at www.ti.com and SNOA549
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. In the 16-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum
operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12
mW. The values for maximum power dissipation listed above will be reached only when the ADC128S102 is operated in a severe fault
condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2500
Machine model (MM)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Operating Temperature, TA
–40
105
°C
VA Supply Voltage
2.7
5.25
V
VD Supply Voltage
2.7
VA
V
Digital Input Voltage
0
VA
V
Analog Input Voltage
0
VA
V
Clock Frequency
8
16
MHz
(1)
4
All voltages are measured with respect to GND = 0V, unless otherwise specified.
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6.4 Thermal Information
ADC128S102
THERMAL METRIC (1)
PW
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
110
RθJC(top)
Junction-to-case (top) thermal resistance
42
RθJB
Junction-to-board thermal resistance
56
ψJT
Junction-to-top characterization parameter
5
ψJB
Junction-to-board characterization parameter
55
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1
MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (2)
UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing
Codes
Integral Non-Linearity (End Point VA = VD = +3.0V
Method)
VA = VD = +5.0V
INL
VA = VD = +3.0V
DNL
Differential Non-Linearity
VA = VD = +5.0V
VOFF
Offset Error
OEM
Offset Error Match
FSE
FSEM
Full Scale Error
Full Scale Error Match
–1
–1.2
−0.7
12
Bits
±0.4
1
LSB
±0.5
1.2
LSB
+0.4
0.9
LSB
−0.2
+0.7
LSB
1.5
LSB
−0.9
−0.4
VA = VD = +3.0V
–2.3
+0.8
2.3
LSB
VA = VD = +5.0V
–2.3
+1.1
2.3
LSB
VA = VD = +3.0V
–1.5
±0.1
1.5
LSB
VA = VD = +5.0V
–1.5
±0.3
1.5
LSB
VA = VD = +3.0V
–2.0
+0.8
2.0
LSB
VA = VD = +5.0V
–2.0
+0.3
2.0
LSB
VA = VD = +3.0V
–1.5
±0.1
1.5
LSB
VA = VD = +5.0V
–1.5
±0.3
1.5
LSB
LSB
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
SINAD
SNR
THD
(1)
(2)
Full Power Bandwidth (−3dB)
Signal-to-Noise Plus Distortion
Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
VA = VD = +3.0V
8
MHz
VA = VD = +5.0V
11
MHz
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
70
73
dB
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
70
73
dB
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
70.8
73
dB
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
70.8
73
dB
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
−88
−74
dB
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
−90
−74
dB
Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Electrical Characteristics (continued)
The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1
MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX.(1)
PARAMETER
SFDR
Spurious-Free Dynamic Range
ENOB
Effective Number of Bits
ISO
Channel-to-Channel Isolation
Intermodulation Distortion,
Second Order Terms
IMD
Intermodulation Distortion, Third
Order Terms
TEST CONDITIONS
MAX (2)
MIN
TYP
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
UNIT
75
91
dB
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
75
92
dB
VA = VD = +3.0V,
fIN = 40.2 kHz
11.3
11.8
Bits
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
11.3
11.8
Bits
VA = VD = +3.0V,
fIN = 20 kHz
82
dB
VA = VD = +5.0V,
fIN = 20 kHz, −0.02 dBFS
84
dB
VA = VD = +3.0V,
fa = 19.5 kHz, fb = 20.5 kHz
−89
dB
VA = VD = +5.0V,
fa = 19.5 kHz, fb = 20.5 kHz
−91
dB
VA = VD = +3.0V,
fa = 19.5 kHz, fb = 20.5 kHz
−88
dB
VA = VD = +5.0V,
fa = 19.5 kHz, fb = 20.5 kHz
−88
dB
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
IDCL
DC Leakage Current
CINA
Input Capacitance
0 to VA
–1
V
1
µA
Track Mode
33
pF
Hold Mode
3
pF
DIGITAL INPUT CHARACTERISTICS
VA = VD = +2.7V to +3.6V
2.1
VA = VD = +4.75V to +5.25V
2.4
VIH
Input High Voltage
VIL
Input Low Voltage
VA = VD = +2.7V to +5.25V
IIN
Input Current
VIN = 0V or VD
CIND
Digital Input Capacitance
–1
V
V
0.8
V
±0.01
1
µA
2
4
pF
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
ISOURCE = 200 µA,
VA = VD = +2.7V to +5.25V
VOL
Output Low Voltage
ISINK = 200 µA to 1.0 mA,
VA = VD = +2.7V to +5.25V
IOZH, IOZL
Hi-Impedance Output Leakage
Current
VA = VD = +2.7V to +5.25V
COUT
Hi-Impedance Output
Capacitance (1)
VD − 0.5
V
–1
2
Output Coding
0.4
V
1
µA
4
pF
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
VA, VD
6
Analog and Digital Supply
Voltages
VA ≥ VD
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2.7
5.25
V
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Electrical Characteristics (continued)
The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1
MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX.(1)
TYP
MAX (2)
VA = VD = +2.7V to +3.6V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
0.76
1.5
mA
VA = VD = +4.75V to +5.25V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
2.13
3.1
mA
PARAMETER
Total Supply Current
Normal Mode ( CS low)
IA + ID
Total Supply Current
Shutdown Mode (CS high)
Power Consumption
Normal Mode ( CS low)
PC
Power Consumption
Shutdown Mode (CS high)
TEST CONDITIONS
MIN
UNIT
VA = VD = +2.7V to +3.6V,
fSCLK = 0 ksps
20
nA
VA = VD = +4.75V to +5.25V,
fSCLK = 0 ksps
50
nA
VA = VD = +3.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
2.3
4.5
mW
VA = VD = +5.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
10.7
15.5
mW
VA = VD = +3.0V
fSCLK = 0 ksps
0.06
µW
VA = VD = +5.0V
fSCLK = 0 ksps
0.25
µW
AC ELECTRICAL CHARACTERISTICS
fSCLKMIN Minimum Clock Frequency
VA = VD = +2.7V to +5.25V
fSCLK
Maximum Clock Frequency
VA = VD = +2.7V to +5.25V
fS
Sample Rate
Continuous Mode
VA = VD = +2.7V to +5.25V
tCONVERT Conversion (Hold) Time
VA = VD = +2.7V to +5.25V
DC
SCLK Duty Cycle
VA = VD = +2.7V to +5.25V
tACQ
Acquisition (Track) Time
VA = VD = +2.7V to +5.25V
Throughput Time
Acquisition Time + Conversion Time
VA = VD = +2.7V to +5.25V
Aperture Delay
VA = VD = +2.7V to +5.25V
tAD
8
500
0.8
MHz
16
MHz
1
MSPS
50
ksps
13 SCLK cycles
40%
30
70
60%
3 SCLK cycles
16 SCLK cycles
4
ns
6.6 Timing Specifications
The following specifications apply for TA = 25°C, VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz,
fSAMPLE = 500 ksps to 1 MSPS, and CL = 50pF. MIN and MAX apply for TA = TMIN to TMAX.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
tCSH
CS Hold Time after SCLK Rising Edge
10
0
tCSS
CS Setup Time prior to SCLK Rising Edge
10
4.5
tEN
CS Falling Edge to DOUT enabled
tDACC
DOUT Access Time after SCLK Falling Edge
tDHLD
DOUT Hold Time after SCLK Falling Edge
tDS
DIN Setup Time prior to SCLK Rising Edge
tDH
DIN Hold Time after SCLK Rising Edge
tCH
SCLK High Time
0.4 x
tSCLK
ns
tCL
SCLK Low Time
0.4 x
tSCLK
ns
tDIS
CS Rising Edge to DOUT High-Impedance
(1)
ns
ns
5
30
ns
17
27
ns
4
ns
10
3
ns
10
3
ns
DOUT falling
2.4
20
ns
DOUT rising
0.9
20
ns
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Power
Down
Power Up
Track
Power Up
Hold
Track
Hold
CS
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
1
16
2
3
4
5
6
7
8
SCLK
Control register
DIN
DOUT
ADD2 ADD1 ADD0
ADD2 ADD1
DB11 DB10 DB9
FOUR ZEROS
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
FOUR ZEROS
DB0
ADD0
DB11 DB10 DB9
Figure 1. ADC128S102 Operational Timing Diagram
CS
tCONVERT
tACQ
tCH
SCLK
1
2
3
4
5
6
7
tCL
tEN
DOUT
8
16
tDACC
DB11
FOUR ZEROS
DB10
tDHLD
DB9
DB8
tDIS
DB1
DB0
tDH
tDS
DONTC
DIN
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Figure 2. ADC128S102 Serial Timing Diagram
SCLK
tCSS
CS
tCSH
CS
Figure 3. SCLK and CS Timing Parameters
8
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6.7 Typical Characteristics
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 4. DNL
Figure 5. DNL
Figure 6. INL
Figure 7. INL
Figure 8. DNL vs. Supply
Figure 9. INL vs. Supply
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
10
Figure 10. SNR vs. Supply
Figure 11. THD vs. Supply
Figure 12. ENOB vs. Supply
Figure 13. DNL vs. VD with VA = 5.0 V
Figure 14. INL vs. VD with VA = 5.0 V
Figure 15. DNL vs. SCLK Duty Cycle
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 16. INL vs. SCLK Duty Cycle
Figure 17. SNR vs. SCLK Duty Cycle
Figure 18. THD vs. SCLK Duty Cycle
Figure 19. ENOB vs. SCLK Duty Cycle
Figure 20. DNL vs. SCLK
Figure 21. INL vs. SCLK
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
12
Figure 22. SNR vs. SCLK
Figure 23. THD vs. SCLK
Figure 24. ENOB vs. SCLK
Figure 25. DNL vs. Temperature
Figure 26. INL vs. Temperature
Figure 27. SNR vs. Temperature
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 28. THD vs. Temperature
Figure 29. ENOB vs. Temperature
Figure 30. SNR vs. Input Frequency
Figure 31. THD vs. Input Frequency
Figure 32. ENOB vs. Input Frequency
Figure 33. Power Consumption vs. SCLK
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7 Detailed Description
7.1 Overview
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter.
7.2 Functional Block Diagram
IN0
.
.
.
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VA
AGND
AGND
IN7
VD
SCLK
ADC128S102
CONTROL
LOGIC
CS
DIN
DOUT
DGND
7.3 Feature Description
7.3.1 ADC128S102 Operation
Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 34 and Figure 35
respectively. In Figure 34, the ADC128S102 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC128S102 is in this state for the first three SCLK cycles after CS is brought low.
Figure 35 shows the ADC128S102 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC128S102 is in this state for the last thirteen SCLK cycles
after CS is brought low.
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
IN7
SAMPLING
CAPACITOR
SW1
SW2
CONTRO
L
LOGI
C
+
-
AGND
VA /2
Figure 34. ADC128S102 in Track Mode
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Feature Description (continued)
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
+
SW1
IN7
SW2
-
CONTROL
LOGIC
AGND
VA /2
Figure 35. ADC128S102 in Hold Mode
7.3.2 ADC128S102 Transfer Function
The output format of the ADC128S102 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC128S102 is VA / 4096. The ideal transfer characteristic is shown
in Figure 36. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of VA / 8192. Other code transitions occur at steps of one LSB.
111...111
111...000
|
|
ADC CODE
111...110
1LSB = VA/4096
011...111
000...010
|
000...001
000...000
0V
0.5LSB
ANALOG INPUT
+VA - 1.5LSB
Figure 36. Ideal Transfer Characteristic
7.3.3 Analog Inputs
An equivalent circuit for one of the ADC128S102's input channels is shown in Figure 37. Diodes D1 and D2
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going
beyond this range will cause the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 37 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the
ADC128S102 sampling capacitor, and is typically 30 pF. The ADC128S102 will deliver best performance when
driven by a low-impedance source (less than 100 ohms). This is especially important when using the
ADC128S102 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or lowpass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing
filters.
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Feature Description (continued)
VA
D1
R1
C2
30 pF
VIN
C1
3 pF
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 37. Equivalent Input Circuit
7.3.4 Digital Inputs and Outputs
The ADC128S102's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone
to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT)
operating range is controlled by VD. The output high voltage is VD - 0.5V (min) while the output low voltage is
0.4V (max).
7.4 Device Functional Modes
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with
one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down
mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent
conversion (see Figure 1).
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS
is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical
specifications. The Power Consumption vs. SCLK curve in the Typical Characteristics section shows the typical
power consumption of the ADC128S102. To calculate the power consumption (PC), simply multiply the fraction of
time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction of time
spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Equation 1.
PC =
tS
tN
x PN +
x PS
tN + t S
tN + t S
(1)
7.5 Programming
7.5.1 Serial Interface
An operational timing diagram and a serial interface timing diagram for the ADC128S102 are shown in the
Timing Specifications section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC128S102's
Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
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Programming (continued)
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than
one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling
edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling
edge of SCLK. "N" is an integer value.
The ADC128S102 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters
track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 3 for
setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next input for conversion is clocked into a control register
through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1, Table 2, and Table 3.
There is no need to incorporate a power-up delay or dummy conversions as the ADC128S102 is able to acquire
the input signal to full resolution in the first conversion immediately following power-up. The first conversion result
after power-up will be that of IN0.
Table 1. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Table 2. Control Register Bit Descriptions
Bit No:
Symbol:
7, 6, 2, 1, 0
DONTC
5
ADD2
4
ADD1
3
ADD0
Description
Don't care. The values of these bits do not affect the device.
These three bits determine which input channel will be sampled and converted at the next
conversion cycle. The mapping between codes and channels is shown in Table 3.
Table 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
0
0
0
IN0 (Default)
0
0
1
IN1
0
1
0
IN2
0
1
1
IN3
1
0
0
IN4
1
0
1
IN5
1
1
0
IN6
1
1
1
IN7
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Since the ADC128S102 integrates an 8 to 1 MUX on the front end, the
device is typically used in applications where multiple voltages need to be monitored. In addition to having 8
input channels, the ADC128S102 can operate at sampling rates up to 1 MSPS. As a result, the ADC128S102 is
typically run in burst fashion where a voltage is sampled for several times and then the ADC128S102 can be
powered-down. This is a common technique for applications that are power limited. Due to the high bandwidth
and sampling rate, the ADC128S102 is suitable for monitoring AC waveforms as well as DC inputs. The following
example shows a common configuration for monitoring AC inputs.
8.2 Typical Application
The following sections outline the design principles of data acquisition system based on the ADC128S102.
A typical application is shown in Figure 38. The analog supply is bypassed with a capacitor network located close
to the ADC128S102. The ADC128S102 uses the analog supply (VA) as its reference voltage, so it is very
important that VA be kept as clean as possible. Due to the low power requirements of the ADC128S102, it is also
possible to use a precision reference as a power supply.
5V
3.3V
1uF
High
Impedance
Source
+
LMV612
0.1uF
0.1uF
VA
100
VD
IN7
1uF
VDD
100
GPIOa
SCLK
100
GPIOb
CS
33n
MCU
100
Low
Impedance
Source
Schottky
Diode
(optional)
100
IN3
ADC128S102
100
DIN
GPIOd
GND
IN0
33n
GPIOc
DOUT
AGND
DGND
Figure 38. Typical Application Circuit
8.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing signals ranging 0 to 5 V, BW = 10 kHz, and a
throughput of 125 kSPS.
The ADC128S102 has to interface to an MCU whose supply is set at 3.3 V.
8.2.2 Detailed Design Procedure
The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from
the fact that VA is also a reference potential for the ADC.
The requirement of interfacing to the MCU which is powered by 3.3-V supply, forces the choice of 3.3-V as a VD
supply.
Sampling is in fact a modulation process which may result in aliasing of the input signal, if the input signal is not
adequately band limited. The maximum sampling rate of the ADC128S102 when all channels are enabled is, Fs:
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Typical Application (continued)
Fs =
FSCLK
16 ´ 8
(2)
Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be
sampled at the maximum rate of:
FSCLK
Fs _ sin gle =
16
(3)
In order to avoid the aliasing the Nyquist criterion has to be met:
Fs
BW signal £
2
(4)
Therefore it is necessary to place anti-aliasing filters at all inputs of the ADC. These filters may be single pole low
pass filters whose pole location has to satisfy, assuming all channels sampled in sequence:
1
FSCLK
£
p ´ R ´ C 16 ´ 8
(5)
128
R´C ³
p ´ FSCLK
(6)
With Fsclk = 16 MHz, a good choice for the single pole filter is:
• R = 100
• C = 33 nF
This reduces the input BWsignal = 48 kHz. The capacitor at the INx input of the device provides not only the
filtering of the input signal, but it also absorbs the charge kick-back from the ADC. The kick-back is the result of
the internal switches opening at the end of the acquisition period.
The VA and VD sources are already separated in this example, due to the design requirements. This also
benefits the overall performance of the ADC, as the potentially noisy VD supply does not contaminate the VA. In
the same vain, further consideration could be given to the SPI interface, especially when the master MCU is
capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal
path may help in reducing the ground bounce, and thus improve the overall noise performance of the system.
Care should be taken when the signal source is capable of producing voltages beyond VA. In such instances the
internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide
the desired clamping action use Schottky diodes as shown in Figure 38.
8.2.3 Application Curve
Figure 39. Typical Performance
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9 Power Supply Recommendations
There are three major power supply concerns with this product: power supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
9.1 Power Supply Sequence
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital
supply (VD) cannot exceed the analog supply (VA) by more than 300 mV. Therefore, VA must ramp up before or
concurrently with VD.
9.2 Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if
the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly
into the analog supply, causing greater performance degradation than would noise on the digital supply alone.
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will
dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise
in the substrate that will degrade noise performance if that current is large enough. The larger the output
capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog
channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance. Since the series resistor and the load
capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
10 Layout
10.1 Layout Guidelines
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have
significant impact upon system noise performance. To avoid performance degradation of the ADC128S102 due
to supply noise, do not use the same supply for the ADC128S102 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes
should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be
placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal
chain that are connected to ground should be connected together with short traces and enter the analog ground
plane at a single, quiet point.
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10.2 Layout Example
ANALOG
SUPPLY
RAIL
to analog
signal sources
CS
SCLK
VA
DOUT
AGND
DIN
IN0
VD
IN1
DGND
IN2
IN7
IN3
IN6
IN4
IN5
toMCU
“DIGITAL” SUPPLY RAIL
VIA to GROUND PLANE
GROUND PLANE
Figure 40. Layout Schematic
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another
channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-toChannel Isolation, except for the sign of the data.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below
VREF+ and is defined as:
VFSE = Vmax + 1.5 LSB – VREF+
where
•
•
Vmax is the voltage at which the transition to the maximum code occurs.
FSE can be expressed in Volts, LSB or percent of full scale range.
(7)
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above
the last code transition). The deviation of any given code from this straight line is measured from
the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as
the ratio of the power in both the second or the third order intermodulation products to the power in
one of the original frequencies. Second order products are fa ± fb, where fa and fb are the two sine
wave input frequencies. Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is usually expressed
in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be
reached with any input value. The ADC128S102 is ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
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Device Support (continued)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not
including d.c. or the harmonics included in THD.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral
component is any signal present in the output spectrum that is not present at the input and may or
may not be a harmonic.
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion and read out times. In the case of the ADC128S102, this is 16
SCLK periods.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five
harmonic components at the output to the rms level of the input signal frequency as seen at the
output. THD is calculated as:
THD = 20 log 10
A f22 + + A f10 2
A f12
where
•
•
Af1 is the RMS power of the input frequency at the output
Af2 through Af10 are the RMS power in the first 9 harmonic frequencies
(8)
11.2 Trademarks
MICROWIRE is a trademark of Texas Instruments.
QSPI is a trademark of Motorola, Inc..
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC128S102CIMT
NRND
TSSOP
PW
16
92
TBD
Call TI
Call TI
-40 to 105
128S102
CIMT
ADC128S102CIMT/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 105
128S102
CIMT
ADC128S102CIMTX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 105
128S102
CIMT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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