February 14, 2006
Rev -2.0
CS
National Semiconductor
Evaluation Board User's Guide
8-bit
10-bit
12-bit
50KSPS - 200kSPS
ADC088S022
ADC108S022
ADC128S022
200KSPS - 500KSPS
ADC088S052
ADC088S102
ADC108S052
ADC108S102
ADC128S052
ADC128S102
500KSPS - 1MSPS
Low Power, Eight-Channel CMOS Analog-to-Digital
Converter Family
© 2005 National Semiconductor Corporation.
1
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2
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Table of Contents
1.0 Introduction ................................................................................................. 4
2.0 Board Assembly .......................................................................................... 5
3.0 Quick Start .................................................................................................. 5
3.1 Stand Alone Mode............................................................................ 5
3.2 Computer Mode................................................................................ 5
4.0 Functional Description................................................................................. 6
4.1 The Signal Input ............................................................................... 6
4.2 ADC Reference Circuitry .................................................................. 6
4.3 ADC Clock Circuit............................................................................. 6
4.4 Digital Data Output ........................................................................... 6
4.5 Power Supply Connections .............................................................. 6
5.0 Software Operation and Settings ................................................................ 7
6.0 Evaluation Board Specifications.................................................................. 7
7.0 Hardware Schematic ................................................................................... 8
8.0 Evaluation Board Bill of Materials................................................................ 9
A1.0 Summary Tables of Test Points, Jumpers, and Connectors..................... 11
3
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number WV4ADCIFCABLE). The Data Capture (WV4)
Board is connected to a personal computer running
WaveVision software through a USB port.
The
™
WaveVision4 software runs on Microsoft Windows
and the latest version can be downloaded from the web
at http://www.national.com/adc.
1.0 Introduction
The ADC128S102EVAL Design Kit (consisting of the
ADC128S102 Evaluation Board and this User's Guide)
is designed to ease evaluation and design-in of
National Semiconductor’s eight-channel, low-power
CMOS Analog-to-Digital Converters (ADC128S102,
ADC108S102,
ADC088S102,
ADC128S052,
ADC108S052,
ADC088S052,
ADC128S022,
ADC108S022, and ADC088S022). This family of pincompatible ADCs will be referenced throughout this
document as the ADC128S102.
Note: WaveVision Software version 4.2 or later is
required to evaluate this part with the WV4 Evaluation
System.
The Analog input signal enters the Analog-to-Digital
Converter through one of its eight selectable input
channels and is converted into a digital stream of bits
by U1, the ADC128S102. The WV4 system captures
and displays the digitized signal on a PC monitor in the
time and frequency domains.
The evaluation board can be used in one of two modes;
Stand-alone or Computer mode.
In Stand-alone mode, suitable test equipment, such as
a function generator and logic analyzer, can be used
with the board to evaluate the ADC128S102.
The software will perform an FFT on the captured data
upon command.
This FFT plot shows dynamic
performance in the form of SNR, SINAD, THD, SFDR
and ENOB. A histogram of the captured data is also
available.
In the Computer mode, data capture and evaluation is
simplified by connecting this board to National
Semiconductor's Data Capture Board (order number
WAVEVSN BRD 4.0) with a 14-pin ribbon cable (order
J2
IN A
JP2
JP1
J4
IN B
U1
ADC128S102
J3
Serial Interface
WV4 Connector
JP3
D3
JP7
Clk Selection
JP8
J5
+5V In
JP6
JP9
D1
J6
External Clock
Figure 1: Component and Test Point Locations
4
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2.0 Board Assembly
2
1
The ADC128S102 evaluation board comes fully
assembled and ready for use. Refer to the Bill of
Materials for a description of components, to Figure 1
for major component placement, and to Figure 3 for the
Evaluation Board schematic.
CS
WV4
SCLK
DOUT
J3
DIN
3.0 Quick Start
Figure 2: J3 WaveVision4 Serial Interface Header
5.
3.1 Stand Alone Mode
Refer to Figure 1 for locations of test points and major
components.
1.
Open all the DIP switches at DIP1 and configure
the board’s jumpers according to Table 1 below.
JP1 (INA Coupling)
JP2 (INB Select)
JP3 (INB Coupling)
JP6 (5P5V Select)
JP7 (SCLK Select)
JP8 (3P3V Select)
JP9 (VD Select)
Pin1
Pin2
Pin3
Pin4
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
3.
4.
Finally, import the Data taken with a Logic
Analyzer or other third-party equipment into the
WaveVision4 Software. Refer to WaveVision4
Manual for data analysis techniques.
3.2 Computer Mode
Refer to Figure 1 for locations of test points and major
components.
1.
2.
Table 1: Quick Start Jumper Configuration
2.
14
13
The ADC128S102 evaluation board may be used in the
Stand-Alone mode to capture data with a logic analyzer
or other third-party equipment. It may also be used in
the Computer Mode with a WV4 Board. In both cases,
the captured data can be analyzed with National
Semiconductor’s WaveVision4 software.
Connect a clean analog (not switching) +5V power
source to Power Connector J5.
Connect a single-ended source of 4.8 VP-P
amplitude from a suitable 50-Ohm source to INB
(BNC J4). This signal should be applied through a
bandpass filter to eliminate the noise and
harmonics commonly associated with signal
sources. To accurately evaluate the performance
of the ADC128S102, the source must be better
than 90dB THD.
Note: For a time-varying DC input signal, DC
couple the input by placing the jumper at JP3
across pins 1 & 2 instead of pins 2 & 3.
The digital inputs and outputs are available at
header J3. Refer to Figure 2 for connection
details. The source used to create signals SCLK,
CSB, and DIN must meet the digital input
characteristics in the ADC128S102 datasheet.
2.
3.
4.
5.
6.
5
Run the WaveVision4 program.
While the
program is loading, continue below.
Install the appropriate crystal oscillator into socket
Y2 and short pins 1 & 2 of JP7 (See Table 1).
Alternatively, connect a low-jitter square wave
generator with an amplitude between 2.5 VP-P and
5 VP-P to BNC connector J6 and short pins 2 & 3
of JP7.
If using an external source, remove the oscillator
from Y2. If using an oscillator at Y2, remove the
signal source from J6. The presence of a second
oscillator source could add noise to the conversion
process.
Perform steps 1 and 2 of section 3.1.
Connect the 14-pin ribbon cable between J3 of the
ADC128S102 evaluation board and J3 of the WV4
board.
Connect a clean analog (not switching) +5V power
source to Power Connector J1 on the WV4 board.
Connect a USB cable between the WaveVision4
Data Capture Board and the PC running the
WaveVision4 program.
See Section 4.5 for
detailed Power Supply Information.
Refer to section 5.0 on Software Operation and
Settings.
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ADC128S102 input channels. For example, to route
INA to input channels 0 and 5, close dip switches 1 and
6. For INB, simply place jumpers across JP2 to select
input channels. For example, to route INB to input
channels 0 and 3, short pins 1 and 2 as well as pins 7
and 8 of JP2.
4.0 Functional Description
Table 2 describes the function of the various jumpers
on the ADC128S102 evaluation board. The Evaluation
Board schematic is shown in Figure 3.
Jumper
Function
DIP1
Routes INA to each of the eight ADC
channels. E.g. Switch 1 routes INA to
channel 0 while switch 4 routes INA to
channel 3.
JP1
JP2
JP3
Pins 1 & 2
Pins 3 & 4
Pins 5 & 6
DC couple
INA
AC couple
INA
Ground
INA
JP7
JP8
JP9
The ADC128S102 family gets its reference voltage
from the analog supply (VA). Hence, a clean analog
supply must be used to guarantee the performance of
the ADC128S102.
4.3 ADC Clock Circuit
In Computer mode, the ADC128S102 Evaluation board
sends a clock signal to the WV4 Data capture board.
This clock signal is used to derive the digital signals
that drive the ADC128S102.
Routes INB to each of the eight ADC
channels. E.g. Pins 1 & 2 route INB to
channel 0 while pins 15 and 16 route INB to
channel 7.
Pins 1& 2
Pins 2 & 3
DC couple INB
AC couple INB
JP5
JP6
4.2 ADC Reference Circuitry
The crystal-based oscillator provided on the evaluation
board is selected by shorting pins 1 & 2 of JP7. It is
best to remove any external signal generator when
using this oscillator to reduce any unnecessary noise.
This board will also accept a clock signal from an
external source by connecting that source to BNC J6
and shorting pins 2 & 3 of JP7. An ac-coupling circuit
together with a DC-biased resistive divider is provided
so the board can accept a 50 Ohm signal source in the
range of 2.5 to 5.0VP-P to drive this input. It is best to
remove the oscillator at Y2 when using an external
clock source to reduce any unnecessary noise.
Not Used
Pins 1& 2
Pins 2 & 3
5P5V_REMOTE
5P5V_LOCAL
Pins 1& 2
Pins 2 & 3
Select on-board
clock oscillator Y2
Select clock
oscillator at BNC J6
Pins 1& 2
Pins 2 & 3
Select on-board
+3.3V
Select +3.3V from
WV4S board
Pins 1& 2
Pins 2 & 3
Not Used
Set VD=VA
If the Evaluation board is used in Stand-alone mode,
the onboard oscillator and signal applied to J6 do not
drive the SCLK pin. Rather, an external source such
as a pattern generator must supply the digital signals
(CSB, SCLK, DIN) to drive the ADC128S102. These
signals must be applied at J3, the Serial Interface
Header (See Figure 2).
Note: SCLK, CSB, & DIN must be driven between 0 and
VA to prevent damage to the ADC.
Table 2: Jumper Functions
4.4 Digital Data Output
4.1 The Signal Input
The serial data output from this board may be
monitored at TP15 or J3. Note: The TP15 test points
are current limited by 1kΩ resistors which will cause
some slewing of the digital waveforms. For data
capture with the WaveVision4 Software, refer to section
3.2. Detailed timing diagrams can be found in the
datasheet.
The input signal to be digitized can be applied through
the BNC connector at J2 (INA) or J4 (INB). Two inputs
allow the user to utilize multiple channels of the eightchannel ADC128S102 at the same time.
Both INA and INB can be AC coupled or DC coupled.
To digitize a time-varying DC signal, place a jumper
across pins 1 and 2 of JP1 for INA, or place a jumper
across pins 1 and 2 of JP3 for INB. If the AC
component of an input signal is to be evaluated, place
a jumper across pins 3 and 4 of JP1 for INA, or place a
jumper across pins 2 and 3 of JP3 for INB. Additionally,
INA can be grounded by shorting pins 5 and 6 of JP1.
4.5 Power Supply Connections
The ADC128S102 Evaluation Board has three
independent supplies; VA, VD, and 3P3V. VA serves as
the analog reference for the Analog to Digital Converter
and must be driven by a clean source to maximize the
performance of the ADC128S102. The voltage applied
to VA can be any value between 2.7V and 5.25V. VD
sets the digital output level of the device and can be
any value between 2.7V and the voltage applied to pin
VA. 3P3V supplies power to the on-board EEPROM
Both INA and INB of the ADC128S102 Evaluation board
can be routed to any number of the Analog-to-Digital
converter’s eight channels. For INA, simply close the
DIP switches corresponding to the desired
6
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and is automatically generated on the evaluation board
when pins 1 & 2 are shorted on JP8. This voltage is
only used by U2 when operating the evaluation board
in computer mode.
A plot of the selected number of samples will be
displayed. Make sure there is no clipping of data
samples. The Samples may be further analyzed by
clicking on the magnifying glass icon, then clicking and
dragging across a specific area of the plot for better
data inspection. See the WaveVision4 Board User's
Guide for details.
If desired, VD and VA can be tied together by placing a
jumper across pins 2 and 3 of JP9. Otherwise, VD can
be driven independently of VA by removing the jumper
at JP9 and driving pin 2 of JP9 directly. In either case,
the supply voltage for VA must be supplied to connector
J5, labeled 5P5V, or directly to TP10. A jumper must
be placed across pins 1 and 2 of JP6.
To view an FFT of the data captured, click on the ‘FFT’
tab. This plot may also be zoomed in on. A display of
dynamic performance parameters in the form of
SINAD, SNR, THD, SFDR and ENOB will be displayed
at the top right hand corner of the FFT plot.
To view a Histogram of the data, click on the “Software
Histogram” tab. This plot may be zoomed in on like the
data plot. If the input signal is clipping, the ‘zero’ and
‘full-scale’ codes will be very abundant. The number of
missing codes will be displayed at the top right hand
corner of the plot.
5.0 Software Operation and Settings
The WaveVision4 software is included with the WV4
board and the latest version can be downloaded for
free
from
National's
web
site
at
http://www.national.com/adc.
WaveVision Software
version 4.2 or later is required to evaluate this part with
the WV4 Evaluation System.
Acquired data may be saved to a file. Plots may also
be exported as graphics.
To install this software, follow the procedure in the
WAVEVSN BRD 4 User's Guide. Once the software is
installed, set it up as follows:
1.
2.
3.
Please refer to the WaveVision4 Data Capture Board
User's Guide for further details.
Follow the steps outlined in Section 3.2 “Computer
Mode Quick Start”.
From the WaveVision main menu, go to Settings,
then Board Settings and do the following:
Select the following from the WaveVision4 main
menu:
• WaveVision 4.0 (USB)
• # of Samples: 2K to 32K, as desired
6.0 Evaluation Board Specifications
Board Size:
Power
Requirements
Clock Frequency
Range:
Apply power as specified in Section 4.5, click on
the "Test" button and await the firmware to
download.
4.
Click on the "Accept" button.
5.
Click on ‘Acquire’ then ‘Samples’ from the Main
Menu (you can also press the F1 shortcut key). If
a dialog box opens, select ‘Discard’ or press the
Escape key to start collecting new updated
samples.
Analog Input
Nominal
Voltage Range:
Impedance:
7
3.25" x 4.19" (8.25 cm x 10.65 cm)
Min: +2.7V,
Max: +5.25V,
100mA
100 mA
ADCXX8S102 8MHz to 16MHz
ADCXX8S052 3.2MHz to 8MHz
ADCXX8S022 800kHz to 3.2MHz
4.9VP-P
Low: +0.05V High: (VA-0.05V)
50 Ohms
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J4
INB
1
1
R19
51
R8
51
VA
INB
C14
1uF
R13
4.99K
R9
4.75K
C8
1uF
R6
4.99K
TP6
Input_2
1
2
3
+
+
+
2
4
6
AC
DC
AGND
IN2_SEL
JP3
INPUT1
INPUT2
INB SELECT
AGND
INA SELECT
IN1_SEL
+
+
+
TP5
AGND
1
3
5
TP13
AGND
DC
AC
GND
TP11
AGND
AGND
10uF
C20
RED LED
D1
R23
510
5P5V
TP10
5P5V
JP2
IN2_CH_SEL
OPEN
DIP1
IN1_CH_SEL
CLOSED
1
2
5P5V_REMOTE
AGND
D5
3.3V Zener
J5
5P5V_REMOTE
D2
1N4001
R34
51
5P5V_REMOTE
2) Stuff a 2-pin male header in pins 2 and 3 of JP9. It w as originally designed to be a 3 pin jumper and now only requires 2 pins.
TP3
AGND
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
AGND
NS
VR2
3P3V_REMOTE
R26
-
3P3V_LOCAL
3P3V SELECTION
JP8
3P3V SELECTION
5P5V SELECTION
JP6
5P5V SELECTION
3P3V
6
5P5V_LOCAL
NS
C21
+
U3B
5
VA ADJUST
1
5P5V
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
1) Device U3 should not be stuffed. Instead, short pad 7 to pad 8 of the U3 footprint. This allow s 5P5V to be directly connected to VA.
Assembly Notes:
INB
INA
J2
INA
2
2
1
1
1
JP1
1
R4
4.75K
1
15
13
11
9
7
5
3
1
16
14
12
10
8
6
4
2
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
NS
NS
R24
C18
NS
C17
NS
IN6
CLK_IN
7
IN5
IN4
IN3
J6
CLK
0
R31
51
C28
0.1uF
VR1
NS
ADC128S102-TSSOP16
VA
NS
C19
C11
VD
R32
4.99K
R29
4.75K
2
3
NS
1
TP14
AGND
NS
NS
D4
R25
-
+
U3A
5P5V
1uF 0.1uF
C10
VD ADJUST
470pF
22
VA
C13
R14
470pF
22
TP8
VA
C12
R12
470pF
22
470pF
22
470pF
22
C1
R1
470pF
22
C2
R2
470pF
22
C3
R3
470pF
22
C4
R5
VA
1
IN7
C9
R10
C7
R7
IN2
IN1
7
INA
1
2
3
8
IN4
IN5
9
1
IN3
IN6
6
IN7
VA
1
3
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1
Figure 3: ADC128S102 Evaluation Board Schematic
1
2
3
8
4
8
4
11
DGND
12
VD
13
VA
1
10
IN2
5
IN1
4
IN0
3
AGND
VA
2
TP7
AGND
AGND
R33 0
2
1
NS
U1
VA
C26
OE
SDA
SCLK
CSB
Y1
NS
1
1
2
L1
100uH
U4
NS
NS
4
C27
VD
VA
3
1
8
OUT
CLK SELECT
2
JP7
CLK SELECT
0.1uF
OUT
R30 51
Y2
16MHz
1
3
NS
CLKSEND
C25
10uF
C16
OSC ENABLE
JP5
OSC ENABLE
3P3V VA
R27
0
0.1uF
R35
NS
10uF
VD SELECTION
JP9
VD = VA
C15
3P3V
14
13
11
9
12
7
5
3
1
8
SDA
SCL
WV4S
SCL
WV4
5P5V_LOCAL
CLKSEND 10
6
4
2
14
12
10
8
6
4
2
5P5V_LOCAL
J3
HEADER 7X2
3P3V_LOCAL
3P3V_LOCAL
DIN
OE
9
CLKSEND
DOUT
C24
7
11
DIN
13
5
DOUT
3
SCLK
J1
HEADER 7X2
1
CSB
R16 R15
1K 1K
DIN
CLKSEND
R18 R17
1K 1K
TP15
SPI TEST POINTS
DOUT
SCLK
CSB
AGND
VD SELECTION
AGND
R11 51
VD ADJUST
R20
C6
TP2
AGND
0.1uF 1uF
C5
VA
DOUT
1
DIN
14
1
CSB
15
1
1
2
3
SCLK
DIN
DOUT
SCLK
CSB
4
3
2
1
TP1
Input_1
2
14
VDD
GND
7
3P3V
7
16
5
3
4
VDD
GND
2
VA
8
3P3V
RED LED
D3
R28
200
3P3V
3P3V
3P3V
TP12
3P3V
R22
0
3P3V
R21
NS
AGND
U2
24C02
TP4
AGND
WP
1
VCC
2
A0
1
A1
6
SCL
5
SDA
A2
3
GND
4
8
1
IN0
7.0 Hardware Schematic
8.0 Evaluation Board Bill of Materials
Qty.
PCB Footprint
5
1
2
1
1
1
1
1
1
1
Reference
C1,C2,C3,C4,C7,
C9, C12, C13
C5,C11,C16,C26,
C28
C10,C6
C14,C8
C15,C20,C25
C17
C18,C19,C21,
C24,C27
DIP1
D3,D1
D2
D4
D5
JP1
JP2
JP3
JP5
sm/c_0805
dip.100/16/w.300/l.900
sm/led_21
DAX2/DO41
sm/sot23_123/nat
sm/SOT23
blkcon.100/vh/tm2oe/w.200/6
blkcon.100/vh/tm2oe/w.200/16
blkcon.100/vh/tm1sq/w.100/3
blkcon.100/vh/tm1sq/w.100/2
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
10V
CT2068-ND
516-1440-1-ND
1N4001GICT-ND
BAT54SLT1OSCT-ND
MMBZ5226BLT1OSCT-ND
A26529-40-ND
A26529-40-ND
A26513-40-ND
A26513-40-ND
1
1
JP6
JP7
blkcon.100/vh/tm1sq/w.100/3
blkcon.100/vh/tm1sq/w.100/3
Digikey
Digikey
A26513-40-ND
A26513-40-ND
1
JP8
blkcon.100/vh/tm1sq/w.100/3
Digikey
A26513-40-ND
1
1
1
1
1
1
1
1
JP9
J1
J2
J3
J4
J5
J6
L1
R1,R2,R3,R5,R7,
R10,R12, R14
R4,R9,R29
R6,R13,R32
R8,R11,R19,R30,
R31,R34
R15,R16,R17,R18
R20,R21,R25,
R26,R35
R22,R24,R27,R33
R23
R28
TP1
TP2,TP3,TP4,
TP5,TP7,TP11
TP13, TP14
blkcon.100/vh/tm1sq/w.100/3
blkcon/2mm/ra/tm2oe/w2mm/14
rf/bnc/r1.350_21
blkcon.100/vh/tm2oe/w.200/14
rf/bnc/r1.350_21
term_block/.200/2pos
rf/bnc/r1.350_21
sm/l_1210
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
A26513-40-ND
S2200-07-ND
ARF1177-ND
A26529-40-ND
ARF1177-ND
ED1609-ND
ARF1177-ND
445-1155-1-ND
8
5
2
2
3
1
8
3
3
6
4
5
4
1
1
1
6
2
Source
Source Part #
Rating
Value
sm/c_0805
10V
470pF
sm/c_0805
sm/c_1206
sm/c_0805
sm/ct_3216_12
sm/c_1206
10V
10V
10V
10V
10V
0.1uF
1uF
1uF
10uF
NS
NS
IN1_CH_SEL
RED LED
1N4001
NS
3.3V Zener
IN1_SEL
IN2_CH_SEL
IN2_SEL
OSC ENABLE
5P5V
SELECTION
CLK SELECT
3P3V
SELECTION
VD
SELECTION
HEADER 7X2
INA
HEADER 7X2
INB
5P5V_REMOTE
CLK
100uH
sm/r_0805
sm/r_0805
sm/r_0805
22
4.75K
4.99K
sm/r_0805
sm/r_0805
51
1K
sm/r_0805
sm/r_0805
sm/r_0805
sm/r_0805
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
NS
0
510
200
Input_1
blkcon.100/vh/tm1sq/w.100/1
blkcon.100/vh/tm1sq/w.100/1
Digikey
Digikey
5011K-ND
5011K-ND
AGND
AGND
9
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1
1
1
1
TP6
TP8
TP10
TP12
blkcon.100/vh/tm1sq/w.100/1
blkcon.100/vh/tm1sq/w.100/1
blkcon.100/vh/tm1sq/w.100/1
blkcon.100/vh/tm1sq/w.100/1
Digikey
Digikey
Digikey
Digikey
5011K-ND
5011K-ND
5011K-ND
5011K-ND
1
1
1
1
1
2
1
1
TP15
U1
U2
U3
U4
VR2,VR1
Y1
Y2
blkcon.100/vh/tm1sq/w.100/4
sog.65m/16/wg6.40/l5.10
sog.050/8/wg.244/l.200
sog.050/8/wg.244/l.200
sm/SOT23-5
vres4
SOJ.100/4/WG8.80MM/L.550
crystal_socket
Digikey
A26513-40-ND
Digikey
Digikey
Digikey
LMC6492AEMX
NC7SZ00M5CT-ND
3386F-103-ND
Digikey
A400-ND
1
1
Y2
PCB
J1
oscillator
ADC128S102 evaluation board
Digikey
CTX116-ND
Input_2
VA
5P5V
3P3V
SPI TEST
POINTS
ADCxx8Sxx2
24C02
NS
NS
NS
NS
socket
16.0MHz OSC
(thru-hole)
Digikey
S2200-07-ND
HEADER 7X2
10
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APPENDIX
A1.0 Summary Tables of Test Points, Jumpers, and Connectors
Test Points on the ADC128S102 Evaluation Board
TP1: INA
INA test point. Located near the top left of the board.
TP2: AGND
Ground. Located near the top left of the board.
TP3: AGND
Ground. Located near the top of the board. Just above U1.
TP4: AGND
Ground. Located at the right edge of the board.
TP5: AGND
Ground. Located between the BNC connectors on the left side of the board.
TP6: INB
INB test point. Located near the middle of the board.
TP7: AGND
Ground. Located just above the oscillator socket.
TP8: VA
VA supply test point. Located near the bottom edge of the board.
TP10: 5P5V
5P5V supply test point. Located near the bottom left of the board.
TP11: AGND
Ground. Located near the bottom left of the board.
TP12: 3P3V
3.3V test point. Located at the right edge of the board.
TP13: AGND
Ground. Located near the bottom edge of the board.
TP14: AGND
Ground. Located near the center of the board.
TP15:
Warning: Do not attempt to drive the chip via these test points, they are isolated by 1kΩ
resistors and for probing only. Instead, use the header J3 as shown in Figure 2.
Pin 1: CSB
Chip Select test point.
Pin 2: SCLK
Serial Clock test point.
Pin 3: DOUT
Data Out test point.
Pin 4: DIN
Data In test point.
Connectors on the ADC128S102 Evaluation Board
J1: WV4S
WV4S 14-Pin Right-angle Header
J2: INA Input
BNC Connector
J3: WV4
WV4 14-Pin Header
J4: INB Input
BNC Connector
J5: VA_REMOTE
Two Position Power connector terminal block.
J6: External Clock
BNC Connector
Selection Jumpers on the ADC128S102 Evaluation Board (Refer to Table 2, Section 4.0 for configuration details)
DIP1: INA Channel Selection
Routes Input A to the ADC’s eight input channels.
JP1: INA Coupling
Selects AC coupling, DC coupling, or simply grounds Input A
JP2: INB Channel Selection
Routes Input B to the ADC’s eight input channels.
JP3: INB Coupling
Selects AC coupling, DC coupling, or simply grounds Input B
JP5: Oscillator Enable
Enables or disables the on-board oscillator.
JP6: 5P5V Select
Selects local or remote source of 5P5V supply.
JP6: Osc Enable
Not Used
JP7: Clock Select
Selects internal or external clock source.
JP8: 3P3V Select
Selects local or remote source of 3P3V supply.
JP9: VD Select
Sets the digital supply (VD) equal to the analog supply (VA).
11
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BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF NATIONAL
SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU HAVE READ AND
AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE WITH THEM, CONTACT THE
VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF THE UNUSED PRODUCT FOR A
REFUND OF THE PURCHASE PRICE PAID, IF ANY.
The ADC128S102, ADC108S102, ADC088S102, ADC128S052, ADC108S052, ADC088S052, ADC128S022, ADC108S022, and
ADC088S022 Evaluation Boards are intended for product evaluation purposes only and are not intended for resale to end
consumers, are not authorized for such use and are not designed for compliance with European EMC Directive 89/336/EEC, or for
compliance with any other electromagnetic compatibility requirements.
National Semiconductor Corporation does not assume any responsibility for use of any circuitry or software supplied or described.
No circuit patent licenses are implied.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to the
user.
National Semiconductor Corporation
Americas
Tel:
1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
2. A critical component is any component in a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Email: europe.support@nsc.com
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Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the right at any time
without notice to change said circuitry and specifications.
12
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EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
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Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
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No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
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REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
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For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
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General Statement for EVMs including a radio
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For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
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This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
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Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
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FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
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FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
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on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
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Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
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Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
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This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
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Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
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Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
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Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
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(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
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【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
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Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
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You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
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