ADC12D500RF, ADC12D800RF
ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SNAS502E
July 2011 – Revised March 2013
ADC12D500RF, ADC12D800RF
www.ti.com
SNAS502E – JULY 2011 – REVISED MARCH 2013
Contents
1
Introduction
1.1
1.2
1.3
2
3
.............................................................................................................. 8
2.1
Block Diagram ............................................................................................................... 8
2.2
RF Performance ............................................................................................................. 9
2.3
ADC12D800/500RF Connection Diagram ............................................................................. 10
2.4
Ball Descriptions and Equivalent Circuits .............................................................................. 11
Electrical Specifications ..................................................................................................... 19
3.1
Absolute Maximum Ratings .............................................................................................. 19
3.2
Operating Ratings ......................................................................................................... 19
3.3
Package Thermal Resistance ............................................................................................ 20
Device Information
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
4
20
21
24
25
25
25
26
27
27
29
29
.................................................................................................... 30
Transfer Characteristic .................................................................................................... 32
Timing Diagrams .......................................................................................................... 33
Typical Performance Plots .................................................................................................. 36
Functional Description ....................................................................................................... 46
6.1
6.2
2
Converter Electrical Characteristics
Static Converter Characteristics .........................................................................................
Converter Electrical Characteristics
Dynamic Converter Characteristics .....................................................................................
Converter Electrical Characteristics
Analog Input/Output and Reference Characteristics ..................................................................
Converter Electrical Characteristics
I-Channel to Q-Channel Characteristics ................................................................................
Converter Electrical Characteristics
Sampling Clock Characteristics .........................................................................................
Converter Electrical Characteristics
AutoSync Feature Characteristics .......................................................................................
Converter Electrical Characteristics
Digital Control and Output Pin Characteristics ........................................................................
Converter Electrical Characteristics
Power Supply Characteristics ............................................................................................
Converter Electrical Characteristics
AC Electrical Characteristics .............................................................................................
Converter Electrical Characteristics Serial Port Interface ............................................................
Converter Electrical Characteristics Calibration .......................................................................
Specification Definitions
4.1
4.2
5
6
........................................................................................................................ 7
Features ...................................................................................................................... 7
Applications .................................................................................................................. 7
Description ................................................................................................................... 7
Overview ....................................................................................................................
Control modes .............................................................................................................
6.2.1
Non-Extended Control Mode ..................................................................................
6.2.1.1
Dual Edge Sampling Pin (DES) ..................................................................
6.2.1.2
Non-Demultiplexed Mode Pin (NDM) ............................................................
6.2.1.3
Dual Data Rate Phase Pin (DDRPh) ............................................................
6.2.1.4
Calibration Pin (CAL) ..............................................................................
6.2.1.5
Calibration Delay Pin (CalDly) ....................................................................
6.2.1.6
Power Down I-channel Pin (PDI) ................................................................
6.2.1.7
Power Down Q-channel Pin (PDQ) ..............................................................
6.2.1.8
Test Pattern Mode Pin (TPM) ....................................................................
6.2.1.9
Full-Scale Input Range Pin (FSR) ...............................................................
6.2.1.10 AC/DC-Coupled Mode Pin (VCMO) ...............................................................
6.2.1.11 LVDS Output Common-mode Pin (VBG) ........................................................
6.2.2
Extended Control Mode ........................................................................................
Contents
46
46
46
47
47
47
48
48
48
48
48
49
49
49
49
Copyright © 2011–2013, Texas Instruments Incorporated
ADC12D500RF, ADC12D800RF
www.ti.com
6.3
6.4
SNAS502E – JULY 2011 – REVISED MARCH 2013
6.2.2.1
The Serial Interface ................................................................................
Features ....................................................................................................................
6.3.1
Input Control and Adjust .......................................................................................
6.3.1.1
AC/DC-coupled Mode .............................................................................
6.3.1.2
Input Full-Scale Range Adjust ....................................................................
6.3.1.3
Input Offset Adjust .................................................................................
6.3.1.4
DES/Non-DES Mode ..............................................................................
6.3.1.5
DES Timing Adjust .................................................................................
6.3.1.6
Sampling Clock Phase Adjust ....................................................................
6.3.2
Output Control and Adjust .....................................................................................
6.3.2.1
SDR / DDR Clock ..................................................................................
6.3.2.2
LVDS Output Differential Voltage ................................................................
6.3.2.3
LVDS Output Common-Mode Voltage ..........................................................
6.3.2.4
Output Formatting ..................................................................................
6.3.2.5
Demux/Non-demux Mode .........................................................................
6.3.2.6
Test Pattern Mode .................................................................................
6.3.2.7
Time Stamp .........................................................................................
6.3.3
Calibration Feature .............................................................................................
6.3.3.1
Calibration Control Pins and Bits ................................................................
6.3.3.2
How to Execute a Calibration ....................................................................
6.3.3.3
Power-on Calibration ..............................................................................
6.3.3.4
On-command Calibration .........................................................................
6.3.3.5
Calibration Adjust ..................................................................................
6.3.3.6
Read/Write Calibration Settings ..................................................................
6.3.3.7
Calibration and Power-Down .....................................................................
6.3.3.8
Calibration and the Digital Outputs ..............................................................
6.3.4
Power Down .....................................................................................................
Applications Information ..................................................................................................
6.4.1
THE ANALOG INPUTS ........................................................................................
6.4.1.1
Acquiring the Input .................................................................................
6.4.1.2
Driving the ADC in DES Mode ...................................................................
6.4.1.3
FSR and the Reference Voltage .................................................................
6.4.1.4
Out-Of-Range Indication ..........................................................................
6.4.1.5
Maximum Input Range ............................................................................
6.4.1.6
AC-coupled Input Signals .........................................................................
6.4.1.7
DC-coupled Input Signals .........................................................................
6.4.1.8
Single-Ended Input Signals .......................................................................
6.4.2
THE CLOCK INPUTS ..........................................................................................
6.4.2.1
CLK Coupling .......................................................................................
6.4.2.2
CLK Frequency .....................................................................................
6.4.2.3
CLK Level ...........................................................................................
6.4.2.4
CLK Duty Cycle ....................................................................................
6.4.2.5
CLK Jitter ............................................................................................
6.4.2.6
CLK Layout .........................................................................................
6.4.3
THE LVDS OUTPUTS .........................................................................................
6.4.3.1
Common-mode and Differential Voltage ........................................................
6.4.3.2
Output Data Rate ..................................................................................
6.4.3.3
Terminating Unused LVDS Output Pins ........................................................
6.4.4
SYNCHRONIZING MULTIPLE ADC12D800/500RFS IN A SYSTEM ...................................
6.4.4.1
AutoSync Feature ..................................................................................
6.4.4.2
DCLK Reset Feature ..............................................................................
6.4.5
SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS ...........................
6.4.5.1
Power Planes .......................................................................................
Copyright © 2011–2013, Texas Instruments Incorporated
Contents
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3
ADC12D500RF, ADC12D800RF
SNAS502E – JULY 2011 – REVISED MARCH 2013
6.5
6.4.5.2
Bypass Capacitors .................................................................................
6.4.5.3
Ground Planes .....................................................................................
6.4.5.4
Power System Example ...........................................................................
6.4.5.5
Thermal Management .............................................................................
6.4.6
SYSTEM POWER-ON CONSIDERATIONS ................................................................
6.4.6.1
Power-on, Configuration, and Calibration .......................................................
6.4.6.2
Power-on and Data Clock (DCLK) ...............................................................
6.4.7
RECOMMENDED SYSTEM CHIPS .........................................................................
6.4.7.1
Temperature Sensor ...............................................................................
6.4.7.2
Clocking Device ....................................................................................
6.4.7.3
Amplifiers for the Analog Input ...................................................................
6.4.7.4
Balun Recommendations for Analog Input .....................................................
Register Definitions .......................................................................................................
Revision History
4
www.ti.com
Contents
67
67
68
68
70
70
71
72
72
73
73
73
74
......................................................................................................................... 80
Copyright © 2011–2013, Texas Instruments Incorporated
ADC12D500RF, ADC12D800RF
www.ti.com
SNAS502E – JULY 2011 – REVISED MARCH 2013
List of Figures
2-1
ADC12D800RF DES Mode IMD3 ................................................................................................ 9
2-2
ADC12D800RF DES Mode FFT
2-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
...............................................................................................
See Package Number NXA0292A .............................................................................................
LVDS Output Signal Levels .....................................................................................................
Input / Output Transfer Characteristic ........................................................................................
Clocking in 1:2 Demux Non-DES Mode* ......................................................................................
Clocking in Non-Demux Non-DES Mode*.....................................................................................
Clocking in 1:4 Demux DES Mode* ............................................................................................
Clocking in Non-Demux Mode DES Mode* ...................................................................................
Data Clock Reset Timing (Demux Mode) .....................................................................................
Power-on and On-Command Calibration Timing.............................................................................
Serial Interface Timing ...........................................................................................................
Serial Data Protocol - Read Operation ........................................................................................
Serial Data Protocol - Write Operation ........................................................................................
DDR DCLK-to-Data Phase Relationship ......................................................................................
SDR DCLK-to-Data Phase Relationship ......................................................................................
Driving DESIQ Mode .............................................................................................................
AC-coupled Differential Input ...................................................................................................
Single-Ended to Differential Conversion Using a Balun .....................................................................
Differential Input Clock Connection ............................................................................................
AutoSync Example ...............................................................................................................
Power and Grounding Example ................................................................................................
HSBGA Conceptual Drawing ...................................................................................................
Power-on with Control Pins set by Pull-up/down Resistors.................................................................
Power-on with Control Pins set by FPGA pre Power-on Cal ...............................................................
Power-on with Control Pins set by FPGA post Power-on Cal ..............................................................
Supply and DCLK Ramping .....................................................................................................
Typical Temperature Sensor Application ......................................................................................
Copyright © 2011–2013, Texas Instruments Incorporated
List of Figures
10
10
31
33
33
34
34
34
35
35
35
51
51
55
55
61
62
63
64
66
68
69
71
71
71
72
73
5
ADC12D500RF, ADC12D800RF
SNAS502E – JULY 2011 – REVISED MARCH 2013
www.ti.com
List of Tables
2-1
Analog Front-End and Clock Balls ............................................................................................. 11
2-2
Control and Status Balls ......................................................................................................... 13
2-3
Power and Ground Balls
2-4
High-Speed Digital Outputs ..................................................................................................... 17
6-1
Non-ECM Pin Summary ......................................................................................................... 47
6-2
Serial Interface Pins.............................................................................................................. 49
6-3
Command and Data Field Definitions
6-4
6-5
........................................................................................................
.........................................................................................
Features and Modes ............................................................................................................
Supported Demux, Data Rate Modes .........................................................................................
16
50
52
56
6-6
Test Pattern by Output Port in
Demux Mode ...................................................................................................................... 56
6-7
Test Pattern by Output Port in
Non-Demux Mode ................................................................................................................ 57
6-8
Calibration Pins ................................................................................................................... 58
6-9
Unused Analog Input Recommended Termination .......................................................................... 61
6-10
Unused AutoSync and DCLK Reset Pin Recommendation ................................................................ 66
6-11
Temperature Sensor Recommendation ....................................................................................... 72
6-12
Amplifier Recommendations .................................................................................................... 73
6-13
Balun Recommendations ........................................................................................................ 73
6-14
Register Addresses .............................................................................................................. 74
6-15
Configuration Register 1......................................................................................................... 74
6-16
Reserved .......................................................................................................................... 75
6-17
I-channel Offset Adjust
6-18
I-channel Full Scale Range Adjust ............................................................................................. 75
6-19
Calibration Adjust ................................................................................................................. 76
6-20
Calibration Values ................................................................................................................ 76
6-21
Reserved - ADC12D800RF ..................................................................................................... 76
6-22
Reserved - ADC12D500RF ..................................................................................................... 76
6-23
DES Timing Adjust ............................................................................................................... 77
6-24
Reserved .......................................................................................................................... 77
6-25
Reserved .......................................................................................................................... 77
6-26
Q-channel Offset Adjust ......................................................................................................... 77
6-27
Q-channel Full-Scale Range Adjust
6-28
Aperture Delay Coarse Adjust .................................................................................................. 78
6-29
Aperture Delay Fine Adjust
6-30
AutoSync .......................................................................................................................... 79
6-31
Reserved .......................................................................................................................... 79
6
List of Tables
..........................................................................................................
...........................................................................................
.....................................................................................................
75
78
78
Copyright © 2011–2013, Texas Instruments Incorporated
ADC12D500RF, ADC12D800RF
www.ti.com
SNAS502E – JULY 2011 – REVISED MARCH 2013
ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC
Check for Samples: ADC12D500RF, ADC12D800RF
1
Introduction
1.1
Features
12
• Excellent Noise and Linearity up to and Above
fIN = 2.7 GHz
• Configurable to Either 1.6/1.0 GSPS Interleaved
or 800/500 MSPS Dual ADC
• New DESCLKIQ Mode for High Bandwidth, High
Sampling Rate Apps
• Pin-Compatible with ADC1xD1x00
• AutoSync Feature for Multi-Chip
Synchronization
• Internally Terminated, Buffered, Differential
Analog Inputs
• Interleaved Timing Automatic and Manual Skew
Adjust
• Test Patterns at Output for System Debug
• Time Stamp Feature to Capture External
Trigger
• Programmable Gain, Offset, and tAD Adjust
Feature
• 1:1 Non-Demuxed or 1:2 Demuxed LVDS
Outputs
1.2
•
•
•
•
Applications
3G/4G Wireless Basestation
– Receive Path
– DPD Path
Wideband Microwave Backhaul
RF Sampling Software Defined Radio
Military Communications
1.3
• Key Specifications
– Resolution 12 Bits
– Interleaved 1.6/1.0 GSPS ADC
• IMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61
dBc (typ)
• IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69
dBc (typ)
• Noise Floor: -152.2/-150.5 dBm/Hz (typ)
• Noise Power Ratio: 50.4/50.7 dB (typ)
• Power: 2.50/2.02 W (typ)
– Dual 800/500 MSPS ADC, Fin = 498 MHz
• ENOB: 9.5/9.6 Bits (typ)
• SNR: 59.7/59.7 dB (typ)
• SFDR: 71.2/72 dBc (typ)
• Power per Channel: 1.25/1.01 W (typ)
•
•
•
•
•
SIGINT
RADAR / LIDAR
Wideband Communications
Consumer RF
Test and Measurement
Description
The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input
frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of
TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable
range beyond the 7th Nyquist zone
The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options
to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE
1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free
292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
ADC12D500RF, ADC12D800RF
SNAS502E – JULY 2011 – REVISED MARCH 2013
2
Device Information
2.1
Block Diagram
8
Device Information
www.ti.com
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ADC12D500RF ADC12D800RF
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2.2
SNAS502E – JULY 2011 – REVISED MARCH 2013
RF Performance
-50
IMD3(dBFS)
-60
-7dBFS
-10dBFS
-13dBFS
-16dBFS
-70
-80
-90
-100
0.0
A.
B.
C.
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
3.0
CW Blocker: Fin = 2710.47MHz; Total Power = -13dBFS
WCDMA Blocker: Fc = 2700MHz; Bandwidth = 3.84MHz; Total Power = -13dBFS
IMD3 Product Power = -73dBFS
Figure 2-1. ADC12D800RF DES Mode IMD3
0
MAGNITUDE (dB)
Fin = 2.7GHz
-30
-60
-90
-120
470 475 480 485 490 495 500 505
FREQUENCY (MHz)
Figure 2-2. ADC12D800RF DES Mode FFT
Copyright © 2011–2013, Texas Instruments Incorporated
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Device Information
9
ADC12D500RF, ADC12D800RF
SNAS502E – JULY 2011 – REVISED MARCH 2013
2.3
www.ti.com
ADC12D800/500RF Connection Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
GND
V_A
SDO
TPM
NDM
V_A
GND
V_E
GND_E
DId0+
V_DR
DId3+
GND_DR
DId6+
V_DR
DId9+
B
Vbg
GND
ECEb
SDI
CalRun
V_A
GND
GND_E
V_E
DId0-
DId2+
DId3-
DId5+
DId6-
DId8+
DId9-
DId10+
C
Rtrim+
Vcmo
Rext+
SCSb
SCLK
V_A
NC
V_E
GND_E
DId1+
DId2-
DId4+
DId5-
DId7+
DId8-
DId10-
D
DNC
Rtrim-
Rext-
GND
GND
CAL
DNC
V_A
V_A
DId1-
V_DR
DId4-
GND_DR
DId7-
V_DR
GND_DR
E
V_A
Tdiode+
DNC
F
V_A
G
18
19
20
DId11-
GND_DR
A
DI0+
DI1+
DI1-
B
DI0-
V_DR
DI2+
DI2-
C
V_DR
DI3+
DI4+
DI4-
D
GND
GND_DR
DI3-
DI5+
DI5-
E
GND_TC Tdiode-
DNC
GND_DR
DI6+
DI6-
GND_DR
F
V_TC
GND_TC
V_TC
V_TC
DI7+
DI7-
DI8+
DI8-
G
H
VinI+
V_TC
GND_TC
V_A
GND
GND
GND
GND
GND
GND
DI9+
DI9-
DI10+
DI10-
H
J
VinI-
GND_TC
V_TC
VbiasI
GND
GND
GND
GND
GND
GND
V_DR
DI11+
DI11-
V_DR
J
K
GND
VbiasI
V_TC
GND_TC
GND
GND
GND
GND
GND
GND
ORI+
ORI-
DCLKI+
DCLKI-
K
L
GND
VbiasQ
V_TC
GND_TC
GND
GND
GND
GND
GND
GND
ORQ+
ORQ-
DCLKQ+ DCLKQ-
L
M
VinQ-
GND_TC
V_TC
VbiasQ
GND
GND
GND
GND
GND
GND
N
VinQ+
V_TC
GND_TC
V_A
GND
GND
GND
GND
GND
GND
P
V_TC
GND_TC
V_TC
R
V_A
GND_TC
V_TC
T
V_A
GND_TC GND_TC
U
GND_TC
CLK+
PDI
GND
GND
RCOut1-
V
CLK-
DCLK
_RST+
PDQ
CalDly
DES
RCOut2+ RCOut2-
W
DCLK
_RST-
GND
DNC
DDRPh
RCLK-
Y
GND
V_A
FSR
RCLK+ RCOut1+
1
2
3
GND_DR DId11+
GND_DR DQ11+
DQ11-
GND_DR
M
DQ9+
DQ9-
DQ10+
DQ10-
N
V_TC
DQ7+
DQ7-
DQ8+
DQ8-
P
V_TC
V_DR
DQ6+
DQ6-
V_DR
R
GND
V_DR
DQ3-
DQ5+
DQ5-
T
4
5
DNC
V_A
V_A
DQd1-
V_DR
DQd4-
V_E
GND_E
DQd1+
DQd2-
DQd4+
DQd5-
DQd5+
V_DR
V_DR
GND_DR
DQ3+
DQ4+
DQ4-
U
DQd7+
DQd8-
DQd10-
DQ0-
GND_DR
DQ2+
DQ2-
V
DQd6-
DQd8+
DQd9-
DQd10+
DQ0+
DQ1+
DQ1-
W
V_DR
DQd9+ GND_DR DQd11+ DQd11- GND_DR
GND_DR DQd7-
V_A
GND
GND_E
V_E
DQd0-
DQd2+
DQd3-
V_A
GND
V_E
GND_E
DQd0+
V_DR
DQd3+ GND_DR DQd6+
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Y
20
Figure 2-3. See Package Number NXA0292A
The center ground pins are for thermal dissipation and must be soldered to a ground plane to
ensure
rated
performance.
See
SUPPLY/GROUNDING,
LAYOUT
AND
THERMAL
RECOMMENDATIONS for more information.
10
Device Information
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback
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2.4
SNAS502E – JULY 2011 – REVISED MARCH 2013
Ball Descriptions and Equivalent Circuits
Table 2-1. Analog Front-End and Clock Balls
Ball No.
Name
Equivalent Circuit
Description
Differential signal I- and Q-inputs. In the Non-Dual
Edge Sampling (Non-DES) Mode, each I- and Qinput is sampled and converted by its respective
channel with each positive transition of the CLK
input. In Non-ECM (Non-Extended Control Mode)
and DES Mode, both channels sample the I-input.
In Extended Control Mode (ECM), the Q-input
may optionally be selected for conversion in DES
Mode by the DEQ Bit (Addr: 0h, Bit 6).
VA
50k
AGND
H1/J1
N1/M1
VinI+/VinQ+/-
VCMO
100
Control from VCMO
VA
Each I- and Q-channel input has an internal
common mode bias that is disabled when DCcoupled Mode is selected. Both inputs must be
either AC- or DC-coupled. The coupling mode is
selected by the VCMO Pin.
In Non-ECM, the full-scale range of these inputs is
determined by the FSR Pin; both I- and Qchannels have the same full-scale input range. In
ECM, the full-scale input range of the I- and Qchannel inputs may be independently set via the
Control Register (Addr: 3h and Addr: Bh). Note
that the high and low full-scale input range setting
in Non-ECM corresponds to the mid and minimum
full-scale input range in ECM.
50k
AGND
The input offset may also be adjusted in ECM.
VA
U2/V1
50k
AGND
CLK+/-
VA
100
VBIAS
50k
Differential Converter Sampling Clock. In the NonDES Mode, the analog inputs are sampled on the
positive transitions of this clock signal. In the DES
Mode, the selected input is sampled on both
transitions of this clock. This clock must be ACcoupled.
AGND
VA
V2/W1
AGND
DCLK_RST+/-
100
VA
Differential DCLK Reset. A positive pulse on this
input is used to reset the DCLKI and DCLKQ
outputs of two or more ADC12D800/500RFs in
order to synchronize them with other
ADC12D800/500RFs in the system. DCLKI and
DCLKQ are always in phase with each other,
unless one channel is powered down, and do not
require a pulse from DCLK_RST to become
synchronized. The pulse applied here must meet
timing relationships with respect to the CLK input.
Although supported, this feature has been
superseded by AutoSync. (1)
AGND
(1)
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
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Table 2-1. Analog Front-End and Clock Balls (continued)
Ball No.
Name
Equivalent Circuit
Description
VA
VCMO
C2
200k
VCMO
Enable AC
Coupling
8 pF
GND
Bandgap Voltage Output or LVDS Common-mode
Voltage Select. This pin provides a buffered
version of the bandgap output voltage and is
capable of sourcing/sinking 100 uA and driving a
load of up to 80 pF. Alternately, this pin may be
used to select the LVDS digital output commonmode voltage. If tied to logic-high, the 1.2V LVDS
common-mode voltage is selected; 0.8V is the
default.
VA
B1
Common Mode Voltage Output or Signal Coupling
Select. If AC-coupled operation at the analog
inputs is desired, this pin should be held at logiclow level. This pin is capable of sourcing/ sinking
up to 100 µA. For DC-coupled operation, this pin
should be left floating or terminated into highimpedance. In DC-coupled Mode, this pin provides
an output voltage which is the optimal commonmode voltage for the input signal and should be
used to set the common-mode voltage of the
driving buffer.
VBG
GND
VA
C3/D3
Rext+/-
V
External Reference Resistor terminals. A 3.3 kΩ
±0.1% resistor should be connected between
Rext+/-. The Rext resistor is used as a reference
to trim internal circuits which affect the linearity of
the converter; the value and precision of this
resistor should not be compromised.
GND
VA
C1/D2
Rtrim+/-
V
Input Termination Trim Resistor terminals. A 3.3
kΩ ±0.1% resistor should be connected between
Rtrim+/-. The Rtrim resistor is used to establish
the calibrated 100Ω input impedance of VinI, VinQ
and CLK. These impedances may be fine tuned
by varying the value of the resistor by a
corresponding percentage; however, the tuning
range and performance is not specified for such
an alternate value.
GND
VA
Tdiode_P
E2/F3
GND
Tdiode+/-
VA
Temperature Sensor Diode Positive (Anode) and
Negative (Cathode) Terminals. This set of pins is
used for die temperature measurements. It has
not been fully characterized.
Tdiode_N
GND
12
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Table 2-1. Analog Front-End and Clock Balls (continued)
Ball No.
Name
Equivalent Circuit
Description
VA
Y4/W5
50k
AGND
RCLK+/-
100
VA
VBIAS
50k
Reference Clock Input. When the AutoSync
feature is active, and the ADC12D800/500RF is in
Slave Mode, the internal divided clocks are
synchronized with respect to this input clock. The
delay on this clock may be adjusted when
synchronizing multiple ADCs. This feature is
available in ECM via Control Register (Addr: Eh).
(1)
AGND
VA
100:
Y5/U6
V6/V7
100:
RCOut1+/RCOut2+/-
+
Reference Clock Output 1 and 2. These signals
provide a reference clock at a rate of CLK/4, when
enabled, independently of whether the ADC is in
Master or Slave Mode. They are used to drive the
RCLK of another ADC12D800/500RF, to enable
automatic synchronization for multiple ADCs
(AutoSync feature). The impedance of each trace
from RCOut1 and RCOut2 to the RCLK of another
ADC12D800/500RF should be 100Ω differential.
Having two clock outputs allows the autosynchronization to propagate as a binary tree. Use
the DOC Bit (Addr: Eh, Bit 1) to enable/ disable
this feature; default is disabled. (1)
A GND
(1)
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
Table 2-2. Control and Status Balls
Ball No.
Name
Equivalent Circuit
VA
V5
DES
GND
Description
Dual Edge Sampling (DES) Mode select. In the
Non-Extended Control Mode (Non-ECM), when
this input is set to logic-high, the DES Mode of
operation is selected, meaning that the VinI input
is sampled by both channels in a time-interleaved
manner. The VinQ input is ignored. When this
input is set to logic-low, the device is in Non-DES
Mode, i.e. the I- and Q-channels operate
independently. In the Extended Control Mode
(ECM), this input is ignored and DES Mode
selection is controlled through the Control Register
by the DES Bit (Addr: 0h, Bit 7); default is NonDES Mode operation.
VA
V4
Calibration Delay select. By setting this input logichigh or logic-low, the user can select the device to
wait a longer or shorter amount of time,
respectively, before the automatic power-on selfcalibration is initiated. This feature is pin-controlled
only and is always active during ECM and NonECM.
CalDly
GND
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Table 2-2. Control and Status Balls (continued)
Ball No.
Name
Equivalent Circuit
VA
D6
CAL
GND
Description
Calibration cycle initiate. The user can command
the device to execute a self-calibration cycle by
holding this input high a minimum of tCAL_H after
having held it low a minimum of tCAL_L. If this input
is held high at the time of power-on, the automatic
power-on calibration cycle is inhibited until this
input is cycled low-then-high. This pin is active in
both ECM and Non-ECM. In ECM, this pin is
logically OR'd with the CAL Bit (Addr: 0h, Bit 15)
in the Control Register. Therefore, both pin and bit
must be set low and then either can be set high to
execute an on-command calibration.
VA
B5
Calibration Running indication. This output is
logic-high while the calibration sequence is
executing. This output is logic-low otherwise.
CalRun
GND
VA
50 k:
U3
V3
PDI
PDQ
Power Down I- and Q-channel. Setting either input
to logic-high powers down the respective I- or Qchannel. Setting either input to logic-low brings the
respective I- or Q-channel to a operational state
after a finite time delay. This pin is active in both
ECM and Non-ECM. In ECM, each Pin is logically
OR'd with its respective Bit. Therefore, either this
pin or the PDI and PDQ Bit in the Control Register
can be used to power-down the I- and Q-channel
(Addr: 0h, Bit 11 and Bit 10), respectively.
GND
VA
A4
Test Pattern Mode select. With this input at logichigh, the device continuously outputs a fixed,
repetitive test pattern at the digital outputs. In the
ECM, this input is ignored and the Test Pattern
Mode can only be activated through the Control
Register by the TPM Bit (Addr: 0h, Bit 12).
TPM
GND
VA
A5
Non-Demuxed Mode select. Setting this input to
logic-high causes the digital output bus to be in
the 1:1 Non-Demuxed Mode. Setting this input to
logic-low causes the digital output bus to be in the
1:2 Demuxed Mode. This feature is pin-controlled
only and remains active during ECM and NonECM.
NDM
GND
14
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Table 2-2. Control and Status Balls (continued)
Ball No.
Name
Equivalent Circuit
VA
Y3
FSR
GND
VA
W4
DDRPh
GND
Description
Full-Scale input Range select. In Non-ECM, when
this input is set to logic-low or logic-high, the fullscale differential input range for both I- and Qchannel inputs is set to the lower or higher FSR
value, respectively. In the ECM, this input is
ignored and the full-scale range of the I- and Qchannel inputs is independently determined by the
setting of Addr: 3h and Addr: Bh, respectively.
Note that the high (lower) FSR value in Non-ECM
corresponds to the mid (min) available selection in
ECM; the FSR range in ECM is greater.
DDR Phase select. This input, when logic-low,
selects the 0° Data-to-DCLK phase relationship.
When logic-high, it selects the 90° Data-to-DCLK
phase relationship, i.e. the DCLK transition
indicates the middle of the valid data outputs. This
pin only has an effect when the chip is in 1:2
Demuxed Mode, i.e. the NDM pin is set to logiclow. In ECM, this input is ignored and the DDR
phase is selected through the Control Register by
the DPS Bit (Addr: 0h, Bit 14); the default is 0°
Mode.
VA
50 k:
B3
ECE
Extended Control Enable bar. Extended feature
control through the SPI interface is enabled when
this signal is asserted (logic-low). In this case,
most of the direct control pins have no effect.
When this signal is de-asserted (logic-high), the
SPI interface is disabled, all SPI registers are
reset to their default values, and all available
settings are controlled via the control pins.
GND
VA
100 k:
C4
SCS
Serial Chip Select bar. In ECM, when this signal is
asserted (logic-low), SCLK is used to clock in
serial data which is present on SDI and to source
serial data on SDO. When this signal is deasserted (logic-high), SDI is ignored and SDO is in
tri-stated.
GND
VA
100 k:
C5
SCLK
Serial Clock. In ECM, serial data is shifted into
and out of the device synchronously to this clock
signal. This clock may be disabled and held logiclow, as long as timing specifications are not
violated when the clock is enabled or disabled.
GND
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Table 2-2. Control and Status Balls (continued)
Ball No.
Name
Equivalent Circuit
Description
VA
100 k:
B4
Serial Data-In. In ECM, serial data is shifted into
the device on this pin while SCS signal is asserted
(logic-low).
SDI
GND
VA
A3
Serial Data-Out. In ECM, serial data is shifted out
of the device on this pin while SCS signal is
asserted (logic-low). This output is tri-stated when
SCS is de-asserted.
SDO
GND
D1, D7, E3, F4,
W3, U7
DNC
NONE
Do Not Connect. These pins are used for internal
purposes and should not be connected, i.e. left
floating. Do not ground.
C7
NC
NONE
Not Connected. This pin is not bonded and may
be left floating or connected to any potential.
Table 2-3. Power and Ground Balls
Ball No.
Name
Equivalent Circuit
A2, A6, B6, C6,
D8, D9, E1, F1,
H4, N4, R1, T1,
U8, U9, W6, Y2,
Y6
VA
NONE
Power Supply for the Analog circuitry. This supply
is tied to the ESD ring. Therefore, it must be
powered up before or with any other supply.
G1, G3, G4, H2,
J3, K3, L3, M3,
N2, P1, P3, P4,
R3, R4
VTC
NONE
Power Supply for the Track-and-Hold and Clock
circuitry.
A11, A15, C18,
D11, D15, D17,
J17, J20, R17,
R20, T17, U11,
U15, U16, Y11,
Y15
VDR
NONE
Power Supply for the Output Drivers.
A8, B9, C8, V8,
W9, Y8
VE
NONE
Power Supply for the Digital Encoder.
NONE
Bias Voltage I-channel. This is an externally
decoupled bias voltage for the I-channel. Each pin
should individually be decoupled with a 100 nF
capacitor via a low resistance, low inductance
path to GND.
NONE
Bias Voltage Q-channel. This is an externally
decoupled bias voltage for the Q-channel. Each
pin should individually be decoupled with a 100 nF
capacitor via a low resistance, low inductance
path to GND.
J4, K2
L2, M4
16
Device Information
VbiasI
VbiasQ
Description
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Table 2-3. Power and Ground Balls (continued)
Ball No.
Name
Equivalent Circuit
A1, A7, B2, B7,
D4, D5, E4, K1,
L1, T4, U4, U5,
W2, W7, Y1, Y7,
H8:N13
Description
GND
NONE
Ground Return for the Analog circuitry.
F2, G2, H3, J2,
K4, L4, M2, N3,
P2, R2, T2, T3,
U1
GNDTC
NONE
Ground Return for the Track-and-Hold and Clock
circuitry.
A13, A17, A20,
D13, D16, E17,
F17, F20, M17,
M20, U13, U17,
V18, Y13, Y17,
Y20
GNDDR
NONE
Ground Return for the Output Drivers.
A9, B8, C9, V9,
W8, Y9
GNDE
NONE
Ground Return for the Digital Encoder.
Table 2-4. High-Speed Digital Outputs
Ball No.
Name
Equivalent Circuit
Description
VDR
K19/K20
L19/L20
DCLKI+/DCLKQ+/-
-
+
+
-
Data Clock Output for the I- and Q-channel data
bus. These differential clock outputs are used to
latch the output data and, if used, should always
be terminated with a 100Ω differential resistor
placed as closely as possible to the differential
receiver. Delayed and non-delayed data outputs
are supplied synchronously to this signal. In 1:2
Demux Mode or Non-Demux Mode, this signal is
at ¼ or ½ the sampling clock rate, respectively.
DCLKI and DCLKQ are always in phase with each
other, unless one channel is powered down, and
do not require a pulse from DCLK_RST to
become synchronized.
DR GND
VDR
K17/K18
L17/L18
ORI+/ORQ+/-
-
+
+
-
Out-of-Range Output for the I- and Q-channel.
This differential output is asserted logic-high while
the over- or under-range condition exists, i.e. the
differential signal at each respective analog input
exceeds the full-scale value. Each OR result
refers to the current Data, with which it is clocked
out. If used, each of these outputs should always
be terminated with a 100Ω differential resistor
placed as closely as possible to the differential
receiver.
DR GND
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Table 2-4. High-Speed Digital Outputs (continued)
18
Ball No.
Name
J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
B19/B20
B18/C17
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20
W19/W20
W18/V17
DI11+/DI10+/DI9+/DI8+/DI7+/DI6+/DI5+/DI4+/DI3+/DI2+/DI1+/DI0+/·
DQ11+/DQ10+/DQ9+/DQ8+/DQ7+/DQ6+/DQ5+/DQ4+/DQ3+/DQ2+/DQ1+/DQ0+/-
A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
C10/D10
A10/B10
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11
V10/U10
Y10/W10
DId11+/DId10+/DId9+/DId8+/DId7+/DId6+/DId5+/DId4+/DId3+/DId2+/DId1+/DId0+/·
DQd11+/DQd10+/DQd9+/DQd8+/DQd7+/DQd6+/DQd5+/DQd4+/DQd3+/DQd2+/DQd1+/DQd0+/-
Device Information
Equivalent Circuit
Description
VDR
-
+
+
-
I- and Q-channel Digital Data Outputs. In NonDemux Mode, this LVDS data is transmitted at the
sampling clock rate. In Demux Mode, these
outputs provide ½ the data at ½ the sampling
clock rate, synchronized with the delayed data, i.e.
the other ½ of the data which was sampled one
clock cycle earlier. Compared with the DId and
DQd outputs, these outputs represent the later
time samples. If used, each of these outputs
should always be terminated with a 100Ω
differential resistor placed as closely as possible
to the differential receiver.
DR GND
VDR
-
+
+
-
Delayed I- and Q-channel Digital Data Outputs. In
Non-Demux Mode, these outputs are tri-stated. In
Demux Mode, these outputs provide ½ the data at
½ the sampling clock rate, synchronized with the
non-delayed data, i.e. the other ½ of the data
which was sampled one clock cycle later.
Compared with the DI and DQ outputs, these
outputs represent the earlier time samples. If
used, each of these outputs should always be
terminated with a 100Ω differential resistor placed
as closely as possible to the differential receiver.
DR GND
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
3
Electrical Specifications
3.1
Absolute Maximum Ratings (1) (2)
Supply Voltage (VA, VTC, VDR, VE)
2.2V
Supply Difference
max(VA/TC/DR/E)- min(VA/TC/DR/E)
0V to 100 mV
−0.15V to (VA + 0.15V)
Voltage on Any Input Pin (except VIN+/-)
VIN+/- Voltage Range
-0.5V to 2.5V
Ground Difference
max(GNDTC/DR/E) -min(GNDTC/DR/E)
Input Current at Any Pin
0V to 100 mV
(3)
±50 mA
ADC12D800/500RF Package Power Dissipation at TA ≤ 85°C (3)
3.45 W
ESD Susceptibility (4)
Human Body Model
2500V
Charged Device Model
1000V
Machine Model
250V
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
3.2
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the
Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific
performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0V, unless otherwise specified.
When the input voltage at any pin exceeds the power supply limits, i.e. less than GND or greater than VA, the current at that pin should
be limited to 50 mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple
pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC
JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package
thermal resistances from junction to case.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated
assembler) then rapidly being discharged.
Operating Ratings (1) (2)
−40°C ≤ TA ≤ 85°C
ADC12D800/500RF Ambient Temperature Range (Standard JEDEC thermal model)
Junction Temperature Range
TJ ≤ 135°C
Supply Voltage (VA, VTC, VE)
+1.8V to +2.0V
Driver Supply Voltage (VDR)
+1.8V to VA
VIN+/- Voltage Range (3)
-0.4V to 2.4V (DC)
VIN+/- Differential Voltage (3)
1.0V (d.c.-coupled @ 100% duty cycle)
2.0V (d.c.-coupled @ 20% duty cycle)
2.8V (d.c.-coupled @ 10% duty cycle)
VIN+/- Current Range (3)
±50 mA (a.c.-coupled)
VIN+/- Power
15.3 dBm (maintaining common mode voltage,
a.c.-coupled)
17.1 dBm (not maintaining common-mode voltage,
a.c.-coupled)
Ground Difference
max(GNDTC/DR/E) -min(GNDTC/DR/E)
(1)
(2)
(3)
0V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the
Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific
performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0V, unless otherwise specified.
Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.
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Operating Ratings(1)(2) (continued)
CLK+/- Voltage Range
0V to VA
Differential CLK Amplitude
0.4VP-P to 2.0VP-P
Common Mode Input Voltage
VCMO - 150 mV < VCMI < VCMO +150 mV
Package Thermal Resistance (1) (2)
3.3
(1)
Package
θJA
θJC1
θJC2
292-Ball BGA Thermally Enhanced Package
16°C/W
2.9°C/W
2.5°C/W
Soldering process must comply with Texas Instrument's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. See
(Note 2).
Reflow temperature profiles are different for lead-free and non-lead-free packages.
(2)
3.4
Converter Electrical Characteristics
Static Converter Characteristics
Unless otherwise specified, the following apply after calibration for VA = VDR = VTC = VE = +1.9V; I- and Q-channels, ACcoupled, unused channel terminated to AC ground, FSR Pin = High; CL = 10 pF; Differential, AC coupled Sine Wave
Sampling Clock, fCLK = 800/500 MHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Non-Extended Control
Mode; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; Non-Demux Non-DES Mode;
Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.
(1) (2) (3)
Symbol
Parameter
Conditions
ADC12D800RF
Typ
Resolution with No Missing Codes
Lim
ADC12D500RF
Typ
12
Lim
Units
(Limits)
12
bits
INL
Integral Non-Linearity
(Best fit)
1 MHz DC-coupled over-ranged
sine wave
±2.5
±7.25
±2.5
±7.25
LSB (max)
DNL
Differential Non-Linearity
1 MHz DC-coupled over-ranged
sine wave
±0.4
±0.95
±0.4
±0.95
LSB (max)
VOFF
Offset Error
5
5
LSB
VOFF_ADJ
Input Offset Adjustment Range
Extended Control Mode
±45
±45
mV
PFSE
Positive Full-Scale Error
See
(4)
NFSE
Negative Full-Scale Error
See
(4)
Out-of-Range Output Code (5)
(VIN+) − (VIN−) > + Full Scale
4095
4095
(VIN+) − (VIN−) < − Full Scale
0
0
(1)
±30
±30
mV (max)
±30
±30
mV (max)
The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may
damage this device.
V
A
TO INTERNAL
CIRCUITRY
I/O
GND
(2)
(3)
(4)
(5)
20
To ensure accuracy, it is required that VA, VTC, VE and VDR be well-bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-2. For relationship between Gain
Error and Full-Scale Error, see Specification Definitions for Gain Error.
This parameter is ensured by design and is not tested in production.
Electrical Specifications
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3.5
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Converter Electrical Characteristics
Dynamic Converter Characteristics (1)
Symbol
Parameter
Conditions
Bandwidth
ADC12D800RF
Typ
Lim
ADC12D500RF
Typ
Lim
Units
(Limits)
Non-DES Mode, DESCLKIQ Mode
-3dB (2)
2.7
2.7
GHz
-6dB
3.1
3.1
GHz
-9dB
3.5
3.5
GHz
-12dB
4.0
4.0
GHz
-3dB (2)
1.2
1.2
GHz
-6dB
2.3
2.3
GHz
-9dB
2.7
2.7
GHz
-12dB
3.0
3.0
GHz
-3dB (2)
1.75
1.75
GHz
-6dB
2.7
2.7
GHz
D.C. to Fs/2
±0.1
±0.02
dB
D.C. to Fs
±0.3
±0.3
dB
D.C. to 3Fs/2
±0.5
±0.3
dB
D.C. to Fs/2
±0.7
±0.6
dB
D.C. to Fs
±2.2
±1.0
dB
D.C. to 3Fs/2
±3.4
±1.8
dB
D.C. to Fs/2
±0.6
±0.3
dB
D.C. to Fs
±1.1
±0.7
dB
D.C. to 3Fs/2
±2.0
±1.1
dB
D.C. to Fs/2
±0.4
±0.2
dB
D.C. to Fs
±0.7
±0.5
dB
D.C. to 3Fs/2
±1.0
±0.7
dB
10-18
10-18
Error/Sam
ple
50.4
50.7
dB
FIN = 2670MHz ± 2.5MHz @
‑13dBFS
-76
-74
dBFS
-63
-61
dBc
FIN = 2070MHz ± 2.5MHz @
‑13dBFS
-80
-79
dBFS
-67
-66
dBc
FIN = 2670MHz ± 2.5MHz @
‑16dBFS
-87
-85
dBFS
-71
-69
dBc
FIN = 2070MHz ± 2.5MHz @
‑16dBFS
-85
-84
dBFS
-69
-68
dBc
DESI, DESQ Mode
DESIQ Mode
Gain Flatness
Non-DES Mode
DESI, DESQ Mode
DESIQ Mode
DESCLKIQ Mode
CER
Code Error Rate
NPR
Noise Power Ratio
DES Mode, fc,notch = Fs/4,
Notch width = 5% of Fs/2
IMD3
3rd order Intermodulation
Distortion
DES Mode
(1)
(2)
This parameter is ensured by design and/or characterization and is not tested in production.
The -3dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half at this
frequency, the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be effectively used
in an application. The ADC may be used at input frequencies above the -3dB FPBW point, for example, into the 5th and 6th Nyquist
zones. Depending on system requirements, it is only necessary to compensate for the insertion loss.
Copyright © 2011–2013, Texas Instruments Incorporated
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Electrical Specifications
21
ADC12D500RF, ADC12D800RF
SNAS502E – JULY 2011 – REVISED MARCH 2013
www.ti.com
Converter Electrical Characteristics
Dynamic Converter Characteristics (1) (continued)
Symbol
Parameter
Conditions
Noise Floor Density
50Ω single-ended input
termination, DES Mode
ADC12D800RF
Typ
Lim
ADC12D500RF
Typ
Lim
Units
(Limits)
-152.2
-150.5
dBm/Hz
-151.2
-149.6
dBFS/Hz
Non-DES Mode (3) (4) (5)
ENOB
Effective Number of Bits
SINAD
Signal-to-Noise Plus Distortion
Ratio
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
2nd Harm
3rd Harm
SFDR
(3)
(4)
(5)
22
Second Harmonic Distortion
Third Harmonic Distortion
Spurious-Free Dynamic Range
AIN = 125 MHz @ -0.5 dBFS
9.6
9.1
9.7
9.1
bits (min)
AIN = 248 MHz @ -0.5 dBFS
9.5
9.7
bits
AIN = 498 MHz @ -0.5 dBFS
9.5
9.6
bits
AIN = 998 MHz @ -0.5 dBFS
9.2
9.3
bits
AIN = 1498 MHz @ -0.5 dBFS
8.9
9.2
bits
AIN = 125 MHz @ -0.5 dBFS
59.7
60.0
dB
AIN = 248 MHz @ -0.5 dBFS
58.7
59.9
dB
AIN = 498 MHz @ -0.5 dBFS
58.8
59.4
dB
AIN = 998 MHz @ -0.5 dBFS
57.1
58.0
dB
AIN = 1498 MHz @ -0.5 dBFS
55.1
56.9
AIN = 125 MHz @ -0.5 dBFS
60.2
AIN = 248 MHz @ -0.5 dBFS
59.8
60.3
dB
AIN = 498 MHz @ -0.5 dBFS
59.7
59.7
dB
AIN = 998 MHz @ -0.5 dBFS
58.4
58.7
dB
57.5
60.4
dB
57.5
57.3
dB (min)
AIN = 1498 MHz @ -0.5 dBFS
56.4
AIN = 125 MHz @ -0.5 dBFS
-69.0
AIN = 248 MHz @ -0.5 dBFS
-65.1
-70.3
dB
AIN = 498 MHz @ -0.5 dBFS
-66.0
-70.4
dB
AIN = 998 MHz @ -0.5 dBFS
-63.2
-66.5
dB
AIN = 1498 MHz @ -0.5 dBFS
-60.8
-67.4
dB
AIN = 125 MHz @ -0.5 dBFS
80.1
80.5
dBc
AIN = 248 MHz @ -0.5 dBFS
78.5
77.0
dBc
AIN = 498 MHz @ -0.5 dBFS
77.9
85.7
dBc
AIN = 998 MHz @ -0.5 dBFS
67.9
81.0
dBc
AIN = 1498 MHz @ -0.5 dBFS
63.1
76.5
dBc
AIN = 125 MHz @ -0.5 dBFS
76.3
77.6
dBc
AIN = 248 MHz @ -0.5 dBFS
66.5
73.8
dBc
AIN = 498 MHz @ -0.5 dBFS
73.2
74.4
dBc
AIN = 998 MHz @ -0.5 dBFS
66.8
68.5
dBc
AIN = 1498 MHz @ -0.5 dBFS
68.8
70.3
AIN = 125 MHz @ -0.5 dBFS
73.4
AIN = 248 MHz @ -0.5 dBFS
66.5
73.8
dBc
AIN = 498 MHz @ -0.5 dBFS
71.2
72.0
dBc
AIN = 998 MHz @ -0.5 dBFS
66.8
68.5
dBc
AIN = 1498 MHz @ -0.5 dBFS
63.1
70.5
dBc
-62.5
62.5
-71.4
74.3
dB
-62.5
dB (max)
dBc
62.5
dBc (min)
The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic
performance vs. temperature in the Typical Performance Plots to see typical performance from cold to room temperature (-40°C to
25°C).
The Fs/2 spur was removed from all the dynamic performance spectifications.
Typical dynamic performance at Fin = 248 MHz, 498 MHz, 998 MHz, and 1498 MHz is ensured by design and/or characterization and is
not tested in production.
Electrical Specifications
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: ADC12D500RF ADC12D800RF
ADC12D500RF, ADC12D800RF
www.ti.com
SNAS502E – JULY 2011 – REVISED MARCH 2013
Converter Electrical Characteristics
Dynamic Converter Characteristics (1) (continued)
Symbol
Parameter
Conditions
ADC12D800RF
Typ
Lim
ADC12D500RF
Typ
Lim
Units
(Limits)
DES Mode (1) (2)
ENOB
SINAD
SNR
THD
2nd Harm
3rd Harm
SFDR
(1)
(2)
Effective Number of Bits
Signal-to-Noise Plus Distortion
Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
Spurious-Free Dynamic Range
AIN = 125 MHz @ -0.5 dBFS
9.4
9.6
bits
AIN = 248 MHz @ -0.5 dBFS
9.3
9.5
bits
AIN = 498 MHz @ -0.5 dBFS
9.3
9.5
bits
AIN = 998 MHz @ -0.5 dBFS
9
9.2
bits
AIN = 1498 MHz @ -0.5 dBFS
8.7
8.7
bits
AIN = 125 MHz @ -0.5 dBFS
58.6
59.6
dB
AIN = 248 MHz @ -0.5 dBFS
57.8
59.0
dB
AIN = 498 MHz @ -0.5 dBFS
57.9
59.0
dB
AIN = 998 MHz @ -0.5 dBFS
55.8
57.3
dB
AIN = 1498 MHz @ -0.5 dBFS
54.0
53.5
dB
AIN = 125 MHz @ -0.5 dBFS
59.1
60.0
dB
AIN = 248 MHz @ -0.5 dBFS
58.5
59.6
dB
AIN = 498 MHz @ -0.5 dBFS
58.3
59.4
dB
AIN = 998 MHz @ -0.5 dBFS
56.2
58.1
dB
AIN = 1498 MHz @ -0.5 dBFS
54.3
53.8
dB
AIN = 125 MHz @ -0.5 dBFS
-68.3
-70.5
dB
AIN = 248 MHz @ -0.5 dBFS
-65.9
-67.8
dB
AIN = 498 MHz @ -0.5 dBFS
-68.5
-69.2
dB
AIN = 998 MHz @ -0.5 dBFS
-66.2
-64.5
dB
AIN = 1498 MHz @ -0.5 dBFS
-65.3
-64.6
dB
AIN = 125 MHz @ -0.5 dBFS
80.3
81.3
dBc
AIN = 248 MHz @ -0.5 dBFS
83.2
78.0
dBc
AIN = 498 MHz @ -0.5 dBFS
80.5
79.5
dBc
AIN = 998 MHz @ -0.5 dBFS
80.2
69.5
dBc
AIN = 1498 MHz @ -0.5 dBFS
71.8
75.1
dBc
AIN = 125 MHz @ -0.5 dBFS
72.5
75.1
dBc
AIN = 248 MHz @ -0.5 dBFS
68.8
72.4
dBc
AIN = 498 MHz @ -0.5 dBFS
76.1
73.8
dBc
AIN = 998 MHz @ -0.5 dBFS
68.1
67.8
dBc
AIN = 1498 MHz @ -0.5 dBFS
73.2
66.2
dBc
AIN = 125 MHz @ -0.5 dBFS
71.9
74.3
dBc
AIN = 248 MHz @ -0.5 dBFS
67.6
70.4
dBc
AIN = 498 MHz @ -0.5 dBFS
68.8
70.3
dBc
AIN = 998 MHz @ -0.5 dBFS
66.2
67.3
dBc
AIN = 1498 MHz @ -0.5 dBFS
63.9
56.7
dBc
The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic
performance vs. temperature in the Typical Performance Plots to see typical performance from cold to room temperature (-40°C to
25°C).
These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature
is used to reduce the interleaving timing spur amplitude, which occurs at Fs/2-Fin, and thereby increase the SFDR, SINAD and ENOB.
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: ADC12D500RF ADC12D800RF
Electrical Specifications
23
ADC12D500RF, ADC12D800RF
SNAS502E – JULY 2011 – REVISED MARCH 2013
3.6
www.ti.com
Converter Electrical Characteristics
Analog Input/Output and Reference Characteristics
Symbol
Parameter
Conditions
ADC12D800RF
Typ
Lim
ADC12D500RF
Typ
Lim
Units
(Limits)
Analog Inputs
VIN_FSR
Analog Differential Input Full Scale Non-Extended Control Mode
Range
FSR Pin Low
530
mVP-P
(min)
670
670
mVP-P
(max)
730
730
mVP-P
(min)
870
mVP-P
(max)
530
600
FSR Pin High
600
800
800
870
Extended Control Mode
CIN
RIN
FM(14:0) = 0000h
600
600
mVP-P
FM(14:0) = 4000h (default)
800
800
mVP-P
FM(14:0) = 7FFFh
1000
1000
mVP-P
Analog Input Capacitance,
Non-DES Mode (1)
Differential
0.02
0.02
pF
Each input pin to ground
1.6
1.6
pF
Analog Input Capacitance,
DES Mode (1)
Differential
0.08
0.08
pF
Each input pin to ground
2.2
2.2
pF
100
100
Ω
Differential Input Resistance
Common Mode Output
VCMO
Common Mode Output Voltage
ICMO = ±100 µA
TC_VCMO
Common Mode Output Voltage
Temperature Coefficient
ICMO = ±100 µA
VCMO_LVL
VCMO input threshold to set
DC-coupling Mode
CL_VCMO
Maximum VCMO Load Capacitance See
1.25
1.15
1.35
1.25
1.15
V (min)
1.35
V (max)
(2)
38
38
ppm/°C
0.63
0.63
V
(1)
80
80
pF
Bandgap Reference
VBG
Bandgap Reference Output
Voltage
IBG = ±100 µA
TC_VBG
Bandgap Reference Voltage
Temperature Coefficient
IBG = ±100 µA (2)
CL_VBG
Maximum Bandgap Reference
load Capacitance
See
(1)
(2)
24
1.25
1.15
1.35
32
1.25
1.15
V (min)
1.35
V (max)
32
ppm/°C
(1)
80
80
pF
This parameter is ensured by design and is not tested in production.
This parameter is ensured by design and/or characterization and is not tested in production.
Electrical Specifications
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: ADC12D500RF ADC12D800RF
ADC12D500RF, ADC12D800RF
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3.7
Converter Electrical Characteristics
I-Channel to Q-Channel Characteristics
Symbol
X-TALK
(1)
(2)
Parameter
Conditions
(1)
ADC12D800RF
Typ
Lim
ADC12D500RF
Typ
Lim
Units
(Limits)
Offset Match
See
2
2
LSB
Positive Full-Scale Match
Zero offset selected in
Control Register
2
2
LSB
Negative Full-Scale Match
Zero offset selected in
Control Register
2
2
LSB
Phase Matching (I, Q)
fIN = 1.0 GHz (2)
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