June 2006
Rev 0.91
National Semiconductor
Evaluation Board Instruction Manual
ADC10DL065, 10-Bit, 65 Msps, 3.3V A/D Converter
ADC12DL040, 12-Bit, 40 Msps, 3.0V A/D Converter
ADC12DL065, 12-Bit, 65 Msps, 3.3V A/D Converter
© 2006 National Semiconductor Corporation.
1
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Table of Contents
1.0 Introduction ......................................................................................................................................... 3
2.0 Board Assembly .................................................................................................................................. 3
3.0 Quick Start........................................................................................................................................... 4
4.0 Functional Description ........................................................................................................................ 4
4.1 Input (signal conditioning) circuitry ............................................................................................ 4
4.2 ADC reference circuitry ............................................................................................................ 4
4.3 ADC clock circuit ..................................................................................................................... 4
4.4 Digital Data Output ................................................................................................................... 5
4.5 Power Supply Connections ........................................................................................................ 5
4.6 Power Requirements ................................................................................................................. 5
5.0 Installing the ADC12DL040 Evaluation Board .................................................................................. 5
6.0 Obtaining Best Results ........................................................................................................................ 5
6.1 Clock Jitter ............................................................................................................................... 5
6.2 Coherent Sampling.................................................................................................................... 6
7.0 Evaluation Board Specifications ......................................................................................................... 6
8.0 Hardware Schematic............................................................................................................................ 7
9.0 Assembly Drawing .............................................................................................................................. 8
10.0 Evaluation Board Bill of Materials.................................................................................................... 9
A1.0 Operating in the Computer Mode ..................................................................................................... 11
A2.0 Summary Tables of Test Points, Connectors, and Jumper Settings................................................. 11
A2.1 Test Points .......................................................................................................................... 11
A2.2 Connectors.......................................................................................................................... 11
A2.3 Jumper settings ................................................................................................................... 11
A2.4 Clock Circuit Solder Jumper settings ................................................................................. 13
A2.5 VADC/VD Solder Jumper settings .................................................................................... 13
2
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dynamic performance in the form of SNR, SINAD, THD
and SFDR.
1.0 Introduction
This Design Kit (consisting of an Evaluation Board and
this manual) is designed to ease evaluation and design-in
of National Semiconductor’s ADC10DL065,
ADC12DL040, or ADC12DL065 Analog-to-Digital
Converters. Further reference in this manual to the
ADC12DL040 is meant to also include the ADC10DL065
and ADC12DL065 unless otherwise specified.
The digital output data from Channel A of the
ADC12DL040 is available at pins A4 (MSB) through A15
of the WaveVision™ (WV4) connector J10 and pins 8
(MSB) through 19 of header JP4. Channel B output data
is available at pins B4 (MSB) through B15 of the WV4
connector J10 and pins 8 (MSB) through 19 of header
JP5. Disregard the two LSB’s for the ADC10DL065.
The evaluation board can be used in either of two modes.
In the Manual mode suitable test equipment can be used
with the board to evaluate the ADC12DL040
performance. In the Computer mode evaluation is
simplified by connecting the board to the WaveVision™
Digital Interface Board (order number WAVEVSN BRD
4.0), which is connected to a personal computer through
a USB port and running WaveVision™ software,
operating under Microsoft Windows. The software can
perform an FFT on the captured data upon command
and, in addition to a frequency domain plot, shows
JP13
Vref Select
2.0 Board Assembly
The ADC12DL040 Evaluation Board comes preassembled. Refer to the Bill of Materials in Section 10 for
a description of components, to Figure 1 for major
component placement and to Section 8 for the Evaluation
Board schematic.
U1
ADC12DL040/065
JP17
J3
PD Ext.CLK
J4
Ext.Vref
JP5
Ch. B
Header
JP20
Vcm Select Ch. B
Input
Signal
Ch. B
JP19
MUX
Input
Signal
Ch. A
J10
WV4
Conn.
TP8
VREF
J5,J11
(on back)
JP22
Vcm Select Ch. A
JP4
Ch. A
Header
TP5
VADC
JP21
DF/DCS
JP18
OE TP4
TP6
VDR
VD
GND +5V
TP9
+5V
JP23
WV Power
JR1
POWER
Figure 1. Major Component and Jumper Locations
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3.0 Quick Start
Refer to Figure 1 for locations of jumpers, test points and
major components. The board is configured by default to
use a crystal clock source, internal 1.0V reference, offset
binary output data format, duty cycle stabilizer on, and
parallel output mode. Refer to Section 4.0 and the
Appendix for more information on jumper settings.
4.0 Functional Description
For Stand-Alone operation:
This section describes the input circuitry for Channel A,
which is the same as Channel B.
1.
2.
3.
4.
Connect a clean +5V power supply to pin 2 of Power
Connector JR1. Pin 1 is ground.
Connect a signal from
a 50-Ohm source to
connector J1 (for Channel A). The ADC input signal
can be observed at TP2. Because of isolation
resistor R54 and the scope probe capacitance, the
input signal at TP2 may not have the same frequency
response as the ADC input. Be sure to use a
bandpass filter before the Evaluation Board.
Adjust the input signal amplitude as needed to
ensure that the signal does not over-range by
examinining a histogram of the output data.
The digitized signal is available at pins 8 (MSB)
through 19 (LSB) of JP4. See board schematic in
Section 8.
For Computer Mode operation:
You must have version 4.1.7 or later of the WaveVision™
software to properly test this board. You can download
the latest version from:
http://www.national.com/appinfo/adc/wv4.html
1.
2.
3.
4.
5.
Connect the evaluation board to the WaveVision™
Digital Interface Board. See the WaveVision™ Board
Manual for operation of that board. Connect the
WaveVision™ board to the computer using a USB
cable.
Connect a clean +5V power supply to pin 2 of Power
Connector JR1. Pin 1 is ground. Short jumper JP23.
With jumper JP23 shorted, the WaveVision™ board
gets power from the ADC12DL040 Evaluation Board,
therefore it does not require a separate power
supply. DO NOT provide separate power supplies
to the Evaluation Board and the WaveVision
Board when JP23 is shorted.
Connect a clock source to connector J3. Connect a
signal from a 50-Ohm source to connector J1 (for
Channel A). The ADC input signal can be observed
at TP2. Because of isolation resistor R54 and the
scope probe capacitance, the input signal at TP2
may not have the same frequency response as the
ADC input. Be sure to use a bandpass filter before
the Evaluation Board.
Adjust the input signal amplitude as needed to
ensure that the signal does not over-range by
examinining a histogram of the output data with the
WaveVision™ software.
Select which channel the WV4 board collects data
from with the Product Board Settings item under
the Settings menu. See the WaveVision™ Board
Manual for instructions for gathering and analyzing
data.
4
The ADC12DL040 Evaluation Board schematic is shown
in Section 8. A list of test points and jumper settings can
be found in the Appendix.
4.1 Input (signal conditioning) circuitry
The input signal to be digitized should be applied to SMA
connector J1. This 50 Ohm input is intended to accept a
low-noise sine wave signal of up to 2V peak-to-peak
amplitude. To accurately evaluate the dynamic
performance of this converter, the input test signal will
have to be passed through a high-quality bandpass filter
with at least 14-bit equivalent noise and distortion
characteristics.
Signal transformer T1 provides single-ended to
differential conversion. The voltage VRMA from the ADC,
or an adjustable voltage from VR2 sets the common
mode of the input signal by biasing the center tap of the
secondary of T1. When VR2 is used, the voltage should
be set within the acceptable range of the ADC, 0.5 to
2.0V. Jumper JP22 selects the source of the common
mode voltatge. Short pins 1-2 of JP22 to use VR2. The
default setting is to use VRMA from the ADC, with pins 2-3
shorted.
Jumper JP20 selects the source of the common mode
voltatge for Channel B. Short pins 1-2 of JP20 to use
VR1. The default setting is to use VRMB from the ADC,
with pins 2-3 shorted.
4.2 ADC reference circuitry
The ADC12DL040 can use an internal 1.0V reference, an
internal 0.5V reference, or an external reference. The
reference is selected using jumper JP13. The default is
the internal 1.0V reference, shorting pins 1-2.
An adjustable reference circuit is provided on the board.
The simple circuit here is not temperature stable and is
not recommended for your final design solution. The
reference circuit will generate a voltage in the range of
0.5 to 2.0V. The ADC12DL040 is specified to operate
with VREF in the range of 0.8 to 1.2V, with a nominal
value of 1.0V. The reference voltage is set with VR1. This
circuit can also be used as a common mode voltage
source (see section 4.1). Short pins 3-4 of JP13 to use
VR1.
Short pins 7-8 of JP13 to select the internal 0.5V
reference. Short pins 5-6 of JP13 to use the external
reference voltage applied at connector J4.
4.3 ADC clock circuit
Solder jumpers are used to select the path of the clock to
the ADC, the latches, and the output data connectors.
While not as convenient as pin-type jumpers, these
introduce less distortion into the clock signal.
The clock source is selected with jumper J12 or J13. By
default J12 is shorted and J13 is open, which selects the
crystal oscillator. To use an external clock source,
connect the signal to connector J3, open J12 , and short
J13.
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between the Digital Interface Board and the host. See the
the WaveVision™ 4.0 Digital Interface Board manual for
details.
There are a number of solder jumpers which allow
changes to the clock path, inversion of the clock, etc.
Please refer to the schematic of Section 8 and the
Appendix for more information.
6.0 Obtaining Best Results
4.4 Digital Data Output
The default mode is Parallel Mode. This is set with JP19
open. In Parallel Mode the digital output data from
Channel A of the ADC12DL040 is available at pins A4
(MSB) through A15 of the WV4 connector J10 and pins 8
(MSB) through 19 of header JP4. Channel B output data
is available at pins B4 (MSB) through B15 of the WV4
connector J10 and pins 8 (MSB) through 19 of header
JP5. When capturing data with WaveVision™ software,
select which channel the WV4 board collects data from
with the Product Board Settings item under the
Settings menu. See the WaveVision™ Board Manual for
instructions for gathering and analyzing data
Shorting JP19 puts the ADC in Multiplex Mode. In this
mode the data from both channels is output on pins
DA0:DA11 of the ADC. Refer to the ADC12DL040
datasheet for more detail of this function. To use Multiplex
mode, open solder jumper J11, and short J5. The
WaveVision™ software should be set to collect data on
Channel A. The channel selected for output to
WaveVision™ software is selected with JP16. With JP16
open, Channel A data is selected. Channel B is selected
by shorting pins 1-2 of JP16.
Obtaining the best results with any ADC requires both
good circuit techniques and a good PC board layout. The
layout is taken care of with the design of this evaluation
board. Note, the plots shown in Section 6 are for
illustrative purposes only. They were not taken with the
ADC12DL040.
6.1 Clock Jitter
When any circuitry is added after a signal source, some
jitter is almost always added to that signal. Jitter in a clock
signal, depending upon how bad it is, can degrade
dynamic performance. We can see the effects of jitter in
the frequency domain (FFT) as "leakage" or "spreading"
around the input frequency, as seen in Figure 2a.
Compare this with the more desirable plot of Figure 2b.
Note that all dynamic performance parameters (shown to
the right of the FFT) are improved by eliminating clock
jitter.
Because the divided signal from the Digital Interface
Board and the oscillator at Y1 are not synchronized, bad
data will sometimes be taken because we are latching
data when the outputs are in transition. This data might
be as you see in Figure 3 or Figure 4.
4.5 Power Supply Connections
Power to this board is supplied through power connector
JR1. The only supply needed is +5V at pin 2 plus ground
at pin 1.
When using the ADC12DL040 Evaluation Board with the
the WaveVision™ Digital Interface Board, a 5V logic
power supply for the interface board is passed through
the WV4 connector to the Digital Interface Board when
jumper JP23 is installed. DO NOT provide separate
power supplies to the Evaluation Board and the
WaveVision Board when JP23 is shorted.
4.6 Power Requirements
Voltage and current requirements for the ADC12DL040
Evaluation Board mode are:
•
+5.0V at 500 mA (1A when connected to the Digital
Interface Board).
5.0 Installing the ADC12DL040 Evaluation Board
The evaluation board requires power supplies as
described in Section 4.5. An appropriate signal source
should be connected to the Signal Input SMA connector
J1 or J2. When evaluating dynamic performance, an
appropriate signal generator (such as the HP8644B or the
R&S SME-03) with 50 Ohm source impedance should be
connected to the Analog Input connector J1 and/or J2
through an appropriate bandpass filter as even the best
signal generator available can not produce a signal pure
enough to evaluate the dynamic performance of an ADC.
Figure 2a. Jitter causes a spreading around
the input signal, as well as undesirable
signal spurs.
The problem of Figure 3 is obvious, but it is not as easy to
see the problem in Figure 4, where the only thing we see
is small excursions beyond the normal envelope.
Compare Figure 3 and Figure 4 with Figure 5.
If your data capture results in something similar to what is
shown here in Figure 3 or in Figure 4, take another
sample. It may take a few trials to get good data.
The use of WAVEVSN BRD 4.0 Digital Interface Board
eliminates this problem, so that board is recommended.
If this board is used in conjunction with the the
WaveVision™ 4.0 Digital Interface Board and
WaveVision™ software, a USB must be connected
5
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Figure 2b. Eliminating or minimizing clock
jitter results in a more desirable FFT that is
more representative of how the ADC actually
performs.
Figure 4 Marginal data capture that results from trying
to capture data that is near but not right at the point
where the ADC outputs are in transition.
Figure 5. Normal data capture.
Figure 3. Poor data capture resulting from trying to
capture data while the ADC outputs are in transition
CY fin
SS = fs
6.2 Coherent Sampling
Artifacts can result when we perform an FFT on a
digitized waveform, producing inconsistent results when
testing repeatedly. The presence of these artifacts means
that the ADC under test may perform better than the
measurements would indicate.
We can eliminate the need for windowing and get more
consistent results if we observe the proper ratios between
the input and sampling frequencies. We call this coherent
sampling. Coherent sampling greatly increases the
spectral resolution of the FFT, allowing us to more
accurately evaluate the spectral response of the A/D
converter. When we do this, however, we must be sure
that the input signal has high spectral purity and stability
and that the sampling clock signal is extremely stable with
minimal jitter.
Coherent sampling of a periodic waveform occurs when a
prime integer number of cycles exists in the sample
window. The relationship between the number of cycles
sampled (CY), the number of samples taken (SS), the
signal input frequency (fin) and the sample rate (fs), for
coherent sampling, is
6
CY, the number of cycles in the data record, must be a
prime integer number and SS, the number of samples in
the data record, must be a factor of 2 integer.
Further, fin (signal input frequency) and fs (sampling rate)
should be locked to each other so that the relationship
between the two frequencies is exact. Locking the two
signal sources to each other also causes whatever
sample-to-sample clock edge timing variation (jitter) that
is present in the two signals to cancel each other.
Windowing (an FFT Option under WaveVision™) should
be turned off for coherent sampling.
7.0 Evaluation Board Specifications
Board Size:
Power Requirements:
Clock Frequency
Range:
Analog Input
Nominal Voltage:
Impedance:
5" x 5.63" (12.7 cm x 14.29 cm)
+5.0V, 1 A (ADC12DL040EVAL
and WaveVision™ 4.0 Board
40/65 MHz
2VP-P
50 Ohms
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8.0 Hardware Schematic
VGATE
R9
VGATE
L1
1
10K
5
R2
11
3
74VCX86
C4
CLK_A
10uF
74VCX86
1
VGATE
1
3
N/C VCC
U8C
GND OUT
1
2
8
J12
R16
22
osc/sm/6
JP16
R11
22
10
4
C68
0.1uF
R10
1
2
U21D
9
U21C
74VCX86
VCC
jumper/sm
3.3V
3.0V
R85
205
22
VGATE
JP30
U22
VADC
ABb
4
1
2
U23
4
VDR
C90
10uF
0.1uF
+5V
U16
LM1117/TO-252
10K
6
5
U10
10K
R18
22
74VCX86
NC7SZ86/SOT23
NC7SZ86/SOT23
100
2
3
4
5
6
7
8
9
4
3
C36
1
1
2
1
J13
jumper
default=open
0.1uF
2
J14
jumper
default=open
2
3
4
5
1
2
3
4
VADC
R86
R20
100
C37 10uF
VDR
open
R29
100
TP1
SIG_IN
VcomB
1
C84
RN2
100
CLK_B
11
VD
C77
10uF
C39
0.1uF
C38 0.1uF
8
7
6
5
1
C40
C78
10uF
10pF
D1
D2
D3
D4
D5
D6
D7
D8
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
1
2
3
4
5
6
7
8
0.1uF
1
.
2
R35
49.9
18pF
R36
open
C44
4
3
VRMB
VRPB
VRNB
VREF
C45
R39
33
T1-6T
18pF
VADC
Place near U1
VRMA
VRMB
C46 0.1uF
C47 0.1uF
C83
10uF
C48
0.1uF
VRPA
VRPB
VRNA
VRPA
VRMA
C49 0.1uF
VRNA
C50 0.1uF
C52
1uF
C85
10uF
C55 0.1uF
VRNB
C86
10uF
C51
1uF
DNP
DNP
VcomA
TP2
SIG_IN
C59
1
6
1
.
2
VD
8
7
6
5
100
100
8
7
6
5
11
1
ABb
CLK
U17
LM1117/TO-252
3
2
3
4
5
6
7
8
9
100
100
8
7
6
5
C61
RN8
VDR
C81
VADC
R62
33
18pF
1
1
3
2
3
4
5
6
7
8
9
100
OEA
R64
R65
10K
10K
CLK_A
11
10K
TP8
1
R66
150
VADC
R68
3
J4
External Vref
JP13
2
4
6
8
JP20
VR1
1k
1uF
VcomB
VRMB
332
VCC
JP21
VREF
2 1
4 3
6 5
8 7
DF/DCS
C34
C33
4.7uF
0.1uF
R71
10K VRMA
R69
10K
R72
10K
D1
D2
D3
D4
D5
D6
D7
D8
VXTAL
JP5
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DA11
DA10
DA9
DA8
DA7
DA6
1
3
5
7
9
11
13
15
17
19
HDR_Clk
DB10
DB8
DB6
DB4
DB2
DB0
22
CLK
2
4
6
8
10
12
14
16
18
20
TP3
1
R75
200
R79
D1
D2
D3
D4
D5
D6
D7
D8
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DA5
DA4
DA3
DA2
DA1
DA0
22
CLK
1
3
5
7
9
11
13
15
17
19
HDR_Clk
DA10
DA8
DA6
DA4
DA2
DA0
2
4
6
8
10
12
14
16
18
20
Logic Analyzer
OE
C70
0.1uF
C71
0.1uF
C72
0.1uF
JP23
C73
0.1uF
W3V3
VcomA
VRMA
TP9
PWR
GND
2
J10
FutureBus Connector
5V_IN
L7
0.5uH
1
C1
47uF
C2
47uF
7
DB11
DA11
DB10
DA10
DB9
DA9
DB8
DA8
DB7
DA7
DB6
DA6
DB5
DA5
DB4
DA4
DB3
DA3
DB2
DA2
DB0
DA0
+5V
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TPG1
GND
TPG3
GND
TPG2
GND
TPG4
GND
1
JR1
1
1
+5V
1
332
1
2
3
1
1
R83
C82
47uF
R76
200
0
JP22
C65
0.1uF
+5V
0.5uH
C3
47uF
D24
C24
B24
A24
D23
C23
B23
A23
D22
C22
B22
A22
D21
C21
B21
A21
D20
C20
B20
A20
D19
C19
B19
A19
D18
C18
B18
A18
D17
C17
B17
A17
D16
C16
B16
A16
D15
C15
B15
A15
D14
C14
B14
A14
D13
C13
B13
A13
D12
C12
B12
A12
D11
C11
B11
A11
D10
C10
B10
A10
D9
C9
B9
A9
D8
C8
B8
A8
D7
C7
B7
A7
D6
C6
B6
A6
D5
C5
B5
A5
D4
C4
B4
A4
D3
C3
B3
A3
D2
C2
B2
A2
D1
C1
B1
A1
2
LM4040-2.5
DA11
DA9
DA7
DA5
DA3
DA1
74LCX574/SO
VCC
3.3V_XTAL
L8
0.5uH
C88
47uF
C89
10uF
R88
124
R90
205
JP4
D24
C24
B24
A24
D23
C23
B23
A23
D22
C22
B22
A22
D21
C21
B21
A21
D20
C20
B20
A20
D19
C19
B19
A19
D18
C18
B18
A18
D17
C17
B17
A17
D16
C16
B16
A16
D15
C15
B15
A15
D14
C14
B14
A14
D13
C13
B13
A13
D12
C12
B12
A12
D11
C11
B11
A11
D10
C10
B10
A10
D9
C9
B9
A9
D8
C8
B8
A8
D7
C7
B7
A7
D6
C6
B6
A6
D5
C5
B5
A5
D4
C4
B4
A4
D3
C3
B3
A3
D2
C2
B2
A2
D1
C1
B1
A1
1uF
VR2
1k
C87
10uF
100
C64
U19
2
OE
UNDER RANGE
DB1
DA1
3
R78
VOUT
GREEN LED
D2
OVER RANGE
332
VIN
R89
200 1/4W
VGATE
R77
U24
LM1117/TO-252
3
Logic Analyzer
L5
R74
150
+5V
DB11
DB9
DB7
DB5
DB3
DB1
WV_Clk
RED LED
D1
VGATE
OE
2
3
4
5
C62
0.1uF
1
R70
1
1
2
3
2
LM4040-2.5
1
3
5
7
VLAT
R34
205
VREF
100
C63
U18
1
VADC
C80
10uF
R31
124
R82
200 1/4W
2
1
332
C9
10uF
DB5
DB4
DB3
DB2
DB1
DB0
U13
2
4
R63
VGATE
VGATE
L4
0.5uH
C8
47uF
DA[0..11]
4
3
JP18 OEB
2
1
MUX
3.3V
2
VOUT
74LCX574/SO
VD
10uF
JP19
VIN
22
CLK
RP4
VGATE
R67
16
15
14
13
12
11
10
9
10uF
1
2
TP7
DB[0..11]
11
C20
0.1uF
1
2
3
4
5
6
7
8
RP3
0.1uF
RN7
1
2
3
4
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
C76
10uF
+5V
OE
D1
D2
D3
D4
D5
D6
D7
D8
VDR
0.5uH
R81
200 1/4W
C7
47uF
R28
124
74LCX574/SO
U12
4
3
RN6
C60
3
T1-6T
4
3
1
2
18pF
R61
open
R60
49.9
2
3
4
5
C21
C58
100
1
2
3
4
RN4
RN5
1
2
3
4
L3
DB11
DB10
DB9
DB8
DB7
DB6
RP2
2
3
4
5
6
7
8
9
C54
0.1uF
C56
open
4
0.1uF
ADC12DL040/65
VADC
R56
33
T1
R54
470
U1
RN3
1
2
VD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vd
DB5
DB4
DB3
DB2
DB1
DB0/ABb
OEB
DR GND
DA11
DA10
DA9
DA8
DA7
DA6
Vd
R51
100
1
C57
0.1uF
J1
VIN-A
VinBVinB+
AGND
VrmB
VrpB
VrnB
Vref
AGND
Va
AGND
MUX
VrnA
VrpA
VrmA
VinA+
VinA-
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C53 0.1uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
open
2.5V
2
R15
124
74LCX574/SO
U11
C79
C42
0.1uF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C43
AGND
Va
Va
AGND
CLK
PD
DR GND
DB11
DB10
DB9
DB8
DB7
DB6
Vdr
DR GND
DGND
6
1
2
3
4
5
R37
33
T2
AGND
Va
Va
AGND
DF/DCS
OEA
DR GND
DA0
DA1
DA2
DA3
DA4
DA5
Vdr
DR GND
DGND
C41
16
15
14
13
12
11
10
9
22
10uF
0.1uF
R30
470
J2
VIN-B
C5
10uF
RP1
RN1
1
2
VOUT
L6
0.5uH
U20
1
2
3
4
TP10
VXTAL
1
R1
10K
10uF
J3
EXT CLK
VIN
R17
1
2
1
JP17
PD
ADJ
U8B
4
3
ADJ
1
2
VADC
R13
174
TP6
R25
1
2
2
R14
100
TP5
VADC
C69
open
1
default=short
C91
VD
VGATE
R12
10K
74VCX86
JP14
TP4
jumper/sm
74VCX86
CLK_B
9
jumper
VGATE
C75
10uF
VD
WV_Clk
8
R8
22
JP26
R3
10
12
VGATE
R4
22
5
N/C N/C
13
11
10K
VADC
0.5uH
R80
200 1/4W
1
2
C35
0.1uF
6
JP25
default=open
R19
1
2
ADJ
1
jumper
2
VCC
default=short
JP27
C6
47uF
R24
open
J5
1
74VCX86
L2
R5
124
1
VCC
J11
jumper
2
3.0V
2
VOUT
16V TANT C-size
74VCX86
12
U8A
C67
0.1uF
Y2
VIN
22
U21B
2
R6
10K
U15
LM1117/TO-252
HDR_Clk
6
R23
22
13
1
3
4
2
U8D
XTAL PWR
3
U21A
C74
10uF
1
R21
10K
Do not populate.
VD
0.5uH
+5V
1
R87
10K
2
1
1
2
open
1
JP24
1
2
R22
ADJ
JP28
JP29
1
VCC
VXTAL
A2 VCC
A1
WP
A0 SCL
GND SDA
24C02
8
7
6
5
C66
0.1uF
9.0 Assembly Drawing
8
http://www.national.com
10.0 Evaluation Board Bill of Materials
QTY
REFERENCE
DESCRIPTION
VALUE
Package
Manufacturer
Manufacturer P/N
C1,C2,C3,C6,C7,C8,C82,
CAP TANT
47uF
SMD 7343
KEMET
T491D476K010AS
10
C4,C5,C9,C74,C75,C76,C80, CAP TANT
10uF
SMD 3216
KEMET
T491A106K006AS
13
C20,C38,C39,C40,C41,C42, CAP CER
0.1uF
SMD 0508
Panasonic
ECY-29RE104KV
10uF
SMD 0805
Panasonic
ECJ-2FF0J106Z
4.7uF
SMD 3216
Kemet
T491A475K010AS
0.1uF
SMD 0603
Panasonic
ECJ-1VB1C104K
8
C88
C87,C89,C90
C46,C47,C48,C54,C56,C57,
C59
10
C21,C37,C77,C78,C79,C81, CAP CER
C83,C85,C86,C91
1
C33
8
C34,C67,C68,C69,C70,C71, CAP CER
CAP TANT
C72,C73
5
C35,C36,C62,C65,C66
CAP CER
0.1uF
SMD 0805
Panasonic
ECJ-2VB1E104K
4
C43,C45,C58,C61
CAP CER
18pF
SMD 0603
Panasonic
ECJ-1VC1H180J
2
C44,C60
CAP
open
4
C49,C50,C53,C55
CAP CER
0.1uF
SMD 0402
Panasonic
ECJ-0EB1A104K
2
C51,C52
CAP CER
open
SMD 402
Panasonic
ECJ-0EF0J105Z
2
C63,C64
CAP CER
1uF
SMD 805
Panasonic
ECJ-2YB1A105K
1
C84
CAP CER.
10pF
SMD 0603
Panasonic
ECJ-1VC1H100D
1
D1
LED RED
OVER RANGE
5MM
Lumex OPTO/COMP
SSL-LX5093IT
1
D2
LED GREEN
UNDER RANGE
5MM
Lumex OPTO/COMP
SSL-LX5093GT
2
JP4,JP5
CON
HDR 2X10
.100 DUAL STR 60POS
Sullins Elect
PBC30DADN
2
JP13,JP21
CON
HDR 4X2
.100 DUAL STR 60POS
Sullins Elect
PBC30DADN
8
JP14,JP16,JP17,JP23,JP27, CON
HDR 1X2
.100 SINGL STR 36POS
Sullins Elect
PBC36SAAN
N/A
JP28,JP29,JP30
1
JP18
CON
HDR 2X2
.100 DUAL STR 60POS
Sullins Elect
PBC30DADN
1
JP19
CON
HDR 1X2
.100 SINGL STR 36POS
Sullins Elect
PBC36SAAN
2
JP20,JP22
CON
HDR 1X3
.100 SINGL STR 36POS
Sullins Elect
PBC36SAAN
1
JP24
CON
HDR 1X2
.100 SINGL STR 36POS
Sullins Elect
PBC36SAAN
2
JP25,JP26
JUMPER
jumper/sm
1
JR1
CONN
ECL power
2 Pos 5.08MM
Phoenix Contacts
1755736
1
J1
CON
VIN-A
SMA RECEPTACLE
Amphenol
901-144-8RFX
1
J2
CON
VIN-B
SMA RECEPTACLE
Amphenol
901-144-8RFX
1
J3
CON
EXT CLK
SMA RECEPTACLE
Amphenol
901-144-8RFX
1
J4
CON
External Vref
SMA RECEPTACLE
Amphenol
901-144-8RFX
5
J5,J11,J12,J13,J14
JUMPER
jumper
N/A
N/A
N/A
1
J10
CONN RECEPT
FutureBus Con
RT/A 2MM 96POS 30AU
Tyco
5536511-3
8
L1,L2,L3,L4,L5,L6,L7,L8
FERRITE_CHOKE
2.5 TURNS
JW MILLER MAG.
FB20020-4B-RC
4
RN1,RN3,RN6,RN8
RES ARRAY
100
2 RES SMD
PANASONIC
EXB-V4V101JV
4
RN2,RN4,RN5,RN7
RES ARRAY
100
0603 x 4
PANASONIC
EXB-V8V101JV
4
RP1,RP2,RP3,RP4
RES-NET
22
16-PIN SMD
CTS CORP.
768163220G
14
R1,R6,R10,R17,R19,R21,
RES
10K
SMD 0603
PANASONIC
ERJ-3EKF1002V
7
R2,R3,R4,R11,R16,R18,R23 RES
22.1
SMD 0603
PANASONIC
ERJ-3EKF22R1V
5
R5,R15,R28,R31,R88
124
SMD 0603
PANASONIC
ERJ-3EKF1240V
R22,R25,R63,R64,R65,R69,
R71,R72
RES
9
http://www.national.com
1
R8
RES
22
SMD 0603
3
R9,R12,R87
RES
open
N/A
PANASONIC
ERJ-3EKF22R1V
1
R13
RES
174
SMD 0603
PANASONIC
ERJ-3EKF1740V
4
R14,R20,R68,R78
RES
100
SMD 0603
PANASONIC
ERJ-3EKF1000V
2
R24,R86
RES
open
N/A
2
R29,R51
RES
100
SMD 0603
PANASONIC
ERJ-3EKF1000V
2
R30,R54
RES
475
SMD 0603
PANASONIC
ERJ-3EKF4750V
3
R34,R85,R90
RES
205
SMD 0603
PANASONIC
ERJ-3EKF2050V
2
R35,R60
RES
49.9
SMD 0603
PANASONIC
ERJ-3EKF49R9V
2
R36,R61
RES
open
N/A
4
R37,R39,R56,R62
RES
33.2
SMD 0603
PANASONIC
P33.2HCT
2
R66,R74
RES
150
SMD 0603
PANASONIC
ERJ-3EKF1500V
4
R67,R70,R77,R83
RES
332
SMD 0603
PANASONIC
ERJ-3EKF3320V
2
R75,R76
RES
200
SMD 0805
PANASONIC
P200CCT
1
R79
RES
0
SMD 0603
PANASONIC
RC0603JR-070RL
4
R80,R81,R82,R89
RES
200
SMD 1206
PANASONIC
ERJ-8GEYJ201V
4
TPG1,TPG2,TPG3,TPG4
Hdr.
HDR 1X1
.100 SINGL STR 36POS
Sullins Elect
PBC36SAAN
2
TP1,TP2
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP3
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP4
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP5
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP6
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP7
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP8
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP9
TP
.040"D
MINI .040"D
Keystone Elec.
5002
1
TP10
TP
.040"D
MINI .040"D
Keystone Elec.
5002
2
T1,T2
XFMR
.015-300MHZ
SM
MINI-CIRCUITS
T1-6T X65
N/A
N/A
N/A
1
U1
IC
DUAL ADC
64-TQFP
NATIONAL
2
U8,U21
IC
EXCL-OR QUAD
14SOIC
FAIRCHILD
74VCX86M
4
U10,U11,U12,U13
IC
FLIP FLOP OCT
20SOIC
FAIRCHILD
4LCX574WMX
4
U15,U16,U17,U24
IC
LM1117/TO-252
TO252
NATIONAL
LM1117DT-ADJ
2
U18,U19
IC
LM4040-2.5
SOT-23-5
NATIONAL
LM4040CIM3-2.5CT
1
U20
IC
EEPROM 2K
ATMEL
AT24C02BN-10SU-1.8
2
U22,U23
IC
8SOIC
EX-OR GATE 2-IN SOT-23-5
Texas Instrument
SN74LVC1G86DBVR
2
1
VR1,VR2
Y2
POT
OSC
1k
40.00MHz or
66.00MHZ
BOURNS INC
PLETRONICS
3296Y-1-102
SM7745HV-66.0M-Y9 or
SM7745HV-40.00M-Y9
3/8" SQ CERM SL MT
5X7MM CERAMIC
10
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APPENDIX
A1.0 Operating in the Computer Mode
The ADC12DL040 Evaluation Board is compatible with the WaveVision™ 4.0 Digital Interface Board and WaveVision™
software. You must have version 4.1.7 or later of the WaveVision™ software to properly test this board. You can
download the latest version from: http://www.national.com/appinfo/adc/wv4.html
When connected to the Digital Interface Board, data capture is easily controlled from a personal computer operating in
the Windows environment. The data samples that are captured can be observed on the PC video monitor in the time and
frequency domains. The FFT analysis of the captured data yields insight into system noise and distortion sources and
estimates of ADC dynamic performance such as SINAD, SNR and THD. Select which channel the WV4 board collects
data from with the Product Board Settings item under the Settings menu. See the Digital Interface Board manual for
more information.
A2.0 Summary Tables of Test Points, Connectors, and Jumper Settings
A2.1 Test Points
Test Points on the ADC12DL040 Evaluation Board
TP 1
Input Signal Channel B
TP 2
Input Signal Channel A
TP3
3.3V from WaveVision Board
TP4
ADC Digital Supply
TP5
ADC Analog Supply
TP6
ADC Output Driver Supply
TP7
Logic Supply
TP8
VREF
TP9
+5V
TPG1 – TPG4
Ground
A2.2 Connectors
JR1 Connector - Power Supply Connections
P1-1
GND
Power Supply Ground
P1-2
+5V
+5V Power Supply
A2.3 Jumper settings
Note: Default settings are in bold
JP13 : VREF selection jumper settings
Connect 1-2
Use internal 1.0V reference
Connect 3-4
Use voltage from VR1 as reference voltage
Connect 5-6
Use external voltage from J4 as reference voltage
Connect 7-8
Use internal 0.5V reference
JP14 : Latch Invert
Connect 1-2
Invert clock for latches
1-2 OPEN
Do not invert clock
JP16 : Latch Invert in Multiplex Mode with ABb as clock
Connect 1-2
Channel B data is selected
1-2 OPEN
Channel A data is selected
11
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JP17 : Power Down
Connect 1-2
Put ADC in Power Down mode
1-2 OPEN
ADC is in normal operation
JP18 : Output Enable
Connect 1-2
Channel B outputs are in high impedance state
Connect 3-4
Channel A outputs are in high impedance state
1-2 OPEN
Channel B outputs are enabled
3-4 OPEN
Channel A outputs are enabled
JP19 : Multiplex/Parallel Mode
Connect 1-2
Outputs are in Multiplex Mode on Channel A outputs
1-2 OPEN
Outputs are in parallel mode
JP20 : Channel B Vcm selection
Connect 1-2
Use voltage from VR1 as common mode voltage for Channel B
Connect 2-3
Use common mode voltage from ADC for Channel B
JP21 : Data Format / Duty Cycle Stabilizer
Connect 1-2
Select Output format of Offset Binary, Duty Cycle Stabilizer is OFF
Connect 3-4
Select Output format of 2’s complement, Duty Cycle Stabilizer is OFF
Connect 5-6
Select Output format of 2’s complement, Duty Cycle Stabilizer is ON
Connect 7-8
Select Output format of Offset Binary, Duty Cycle Stabilizer is ON
JP22 : Channel A Vcm selection
Connect 1-2
Use voltage from VR2 as common mode voltage for Channel A
Connect 2-3
Use common mode voltage from ADC for Channel A
JP23 : Wavevision Power (when used with WaveVision™ 4.0 Digital Interface Board
Connect 1-2
A +5V supply is applied to the WaveVision Board or the ADC12DL040 Board, but not both
1-2 OPEN
Separate supplies are used for the WaveVision Board and the ADC12DL040 Board
JP24 : Power for Crystal Oscillator
Connect 1-2
Power is applied to the crystal
1-2 OPEN
No power for the crystal
JP27 : Latch Invert
Connect 1-2
Invert clock for latches
1-2 OPEN
Do not invert clock
JP28 : Latch Invert
Connect 1-2
Invert clock for latches
1-2 OPEN
Do not invert clock
JP29 : Latch Invert
Connect 1-2
Invert clock for latches
1-2 OPEN
Do not invert clock
12
http://www.national.com
JP30 : Latch Invert
Connect 1-2
Invert clock for latches
1-2 OPEN
Do not invert clock
A2.4 Clock Circuit Solder Jumper settings
Solder jumpers are used to select the path of the clock to the ADC, the latches, and the capture device at J7. While not
as convenient as pin-type jumpers, these introduce less distortion into the clock signal.
By default the following jumpers are OPEN:
J5, J13, J14
By default the following jumpers are shorted:
J11, J12
A2.5 VADC/VD Solder Jumper settings
Either J25 or J26 is shorted to set the voltage for the ADC’s analog (VADC) and digital (VD) supplies.
J26 is shorted to produce a VADC and VD of 3.0V, which is the default value for the ADC12DL040.
J25 is shorted to produce a VADC and VD of 3.3V, which is the default value for the ADC12DL065.
13
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BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF NATIONAL
SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU HAVE READ AND AGREED
TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE WITH THEM, CONTACT THE VENDOR
WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF THE UNUSED PRODUCT FOR A REFUND OF THE
PURCHASE PRICE PAID, IF ANY.
The ADC12DL040/065 Evaluation Boards are intended for product evaluation purposes only and are not intended for resale to end
consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for
compliance with any other electromagnetic compatibility requirements.
National Semiconductor Corporation does not assume any responsibility for use of any circuitry or software supplied or described. No
circuit patent licenses are implied.
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury to the user.
National Semiconductor Corporation
Americas
Tel:
1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
2. A critical component is any component in a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 699508 6208
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the right at any time
without notice to change said circuitry and specifications.
14
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IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
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products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
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