ADC12DL080EVAL

ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 ADC12DL080 Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling Check for Samples: ADC12DL080 FEATURES DESCRIPTION • • • • • • • The ADC12DL080 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-andhold circuit to minimize power consumption while providing excellent dynamic performance and a 600 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC12DL080 achieves 11.0 effective bits at Nyquist and consumes just 447mW at 80 MSPS. The Power Down feature reduces power consumption to 50 mW. 1 2 Single +3.3V Supply Operation Internal Sample-and-Hold Internal or External Reference Outputs 2.4V to 3.6V Compatible Power Down Mode Duty Cycle Stabilizer Pin Compatible with ADC12DL040, ADC12DL065, ADC12DL066 APPLICATIONS • • • • Instrumentation Communications Receivers Sonar/Radar xDSL, Cable Modems KEY SPECIFICATIONS • • • • • • • • Resolution: 12 Bits Max Conversion Rate: 80 MSPS DNL: ±0.4 LSB (typ) SNR (fIN=40MHz): 69 dB (typ) SNR (fIN=200MHz): 67 dB(typ) SFDR (fIN=40MHz): 82 dB (typ) SFDR (fIN=200MHz): 81 dB (typ) Power Consumption – Operating: 447 mW (typ) – Power Down Mode: 50 mW (typ) The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. Duty cycle stabilization and output data format are selectable. The output data can be set for offset binary or two's complement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL080 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com DGND DRGND 49 DB7 DB8 DB9 DB10 DB11 (MSB) DRGND PD AGND CLK DB6 VDR 50 51 52 53 54 55 56 57 58 59 60 VA 61 62 42 ADC12DL080 (Top View) 8 9 10 41 40 39 33 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) OEB / DRDY DRGND DA11 (MSB) DA10 DA9 DA8 DA7 DA6 VD DGND DRGND DA5 VDR DA4 DA3 DA2 DA1 (LSB) DA0 AGND VA VD 32 16 31 34 30 35 15 29 14 28 36 27 13 26 37 25 12 24 38 23 11 17 VIN A+ VIN A- 43 7 DRGND VRM A 6 OEA / OF VRP A 44 22 REFSEL/DCS VRN A 45 5 21 AGND 4 OF / DOEN AGND VA 46 20 VREF 3 VA VRN B 47 AGND VRP B 48 2 19 VRM B 1 18 VIN BVIN B+ AGND 63 64 AGND VA Connection Diagram Figure 1. TQFP Package See Package Number PAG0064A 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Block Diagram VINA+ VA S/H VINA- 12 Bit 80 MSPS Pipeline Converter AGND Timing Control 3 CLK VD Digital Correction DGND 12 12 DA0 - DA11 Output Buffers VRN A VRM A ~OEA/OF Output Clock VRP A ~OEB/DRDY REFSEL/DCS VDR Reference VREF DRGND OF/DOEN VRN B VRM B 12 VRP B Output Buffers DB0 - DB11 12 Digital Correction PD VD DGND 3 Timing Control 12 Bit 80 MSPS Pipeline Converter VINB+ VINB- S/H VA AGND Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 3 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 15 2 16 1 VINA+ VINB+ VA Differential analog input pins. With a 1.0V reference voltage the differential full-scale input signal level is 2.0 VP-P with each input pin voltage centered on a common mode voltage, VCM. The negative input pins may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. VINA− VINB− AGND 7 VA VREF 11 REFSEL/DCS 13 5 VRPA VRPB 14 4 VRMA VRMB This pin is used in conjunction with REFSEL/DCS (pin 11) to select the internal 1.0V reference, or as the external reference input. If VREF is tied HIGH, the internal 1.0V reference is selected. REFSEL/DCS must be LOW or tied to VRMA or VRMB. If a voltage in the range of 0.8V to 1.2V is applied to this pin, that voltage is used as the reference. VREF should be bypassed to AGND with a 0.1 µF low ESL capacitor when an external reference is used. The nominal external reference voltage is 1.0V but values in the range of 0.8V to 1.2V may be used. REFSEL/DCS must be HIGH or REFSEL/DCStied to VRMA or VRMB. See Table 3 in for more information. AGND VA VA VA 12 6 This pin is used in conjunction with VREF (pin 7) to select the reference source and turn the Duty Cycle Stabilizer (DCS) on or off. When REFSEL/DCS is LOW and VREF is HIGH, the internal 1.0V reference is selected and DCS is On. When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the VREF input. DCS is On. With this pin connected to VRMA or VRMB, DCS is Off. See Table 3 in REFSEL/DCS for more information. VRNA VRNB These are reference bypass pins. These pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins. These pins should not be loaded. VA AGND AGND 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits (continued) Pin No. Symbol Equivalent Circuit Description DIGITAL I/O VD VA 60 Digital clock input. The range of frequencies for this input is as specified in the electrical tables with ensured performance at 80 MHz. The inputs are sampled on the rising edge. CLK AGND DGND VA 21 OF/DOEN selects the output format (OF) or enables the DRDY output (DOEN). The state of this pin also controls the function of pins 22 and 41. When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41 is used as the DRDY output strobe, and pin 22 is used to select the output format. Output Enable for channels A and B are not available in this mode. When OF/DOEN is LOW, the output data format is offset binary. With OF/DOEN tied HIGH, the output format is 2's complement. See Table 4 in OF/DOEN, OEA/OF, and OEB/DRDY for more information. OF/DOEN AGND VD Output Enable for Channel A (OEA ) or Output format (OF). The function of this pin is controlled by the state of pin 21. When DRDY is enabled (pin 21 tied to VRMA or VRMB) this pin sets the output format. When LOW, the output data format is offset binary. When HIGH, the output format is 2's complement. When DRDY is not enabled (pin 21 is LOW or HIGH) this pin is the Output Enable for Channel A. When LOW the outputs for Channel A are active. When HIGH, the outputs for Channel A are in a high impedance state. See Table 4 in OF/DOEN, OEA/OF, and OEB/DRDY for more information. VA 22 OEA/OF AGND DGND VD Output Enable for Channel B (OEB ) or Data Ready Output strobe (DRDY). The function of this pin is controlled by the state of pin 21. When DRDY is enabled (pin 21 tied to VRMA or VRMB) this pin is the DRDY output. The data outputs are synchronized with the falling edge of this signal. This signal switches at the same rate as the input clock. When DRDY is not enabled (pin 21 is LOW or HIGH) this pin is the Output Enable for Channel B. When LOW the outputs for Channel B are active. When HIGH, the outputs for Channel B are in a high impedance state. See Table 4 in OF/DOEN, OEA/OF, and OEB/DRDY for more information. VA 41 OEB/DRDY AGND DGND Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 5 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Pin Descriptions and Equivalent Circuits (continued) Pin No. Symbol Equivalent Circuit Description VD VA 59 PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. PD AGND DGND 24–29 34–39 42–47 52–57 DA0–DA5 DA6-DA11 VDR VA Digital data output pins that make up the 12-bit conversion results of their respective converters. DA0 and DB0 are the LSBs, while DA11 and DB11 are the MSBs of the output word. Output levels are TTL/CMOS compatible. Optimum loading is < 10pF. DB0–DB5 DB6-DB11 AGND DR GND ANALOG POWER 9, 18, 19, 62, 63 VA 3, 8, 10, 17, 20, 61, 64 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors located near the power pins, and with a 10 µF capacitor. The ground return for the analog supply. DIGITAL POWER 33, 48 VD 32, 49 DGND 30, 51 23, 31, 40, 50, 58 6 Positive digital supply pin. This pin should be connected to the same quiet +3.3V source as is VA and be bypassed to DGND with a 0.1 µF capacitor located near the power pins, and with a 10 µF capacitor. The ground return for the digital supply. VDR Positive driver supply pin for the ADC12DL080's output drivers. This pin should be connected to a voltage source of +2.4V to VD and be bypassed to DRGND with a 0.1 µF capacitor. This supply should also be bypassed with a 10 µF capacitor. VDR should never exceed the voltage on VD. All 0.1 µF bypass capacitors should be located near the supply pin. DRGND The ground return for the digital supply for the ADC12DL080's output drivers. These pins should be connected to the system digital ground, but not be connected in close proximity to the ADC12DL080's DGND or AGND pins. See LAYOUT AND GROUNDING (Layout and Grounding) for more details. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) VA, VD, VDR 4.2V ≤ 100 mV |VA–VD| −0.3V to (VA or VD +0.3V) Voltage on Any Input or Output Pin Input Current at Any Pin (4) ±25 mA Package Input Current (4) ±50 mA See (5) Package Dissipation at TA = 25°C ESD Susceptibility Soldering Temperature, Infrared, 10 sec. Human Body Model (6) 2500V Machine Model (6) 250V Charge Device Model 750V (7) 235°C −65°C to +150°C Storage Temperature Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (7) (1) (2) (3) (4) (5) (6) (7) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 64-pin TQFP, θJA is 50°C/W, so PDMAX = 2 Watts at 25°C and 800 mW at the maximum operating ambient temperature of 85°C. Note that the power consumption of this device under normal operation will typically be about 497 mW (447 typical power consumption + 50 mW TTL output loading). The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Reflow Reflow temperature profiles are different for lead-free and non-lead-free packages. Operating Ratings (1) (2) Operating Temperature −40°C ≤ TA ≤ +85°C Supply Voltage (VA, VD) +3.0V to +3.6V Output Driver Supply (VDR) +2.4V to VD −0.05V to (VD + 0.05V) CLK, PD, OF/DOEN, OEA/OF, OEB/DRDY Analog Input Pins 0V to 2.6V VCM 1.0V to 2.0V ≤100mV |AGND–DGND| Clock Duty Cycle (DCS On) 30% to 70% Clock Duty Cycle (DCS Off) 40% to 60% (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 7 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Converter Electrical Characteristics (1) (2) (3) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Parameter Test Conditions Typical (4) Limits (4) Units (Limits) STATIC CONVERTER CHARACTERISTICS 12 Bits (min) INL Resolution with No Missing Codes Integral Non Linearity (5) fIN = 0, Best Fit Method ±0.9 ±3.5 LSB (max) DNL Differential Non Linearity fIN = 0 ±0.4 ±1.0 LSB (max) PGE Positive Gain Error ±0.3 ±3.5 %FS (max) NGE Negative Gain Error ±0.3 ±3.5 %FS (max) TC GE Gain Error Tempco +0.75 -1.1 %FS (max) %FS (min) VOFF Offset Error (VIN+ = VIN−) TC VOFF Offset Error Tempco −40°C ≤ TA ≤ +85°C 10 -0.2 −40°C ≤ TA ≤ +85°C ppm/°C 16 ppm/°C Under Range Output Code 0 0 Over Range Output Code 4095 4095 REFERENCE AND ANALOG INPUT CHARACTERISTICS 1.0 V (min) 2.0 V (max) VCM Common Mode Input Voltage 1.5 VRMA, VRMB Reference Output Voltage 1.5 V CIN VIN Input Capacitance (each pin to GND) (CLK LOW) 8 pF (CLK HIGH) 7 VREF VIN = 1.5 Vdc ±0.5V External Reference Voltage (6) 1.00 Reference Input Resistance pF 0.8 1.2 1 V (min) V (max) MΩ (min) DYNAMIC CONVERTER CHARACTERISTICS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio (7) SINAD Signal-to-Noise and Distortion (7) ENOB Effective Number of Bits (7) THD Total Harmonic Distortion H2 Second Harmonic Distortion (1) (2) (3) (4) (5) (6) (7) 8 0 dBFS Input, Output at −3 dB 600 fIN = 40 MHz, VIN = −1 dBFS 69.3 fIN = 200 MHz, VIN = −1 dBFS 67 fIN = 40 MHz, VIN = −1 dBFS 69 fIN = 200 MHz, VIN = −1 dBFS 66.5 fIN = 40 MHz, VIN = −1 dBFS 11 fIN = 200 MHz, VIN = −1 dBFS 10.75 fIN = 40 MHz, VIN = −1 dBFS −80 fIN = 200 MHz, VIN = −1 dBFS −76.8 fIN = 40 MHz, VIN = −1 dBFS −85 fIN = 200 MHz, VIN = −1 dBFS −84 MHz 67 dBFS (min) 66.5 dBFS (min) dBFS dBFS 10.75 Bits (min) -71 dBc (min) Bits dBc -73 dBc (min) dBc The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. See Figure 2. To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are to AOQL (Average Outgoing Quality Level). Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is recommended for external reference applications. This parameter is specified in units of dBFS - indicating the equivalent value that would be attained with a full-scale input signal Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Converter Electrical Characteristics(1)(2)(3) (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Typical (4) Limits (4) Units (Limits) fIN = 40 MHz, VIN = −1 dBFS −82 -74 dBc (min) fIN = 200 MHz, VIN = −1 dBFS −81 fIN = 40 MHz, VIN = −1 dBFS 82 73 dBc (min) fIN = 200 MHz, VIN = −1 dBFS 81 dBc fIN = 19.6 MHz and 20.2 MHz, each = −6.5 dBFS −70 dBFS ±0.3 %FS ±0.4 %FS 90 dBc Parameter H3 Third Harmonic Distortion SFDR IMD Spurious Free Dynamic Range Intermodulation Distortion Test Conditions dBc INTER-CHANNEL CHARACTERISTICS Channel—Channel Offset Match Channel—Channel Gain Match 10 MHz Tested, Channel; 20 MHz Other Channel Crosstalk DC and Logic Electrical Characteristics (1) (2) (3) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Parameter Test Conditions Typical (4) Limits (4) Units (Limits) DIGITAL INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage VD = 3.6V 2.0 V (min) VIN(0) Logical “0” Input Voltage VD = 3.0V 1.0 V (max) IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN = 0V −10 µA CIN Digital Input Capacitance 5 pF DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 3V VDR = 2.5V 2.3 V (min) VDR = 3V 2.7 V (min) 0.4 V (max) VOUT = 2.5V or 3.3V 100 VOUT = 0V −100 nA nA IOZ TRI-STATE Output Current +ISC Output Short Circuit Source Current VOUT = 0V −20 mA −ISC Output Short Circuit Sink Current VOUT = VDR 20 mA COUT Digital Output Capacitance 5 pF (1) (2) (3) (4) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. See Figure 2. To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 9 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com DC and Logic Electrical Characteristics(1)(2)(3) (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Parameter Test Conditions Typical (4) Limits (4) Units (Limits) 112.5 15 136 mA (max) mA 26 mA (max) mA POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND, VREF = VA PD Pin = VD ID Digital Supply Current PD Pin = DGND PD Pin = VD , fCLK = 0 23 0 IDR Digital Output Supply Current PD Pin = DGND, CL = 10 pF (5) PD Pin = VD, fCLK = 0 15 0 Total Power Consumption PD Pin = DGND, CL = 10 pF (6) PD Pin = VD 447 50 Power Supply Rejection Ratio Rejection of Full-Scale Error with VA = 3.0V vs. 3.6V 80 PSRR (5) (6) mA mA 535 mW (max) mW dB IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Excludes IDR. See Note 5. AC Electrical Characteristics (1) (2) (3) (4) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Parameter Test Conditions Typical (5) Limits (5) Units (Limits) 80 MHz (min) fCLK1 Maximum Clock Frequency fCLK2 Minimum Clock Frequency tCH Clock High Time Duty Cycle Stabilizer On 6.25 3.75 ns (min) tCL Clock Low Time Duty Cycle Stabilizer On 6.25 3.75 ns (min) tCH Clock High Time Duty Cycle Stabilizer Off 6.25 5 ns (min) tCL Clock Low Time Duty Cycle Stabilizer Off 6.25 5 ns (min) tr, tf Clock Rise and Fall Times tCONV Conversion Latency 7 Clock Cycles tOD Data Output Delay after Rising Clock Edge 3.5 ns (min) 11 ns (max) tOSU Output Set up time from data output transition to rising edge of DRDY See (6) 7.2 4 ns (min) tOH Output Hold time from rising edge of DRDY to next data output transition See (6) 5.3 4 ns (min) tAD Aperture Delay 2 ns tAJ Aperture Jitter 0.3 ps rms tDIS Data outputs into Hi-Z Mode 10 ns tEN Data Outputs Active after Hi-Z Mode 10 ns (1) (2) (3) (4) (5) (6) 10 10 MHz 2 7.5 ns (max) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. See Figure 2. To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are to AOQL (Average Outgoing Quality Level). This parameter is ensured by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 AC Electrical Characteristics(1)(2)(3)(4) (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C tPD Parameter Test Conditions Typical (5) Power Down Mode Exit Cycle 0.1 µF on pins 4,5,6,12,13,14; 10 µF between pins 5, 6 and between pins 12, 13 100 Limits (5) Units (Limits) µs VA I/O To Internal Circuitry AGND Figure 2. SPECIFICATION DEFINITIONS APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error (1) Gain Error can also be expressed as Positive Gain Error and Negative Gain Error, which are: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average gain of the converters. INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 11 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12DL080 is ensured not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN−)] required to cause a transition from code 2047 to 2048. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. OVER RANGE RECOVERY TIME is the time required after VIN goes from a specified voltage out of the normal input range to a specified voltage within the normal input range and the converter makes a conversion with its rated accuracy. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC12DL080, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as (2) where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Timing Diagram Sample N + 7 Sample N + 6 Sample N Sample N + 9 Sample N + 10 | VINA Sample N + 8 VINB tAD Clock N 1 FCLK Clock N + 7 90% CLK 90% | 10% tCH 10% tCL tf tr DRDY | Latency ( tCONV ) tOD | | DA0 - DA11 DB0 - DB11 Data N - 1 Data N + 1 Data N tOSU tOH Data N + 2 tDIS tEN OEA | OEB Note: Output Enable inputs are not available when DRDY is enabled Figure 3. Output Timing Transfer Characteristic Figure 4. Transfer Characteristic Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 13 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 0, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C 14 DNL INL Figure 5. Figure 6. DNL vs. fCLK INL vs. fCLK Figure 7. Figure 8. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics DNL, INL (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 0, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C DNL vs. Temperature INL vs. Temperature Figure 11. Figure 12. DNL vs. VDR, VA = VD = 3.6V INL vs. VDR, VA = VD = 3.6V Figure 13. Figure 14. DNL vs. VA INL vs. VA Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 15 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C 16 SNR, SINAD, SFDR vs. VA Distortion vs. VA Figure 17. Figure 18. SNR,SINAD,SFDR vs. VDR, VA = VD = 3.6V Distortion vs. VDR, VA = VD = 3.6V Figure 19. Figure 20. SNR, SINAD, SFDR vs. VCM Distortion vs. VCM Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C SNR, SINAD, SFDR vs. fCLK Distortion vs. fCLK Figure 23. Figure 24. SNR, SINAD, SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle Figure 25. Figure 26. SNR, SINAD, SFDR vs. Clock Duty Cycle (DCS=OFF) Distortion vs. Clock Duty Cycle (DCS=OFF) Figure 27. Figure 28. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 17 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C 18 SNR, SINAD, SFDR vs. VREF Distortion vs. VREF Figure 29. Figure 30. SNR, SINAD, SFDR vs. fIN Distortion vs. fIN Figure 31. Figure 32. SNR, SINAD, SFDR vs. Temperature Distortion vs. Temperature Figure 33. Figure 34. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C tOD vs. VDR, VA = VD = 3.6V Spectral Response @ 20 MHz Input Figure 35. Figure 36. Spectral Response @ 39 MHz Input Spectral Response @ 200 MHz Input Figure 37. Figure 38. Intermodulation Distortion, fIN1= 19.6 MHz, fIN2 = 20.2 MHz Power Consumtion vs. fCLK Figure 39. Figure 40. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 19 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION Operating on a single +3.3V supply, the ADC12DL080 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of using an internal 1.0 Volt or an external reference. Any external reference is buffered onchip to ease the task of driving that pin. The output word rate is the same as the clock frequency, which can be between 10 MSPS and 80 MSPS (typical) with fully specified performance at 80 MSPS. The analog input for both channels is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle stabilization and output data format are selectable. The output data format can be set for offset binary or two's complement. A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW. APPLICATIONS INFORMATION OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC12DL080: 3.0V ≤ VA ≤ 3.6V VD = VA 2.4V ≤ VDR ≤ VD 10 MHz ≤ fCLK ≤ 80 MHz 0.8V ≤ VREF ≤ 1.2V (for an external reference) 1.0V ≤ VCM ≤ 2.0V Analog Inputs There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external reference. The ADC12DL080 has two analog signal input pairs, VIN A+ and VIN A- for one converter and VIN B+ and VIN B- for the other converter. Each pair of pins forms a differential input pair. Reference Pins The ADC12DL080 is designed to operate with an internal 1.0V reference or an external 1.0V reference, but performs well with external reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12DL080. Increasing the reference voltage (and the input signal swing) beyond 1.2V may degrade THD for a full-scale input, especially at higher input frequencies. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The six Reference Bypass Pins (VRPA, VRMA, VRNA, VRPB, VRMB and VRNB) are made available for bypass purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins, as shown in Figure 43. This configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. Loading any of these pins other than VRMA and VRMB may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VRM = 1.5 V VRP = VRM + VREF / 2 VRN = VRM − VREF / 2 20 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 User choice of an on-chip or external reference voltage is provided. The internal 1.0 Volt reference is in use when the the VREF pin is connected to VA. If a voltage in the range of 0.8V to 1.2V is applied to the VREF pin, that is used for the voltage reference. When an external reference is used, the VREF pin should be bypassed to ground with a 0.1 µF capacitor close to the reference input pin. There is no need to bypass the VREF pin when the internal reference is used. Signal Inputs The signal inputs are VIN A+ and VINA− for one ADC and VINB+ and VINB− for the other ADC . The input signal, VIN, is defined as VIN A = (VINA+) – (VINA−) (3) for the "A" converter and VIN B = (VINB+) – (VINB−) (4) for the "B" converter. Figure 41 shows the expected input signal range. Note that the common mode input voltage, VCM, should be in the range of 1.0V to 2.0V. The peaks of the individual input signals should never exceed 2.6V. The ADC12DL080 performs best with a differential input signal with each input centered around a common mode voltage, VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180° out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. Figure 41. Expected Input Signal Range For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 4096 ( 1 - sin (90° + dev)) (5) Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see Figure 42). Drive the analog inputs with a source impedance less than 100Ω. Figure 42. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 21 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM. Single-Ended Operation Performance with differential input signals is better than with single-ended signals. For this reason, single-ended operation is not recommended. However, if single ended-operation is required and the resulting performance degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the driven input. The peak-to-peak input signal at the driven input pin should be twice the reference voltage to maximize SNR and SINAD performance (Figure 41b). For example, set VREF to 1.0V, bias VIN− to 1.5V and drive VIN+ with a signal range of 0.5V to 2.5V. Because very large input signal swings can degrade distortion performance, better performance with a singleended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and Table 2 indicate the input to output relationship of the ADC12DL080. Table 1. Input to Output Relationship – Differential Input VIN VIN− Binary Output 2’s Complement Output VCM − VREF/2 VCM + VREF/2 0000 0000 0000 1000 0000 0000 VCM − VREF/4 VCM + VREF/4 0100 0000 0000 1100 0000 0000 + VCM VCM 1000 0000 0000 0000 0000 0000 VCM + VREF/4 VCM − VREF/4 1100 0000 0000 0100 0000 0000 VCM + VREF/2 VCM − VREF/2 1111 1111 1111 0111 1111 1111 Table 2. Input to Output Relationship – Single-Ended Input VIN+ VIN− Binary Output 2’s Complement Output VCM − VREF VCM 0000 0000 0000 1000 0000 0000 VCM − VREF/2 VCM 0100 0000 0000 1100 0000 0000 VCM VCM 1000 0000 0000 0000 0000 0000 VCM + VREF/2 VCM 1100 0000 0000 0100 0000 0000 VCM + VREF VCM 1111 1111 1111 0111 1111 1111 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC12DL080 consist of an analog switch followed by a switched-capacitor amplifier. As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in voltage spikes at the signal input pins. As the driving source attempts to counteract these voltage spikes, it may add noise to the signal at the ADC analog input. To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in Figure 43 and Figure 44. These components should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response. The values of the RC shown in Figure 43 and Figure 44 are suitable for applications with input frequencies up to approximately 70MHz. Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 1.0V to 2.0V and be a value such that the peak excursions of the analog signal does not go more negative than ground or more positive than 2.6V. See Reference Pins. 22 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 DIGITAL INPUTS Digital TTL/CMOS compatible inputs consist of CLK, REFSEL/DCS, OF/DOEN, OEA/OF, OEB/DRDY. The OEB/DRDY pin may also be configured as the DRDY output. CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 10 MHz to 80 MHz. The higher the input frequency, the more critical it is to have a low jitter clock. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90°. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated with a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is (6) where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12DL080 has a Duty Cycle Stabilizer which can be enabled using the REFSEL/DCS pin. It is designed to maintain performance over a clock duty cycle range of 30% to 70% at 80 MSPS. REFSEL/DCS This pin is used in conjunction with VREF (pin 7) to select the reference source and turn the Duty Cycle Stabilizer (DCS) on or off. When REFSEL/DCS is LOW and VREF is HIGH, the internal 1.0V reference is selected and DCS is On. When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the VREF input. DCS is On. With this pin connected to VRMA or VRMB, DCS is Off. When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate a stable internal clock, improving the performance of the part. Table 3. VREF, REFSEL/DCS Pin Functions REFSEL/DCS (pin 11) VREF (pin 7) Reference DCS Logic LOW Logic HIGH Internal 1.0 V ON Logic High 0.8 to 1.2V External ON VRMA or VRMB Logic High Internal 1.0V OFF VRMA or VRMB 0.8 to 1.2V External OFF Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 23 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com OF/DOEN, OEA/OF, and OEB/DRDY OF/DOEN (pin 21) selects the output format (OF) or enables the DRDY output (DOEN). The state of this pin also controls the function of pins 22 (OEA/OF) and 41 (OEB/DRDY). When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41 is used as the DRDY output strobe, and pin 22 is used to select the output format. Output Enable for channels A and B are not available in this mode. When OF/DOEN is LOW, the output data format is offset binary. With OF/DOEN tied HIGH, the output format is 2's complement. The following table describes the function of these pins. Table 4. OF/DOEN, OEA/OF, OEB/DRDY Pin Functions Pin 21 State Pin 21 Function Pin 22 Function Pin 41 Function VRMA or VRMB DRDY output is enabled Output Format LOW = Offset Binary HIGH = 2's Complement DRDY Output Logic LOW Output Format = Offset Binary Logic HIGH Output Format = 2's Complement Output Enable for Channel A LOW = outputs are enabled HIGH = outputs are in high impedance state Output Enable for Channel B LOW = outputs are enabled HIGH = outputs are in high impedance state PD The PD pin, when high, holds the ADC12DL080 in a power-down mode to conserve power when the converter is not being used. The output data pins are undefined and the data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and 14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance. OUTPUTS The ADC12DL080 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at these outputs while the OE and PD pins are low. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers (74LVTH162374, for example) between the ADC outputs and any other circuitry. Only one driven input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 43. 24 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 +3.3V 3 x 0.1 PF + CHOKE 2 x 0.1 PF 2 x 0.1 PF D0 D1 D2 D3 D4 D5 D6 D7 + 7 4 0.1 PF 100 5 10 PF 6 30 51 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VREF VR B M VRP B VR B N 0.1 PF 0.1 PF 14 0.1 PF VIN_B 1 0.1 PF 0.1 PF 13 10 PF 12 22 T2 VR A M VRP A 2 1 2 22 39 pF * ChB Output Word D8 D9 D10 D11 D12 D13 D14 D15 12x100: N * 57 56 55 54 53 52 47 46 45 44 43 42 VR A ADC12DL080 0.1 PF 39 pF 0.1 PF R 1k VD R VD VA 9 VA 18 VA 19 VA 62 VA 63 VD 33 VD 48 2 x 10 PF Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 CLK OE VINB- 74LVTH162374 VINB+ ADT1-1WT 100 VIN_A 1 0.1 PF OEB/DRDY 41 1/4 74ACQ04 22 T2 39 pF 0.1 PF 2 * 22 16 15 39 pF * VINA- DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 VINA+ ADT1-1WT 22 59 OEA/OF 3 8 10 17 20 61 64 * This R-C network is suitable for input frequencies up to 70 MHz. For undersampling applications do not install these capacitors. Refer to Section 1.3.2 for more information. Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 ChA Output Word 12x100: PD AGND AGND AGND AGND AGND AGND AGND PD OF/DOEN REFSEL/DCS DR GND DR GND DR GND DR GND DR GND 11 CLK 23 31 40 50 58 Connect to VRMA DGND DGND 60 21 32 49 50 Crystal Oscillator D0 D1 D2 D3 D4 D5 D6 D7 39 38 37 36 35 34 29 28 27 26 25 24 D8 D9 D10 D11 D12 D13 D14 D15 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 CLK OE 74LVTH162374 Figure 43. Application Circuit using Transformer Drive Circuit 511, 1% VRM from ADC 22 255, 1% 50: SIGNAL INPUT 49.9, 1% 280, 1% To ADC VIN39 pF + VCM Amplifier: LMH6650 - 39 pF 511, 1% 22 To ADC VIN+ Figure 44. Optional Amplifier Drive for Circuit in Figure 43 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 25 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor near each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC12DL080 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.4V to VD. This can simplify interfacing to lower voltage devices and systems. Note, however, that tOD increases with reduced VDR. DO NOT operate the VDR pin at a voltage higher than VD. LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12DL080 between these areas, is required to achieve specified performance. The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12DL080's other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. 26 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 6 x 100: COMMON GROUND PLANE Clock line should be short and cross no other lines. OSC LATCH All Analog Components mounted over Analog area of Ground Plane All Digital Components mounted over Digital area of Ground Plane 14 15 16 DGND VDR DB6 DB7 DB9 DB8 DB11 DB10 PD DR GND CLK AGND DR GND OEB/DRDY ADC12DL080 VA DR GND AGND DA11 REFSEL/DCS DA10 VRN A DA9 VRP A DA8 VRM A DA7 VIN A+ DA6 AGND VA AGND Analog power line should be routed away from Digital power trace. VA VIN A- 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DGND 13 DB0 AGND DR GND 12 VREF VDR 11 DB1 DA5 10 DB2 VRN B DA4 9 VRP B DA3 8 DB3 DA2 7 DB4 VRM B DA1 Driving source located close to converter. Single Ground entry for all Reference Components AGND DA0 5 6 DB5 DR GND 4 VD VIN B+ OEA/OF 3 VIN B- OF/DOEN 2 VA AGND 1 VA 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Xfmr/Amplifier VD 48 6 x 100: 47 46 45 44 LATCH 43 42 41 40 39 38 37 36 35 34 33 Digital power line should be routed away from analog power trace. Ground entry points close to ground pins. Figure 45. Example of a Suitable Layout Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Figure 45 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be placed in the digital area of the board. The ADC12DL080 should be between these two areas. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single, quiet point. All ground connections should have a low inductance path to ground. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 27 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 46. The gates used in the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be prevented. Best performance will be obtained with a differential input drive, compared with a single-ended drive, as discussed in Single-Ended Operation and Driving the Analog Inputs. As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line. Figure 46. Isolating the ADC Clock from other Circuitry with a Clock Tree 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending digital input, close to the signal source, will eliminate the problem. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. Be careful not to overdrive the inputs of the ADC12DL080 with a device that is powered from supplies outside the range of the ADC12DL080 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance. The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12DL080, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω. 28 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 ADC12DL080 www.ti.com SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in Figure 44) will improve performance. Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, VREF should be in the range of 0.8V ≤ VREF ≤ 1.2V (7) Operating outside of these limits could lead to performance degradation. Inadequate network on Reference Bypass pins (VRPA, VRNA, VRMA, VRPB, VRNB and VRMB). As mentioned in Reference Pins, these pins should be bypassed with 0.1 µF capacitors to ground at VRMA and VRMB and with a 10 µF between pins VRPA and VRNA and between VRPB and VRNB for best performance. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 29 ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (April 2013) to Revision A • 30 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 29 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) ADC12DL080CIVS/NOPB ACTIVE TQFP PAG 64 160 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC12DL080 CIVS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of