ADC12DL3200ACF

Product Folder Order Now Support & Community Tools & Software Technical Documents ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 ADC12DL3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-Bit Analog-to-Digital Converter (ADC) With LVDS Interface 1 Features 3 Description • The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. • • • • • • • ADC Core: – 12-Bit Resolution – Up to 6.4 GSPS in Single-Channel Mode – Up to 3.2 GSPS in Dual-Channel Mode Internal Dither for Low-Magnitude, High-Order Harmonics Low-Latency LVDS Interface: – Total Latency: < 10 ns – Up to 48 Data Pairs at 1.6 Gbps – Four DDR Data Clocks – Strobe Signals Simplify Synchronization Noise Floor (No Input, VFS = 1.0 VPP-DIFF): – Dual-Channel Mode: –151.1 dBFS/Hz – Single-Channel Mode: –154.3 dBFS/Hz Buffered Analog Inputs With VCMI of 0 V: – Analog Input Bandwidth (–3 dB): 8.0 GHz – Usable Input Frequency Range: > 10 GHz – Full-Scale Input Voltage (VFS, Default): 0.8 VPP Noiseless Aperture Delay (TAD) Adjustment: – Precise Sampling Control: 19-fs Step – Simplifies Synchronization and Interleaving – Temperature and Voltage Invariant Delays Easy-to-Use Synchronization Features: – Automatic SYSREF Timing Calibration – Timestamp for Sample Marking Power Consumption: 3.15 W 2 Applications • • • • • • Oscilloscopes and Wideband Digitizers Electronic Warfare (SIGINT, ELINT) Time-of-Flight and LIDAR Distance Measurement Microwave Backhaul Automotive Radar Testers Spectrometry The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing. Device Information(1) PART NUMBER ADC12DL3200 PACKAGE BODY SIZE (NOM) FCBGA (256) 17.00 mm × 17.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. ADC12DL3200 Frequency Response 3 Normalized Gain Response (dB) 1 0 -3 -6 -9 Dual-Channel Mode Single-Channel Mode -12 0 2000 4000 6000 Input Frequency (MHz) 8000 10000 D_BW 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 4 Revision History Changes from Revision A (September 2018) to Revision B • Corrected mislabeled LVDS buses in Figure 7. LVDS buses B and C were swapped........................................................ 35 Changes from Original (May 2018) to Revision A • 2 Page Page Released to production .......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Table of Contents 1 2 3 4 5 6 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 4 Specifications....................................................... 12 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Absolute Maximum Ratings .................................... 12 ESD Ratings............................................................ 13 Recommended Operating Conditions..................... 13 Thermal Information ................................................ 14 Electrical Characteristics: DC Specifications .......... 14 Electrical Characteristics: Power Consumption ...... 17 Electrical Characteristics: AC Specifications (DualChannel Mode) ........................................................ 18 6.8 Electrical Characteristics: AC Specifications (SingleChannel Mode) ........................................................ 22 6.9 Timing Requirements .............................................. 25 6.10 Switching Characteristics ...................................... 25 6.11 Typical Characteristics .......................................... 37 7 Detailed Description ............................................ 49 7.1 Overview ................................................................. 49 7.2 Functional Block Diagram ....................................... 49 7.3 Feature Description................................................. 50 7.4 Device Functional Modes........................................ 60 7.5 Programming........................................................... 68 7.6 Register Maps ......................................................... 70 8 Application and Implementation ...................... 121 8.1 Application Information.......................................... 121 8.2 Typical Applications .............................................. 121 8.3 Initialization Set Up ............................................... 128 9 Power Supply Recommendations.................... 129 9.1 Power Sequencing ................................................ 131 10 Layout................................................................. 132 10.1 Layout Guidelines ............................................... 132 10.2 Layout Example .................................................. 132 11 Device and Documentation Support ............... 137 11.1 Device Support.................................................... 11.2 Documentation Support ...................................... 11.3 Receiving Notification of Documentation Updates.................................................................. 11.4 Support Resources ............................................. 11.5 Trademarks ......................................................... 11.6 Electrostatic Discharge Caution .......................... 11.7 Glossary .............................................................. 137 137 137 137 137 138 138 12 Mechanical, Packaging, and Orderable Information ......................................................... 138 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 3 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 5 Pin Configuration and Functions ACF Package 256-Ball Flip Chip BGA Top View A B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AGND AGND AGND INA+ INA± AGND AGND ORA1 DA0+ DA0± DA6+ DA6± DC0+ DC0± AGND AGND AGND AGND AGND ORA0 DA1+ DA1± DA7+ DA7± DC1+ DC1± DC7+ DC7± CALSTAT CALTRIG 15 DGND 16 DGND C AGND AGND AGND AGND AGND AGND AGND ORB1 DA2+ DA2± DA8+ DA8± DC2+ DC2± DC8+ DC8± D TMSTP+ BG AGND AGND AGND AGND DGND ORB0 DA3+ DA3± DA9+ DA9± DC3+ DC3± DC9+ DC9± E TMSTP± SYNCSE AGND VA11 VA11 VA11 DGND VD11 DA4+ DA4± DA10+ DA10± DC4+ DC4± DC10+ DC10± DA5+ DA5± DA11+ DA11± DC5+ DC5± DC11+ DC11± DC6± DCCLK+ DCCLK± F AGND AGND VA11 VA11 VA11 VA11 DGND VD11 G AGND AGND VA19 VA19 VA19 VA19 DGND VD11 DACLK+ DACLK± VLVDS VLVDS DC6+ H CLK+ AGND VA19 VA19 VA19 VA19 DGND DGND DASTR+ DASTR± VLVDS VLVDS VLVDS DGND DCSTR+ DCSTR± J CLK± AGND VA19 VA19 VA19 VA19 DGND DGND DBSTR+ DBSTR± VLVDS VLVDS VLVDS DGND DDSTR+ DDSTR± K AGND AGND VA19 VA19 VA19 VA19 DGND VD11 DBCLK+ DBCLK± VLVDS VLVDS DD6+ DD6± DDCLK+ DDCLK± L AGND AGND VA11 VA11 VA11 VA11 DGND VD11 DB5+ DB5± DB11+ DB11± DD5+ DD5± DD11+ DD11± M SYSREF+ TDIODE+ AGND VA11 VA11 VA11 DGND VD11 DB4+ DB4± DB10+ DB10± DD4+ DD4± DD10+ DD10± N SYSREF± TDIODE± AGND AGND AGND AGND DGND SDO DB3+ DB3± DB9+ DB9± DD3+ DD3± DD9+ DD9± P AGND AGND AGND AGND AGND AGND AGND SDI DB2+ DB2± DB8+ DB8± DD2+ DD2± DD8+ DD8± R PD AGND AGND AGND AGND AGND AGND SCS DB1+ DB1± DB7+ DB7± DD1+ DD1± DD7+ DD7± T AGND AGND AGND INB+ INB± AGND AGND SCLK DB0+ DB0± DB6+ DB6± DD0+ DD0± DGND DGND Not to scale 4 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Pin Functions PIN NO. NAME I/O DESCRIPTION A1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. A2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. A3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. A4 INA+ I Channel A analog input positive connection. The differential full-scale input range is determined by the FS_RANGE_A register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to AGND through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. A5 INA– I Channel A analog input negative connection. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used. A6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. A7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. A8 ORA1 O Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. A9 DA0+ O LVDS output for bit 0 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. A10 DA0– O LVDS output for bit 0 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. A11 DA6+ O LVDS output for bit 6 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. A12 DA6– O LVDS output for bit 6 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. A13 DC0+ O LVDS output for bit 0 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. A14 DC0– O LVDS output for bit 0 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. A15 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. A16 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. B1 CALSTAT O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used. B2 CALTRIG I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used. B3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. B4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. B5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. B6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. B7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. B8 ORA0 O Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. B9 DA1+ O LVDS output for bit 1 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. B10 DA1– O LVDS output for bit 1 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. B11 DA7+ O LVDS output for bit 7 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. B12 DA7– O LVDS output for bit 7 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. B13 DC1+ O LVDS output for bit 1 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. B14 DC1– O LVDS output for bit 1 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. B15 DC7+ O LVDS output for bit 7 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. B16 DC7– O LVDS output for bit 7 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. C1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. C2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. C3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. C4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. C5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 5 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION C6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. C7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. C8 ORB1 O Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. C9 DA2+ O LVDS output for bit 2 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. C10 DA2– O LVDS output for bit 2 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. C11 DA8+ O LVDS output for bit 8 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. C12 DA8– O LVDS output for bit 8 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. C13 DC2+ O LVDS output for bit 2 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. C14 DC2– O LVDS output for bit 2 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. C15 DC8+ O LVDS output for bit 8 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. C16 DC8– O LVDS output for bit 8 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. D1 TMSTP+ I Timestamp input positive connection or differential LVDS SYNC positive connection. This input is used as the timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set 1. This differential input is used as the SYNC signal input when SYNC_SEL is set to 1. This input can be used as both a timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling when used as the LVDS SYNC signal. For additional usage information, see the Timestamp section. TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC-coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC-coupled and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC-coupled and DC-coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required. D2 BG O Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. See the Analog Reference Voltage section for more details. This pin can be left disconnected if not used. D3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. D4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. D5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. D6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. D7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. D8 ORB0 O Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used. D9 DA3+ O LVDS output for bit 3 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. D10 DA3– O LVDS output for bit 3 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. D11 DA9+ O LVDS output for bit 9 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. D12 DA9– O LVDS output for bit 9 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. D13 DC3+ O LVDS output for bit 3 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. D14 DC3– O LVDS output for bit 3 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. D15 DC9+ O LVDS output for bit 9 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. D16 DC9– O LVDS output for bit 9 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. TMSTP– I Timestamp input negative connection or differential LVDS SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required. E1 6 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION LVDS interface SYNC signal, single-ended active low input used to control sending strobe signals for synchronization or digital interface test patterns. The Digital Interface Test Patterns section describes using the SYNC signal in more detail. The choice of single-ended or differential SYNC (using the TMSTP+ and TMSTP– pins) is selected by programming SYNC_SEL. Tie this pin to ground if differential SYNC (TMSTP±) is used as the SYNC signal. E2 SYNCSE I E3 AGND — E4 VA11 I 1.1-V analog supply E5 VA11 I 1.1-V analog supply E6 VA11 I 1.1-V analog supply E7 DGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. E8 VD11 I 1.1-V digital supply E9 DA4+ O LVDS output for bit 4 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. E10 DA4– O LVDS output for bit 4 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. E11 DA10+ O LVDS output for bit 10 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. E12 DA10– O LVDS output for bit 10 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. E13 DC4+ O LVDS output for bit 4 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. E14 DC4– O LVDS output for bit 4 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. E15 DC10+ O LVDS output for bit 10 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. E16 DC10– O LVDS output for bit 10 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. F1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. F2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. F3 VA11 I 1.1-V analog supply F4 VA11 I 1.1-V analog supply F5 VA11 I 1.1-V analog supply 1.1-V analog supply F6 VA11 I F7 DGND — F8 VD11 I 1.1-V digital supply F9 DA5+ O LVDS output for bit 5 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. F10 DA5– O LVDS output for bit 5 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. F11 DA11+ O LVDS output for bit 11 of LVDS bus A. Positive connection. This pin can be left disconnected if not used. F12 DA11– O LVDS output for bit 11 of LVDS bus A. Negative connection. This pin can be left disconnected if not used. F13 DC5+ O LVDS output for bit 5 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. F14 DC5– O LVDS output for bit 5 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. F15 DC11+ O LVDS output for bit 11 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. F16 DC11– O LVDS output for bit 11 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. G1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. G2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. G3 VA19 I 1.9-V analog supply G4 VA19 I 1.9-V analog supply G5 VA19 I 1.9-V analog supply 1.9-V analog supply G6 VA19 I G7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 7 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION G8 VD11 I 1.1-V digital supply G9 DACLK+ O LVDS output for data clock of LVDS bus A. Positive connection. This pin can be left disconnected if not used. G10 DACLK– O LVDS output for data clock of LVDS bus A. Negative connection. This pin can be left disconnected if not used. G11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply G12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply G13 DC6+ O LVDS output for bit 6 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. G14 DC6– O LVDS output for bit 6 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. G15 DCCLK+ O LVDS output for data clock of LVDS bus C. Positive connection. This pin can be left disconnected if not used. G16 DCCLK– O LVDS output for data clock of LVDS bus C. Negative connection. This pin can be left disconnected if not used. Device (sampling) clock positive input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both rising and falling edges. In-dual channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0. H1 CLK+ I H2 AGND — H3 VA19 I 1.9-V analog supply H4 VA19 I 1.9-V analog supply H5 VA19 I 1.9-V analog supply H6 VA19 I 1.9-V analog supply H7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H8 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H9 DASTR+ O LVDS output for data strobe of LVDS bus A. Positive connection. This pin can be left disconnected if not used. H10 DASTR– O LVDS output for data strobe of LVDS bus A. Negative connection. This pin can be left disconnected if not used. H11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply H12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply H13 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply H14 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H15 DCSTR+ O LVDS output for data strobe of LVDS bus C. Positive connection. This pin can be left disconnected if not used. H16 DCSTR– O LVDS output for data strobe of LVDS bus C. Negative connection. This pin can be left disconnected if not used. J1 CLK– I Device (sampling) clock negative input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. J2 AGND — J3 VA19 I 1.9-V analog supply J4 VA19 I 1.9-V analog supply J5 VA19 I 1.9-V analog supply J6 VA19 I 1.9-V analog supply J7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. J8 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. J9 DBSTR+ O LVDS output for data strobe of LVDS bus B. Positive connection. This pin can be left disconnected if not used. J10 DBSTR– O LVDS output for data strobe of LVDS bus B. Negative connection. This pin can be left disconnected if not used. J11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply 8 Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION J12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply J13 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply J14 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. J15 DDSTR+ O LVDS output for data strobe of LVDS bus D. Positive connection. This pin can be left disconnected if not used. J16 DDSTR– O LVDS output for data strobe of LVDS bus D. Negative connection. This pin can be left disconnected if not used. K1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. K2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. K3 VA19 I 1.9-V analog supply K4 VA19 I 1.9-V analog supply K5 VA19 I 1.9-V analog supply K6 VA19 I 1.9-V analog supply K7 DGND — K8 VD11 I 1.1-V digital supply K9 DBCLK+ O LVDS output for data clock of LVDS bus B. Positive connection. This pin can be left disconnected if not used. K10 DBCLK– O LVDS output for data clock of LVDS bus B. Negative connection. This pin can be left disconnected if not used. K11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply K12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply K13 DD6+ O LVDS output for bit 6 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. K14 DD6– O LVDS output for bit 6 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. K15 DDCLK+ O LVDS output for data clock of LVDS bus D. Positive connection. This pin can be left disconnected if not used. K16 DDCLK– O LVDS output for data clock of LVDS bus D. Negative connection. This pin can be left disconnected if not used. L1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. L2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. L3 VA11 I 1.1-V analog supply L4 VA11 I 1.1-V analog supply L5 VA11 I 1.1-V analog supply L6 VA11 I 1.1-V analog supply L7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. L8 VD11 I 1.1-V digital supply L9 DB5+ O LVDS output for bit 5 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. L10 DB5– O LVDS output for bit 5 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. L11 DB11+ O LVDS output for bit 11 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. L12 DB11– O LVDS output for bit 11 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. L13 DD5+ O LVDS output for bit 5 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. L14 DD5– O LVDS output for bit 5 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. L15 DD11+ O LVDS output for bit 11 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. L16 DD11– O LVDS output for bit 11 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 9 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION M1 SYSREF+ I SYSREF input positive connection. The SYSREF input is used to achieve synchronization between multiple ADC12DL3200 devices and deterministic latency across the LVDS data interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSERF_LVPECL_EN is set to 1. This input is not self-biased when SYSERF_LVPECL is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table. M2 TDIODE+ I Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used. M3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. M4 VA11 I 1.1-V analog supply M5 VA11 I 1.1-V analog supply 1.1-V analog supply M6 VA11 I M7 DGND — M8 VD11 I 1.1-V digital supply M9 DB4+ O LVDS output for bit 4 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. M10 DB4– O LVDS output for bit 4 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. M11 DB10+ O LVDS output for bit 10 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. M12 DB10– O LVDS output for bit 10 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. M13 DD4+ O LVDS output for bit 4 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. M14 DD4– O LVDS output for bit 4 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. M15 DD10+ O LVDS output for bit 10 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. M16 DD10– O LVDS output for bit 10 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. N1 SYSREF– I SYSREF input negative connection. See SYSREF+ (pin M1) for detailed description. N2 TDIODE– I Temperature diode negative (cathode) connection. This pin can be left disconnected if not used. N3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. N4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. N5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. N6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. N7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. N8 SDO O Serial programming interface (SPI) data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used. N9 DB3+ O LVDS output for bit 3 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. N10 DB3– O LVDS output for bit 3 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. N11 DB9+ O LVDS output for bit 9 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. N12 DB9– O LVDS output for bit 9 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. N13 DD3+ O LVDS output for bit 3 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. N14 DD3– O LVDS output for bit 3 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. N15 DD9+ O LVDS output for bit 9 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. N16 DD9– O LVDS output for bit 9 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. P1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. P2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. P3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. 10 Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION P4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. P5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. P6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. P7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. P8 SDI I Serial programming interface (SPI) data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. P9 DB2+ O LVDS output for bit 2 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. P10 DB2– O LVDS output for bit 2 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. P11 DB8+ O LVDS output for bit 8 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. P12 DB8– O LVDS output for bit 8 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. P13 DD2+ O LVDS output for bit 2 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. P14 DD2– O LVDS output for bit 2 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. P15 DD8+ O LVDS output for bit 8 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. P16 DD8– O LVDS output for bit 8 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. R1 PD I This pin disables all analog circuits and LVDS outputs when set high to save power or for temperature diode calibration. Tie this pin to ground during normal operation. R2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. R3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. R4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. R5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. R6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. R7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. R8 SCS I Serial programming interface (SPI) chip-select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has an 82kΩ pullup resistor to VD11. R9 DB1+ O LVDS output for bit 1 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. R10 DB1– O LVDS output for bit 1 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. R11 DB7+ O LVDS output for bit 7 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. R12 DB7– O LVDS output for bit 7 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. R13 DD1+ O LVDS output for bit 1 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. R14 DD1– O LVDS output for bit 1 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. R15 DD7+ O LVDS output for bit 7 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. R16 DD7– O LVDS output for bit 7 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. T1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. T2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. T3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. T4 INB+ I Channel B analog input positive connection. The differential full-scale input range is determined by the FS_RANGE_B register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to AGND through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. T5 INB– I Channel B analog input negative connection. See INB+ (pin T4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used. T6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. T7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. T8 SCLK I Serial programming interface (SPI) clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. T9 DB0+ O LVDS output for bit 0 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. T10 DB0– O LVDS output for bit 0 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 11 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION T11 DB6+ O LVDS output for bit 6 of LVDS bus B. Positive connection. This pin can be left disconnected if not used. T12 DB6– O LVDS output for bit 6 of LVDS bus B. Negative connection. This pin can be left disconnected if not used. T13 DD0+ O LVDS output for bit 0 of LVDS bus D. Positive connection. This pin can be left disconnected if not used. T14 DD0– O LVDS output for bit 0 of LVDS bus D. Negative connection. This pin can be left disconnected if not used. T15 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. T16 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range MIN MAX VA19 (2) –0.3 2.35 VA11 (2) –0.3 1.32 (3) –0.3 1.32 –0.3 2.35 –1.32 1.32 VD11 VLVDS (3) Voltage between VD11 and VA11 Voltage between AGND and DGND UNIT V –0.1 0.1 DACLK+, DACLK–, DASTR+, DASTR–, DA[11:0]+, DA[11:0]–, DBCLK+, DBCLK–, DBSTR+, DBSTR–, DB[11:0]+, DB[11:0]–, DCCLK+, DCCLK–, DCSTR+, DCSTR–, DC[11:0]+, DC[11:0]–, DDCLK+, DDCLK–, DDSTR+, DDSTR–, DD[11:0]+, DD[11:0]– (3) –0.5 VLVDS + 0.5 (4) CLK+, CLK–, SYSREF+, SYSREF– (2) –0.5 VA11 + 0.5 (5) TMSTP+, TMSTP– (3) –0.5 VD11 + 0.5 (6) BG, TDIODE+, TDIODE– (2) –0.5 VA19 + 0.5 (7) –1 1 –0.5 VA19 + 0.5 (7) Peak input current (any input except INA+, INA–, INB+, INB–) –25 25 mA Peak input current (INA+, INA–, INB+, INB–) –50 50 mA 16.4 dBm 100 mA 150 °C 150 °C Pin voltage range INA+, INA–, INB+, INB– (2) CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE (2) Peak RF input power (INA+, INA–, INB+, INB–) Single-ended with ZS-SE = 50 Ω or differential with ZS-DIFF = 100 Ω Peak total input current (sum of absolute value of all currents forced in or out, not including power supply current) Operating junction temperature, Tj Storage temperature, Tstg (1) (2) (3) (4) (5) (6) (7) 12 –65 V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured to AGND. Measured to DGND. Maximum voltage not to exceed VLVDS absolute maximum rating. Maximum voltage not to exceed VA11 absolute maximum rating. Maximum voltage not to exceed VD11 absolute maximum rating. Maximum voltage not to exceed VA19 absolute maximum rating. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM (1) 1.8 1.9 2.0 VA11, analog 1.1-V supply (1) 1.05 1.1 1.15 VD11, digital 1.1-V supply (2) 1.05 1.1 1.15 VLVDS, LVDS interface supply (2) 1.05 1.9 2.0 -50 0 110 0 0.3 0.55 0 0.3 0.55 0.4 1.0 2.0 VA19, analog 1.9-V supply VDD Supply voltage range INA+, INA–, INB+, INB– (1) VCMI Input common-mode voltage CLK+, CLK–, SYSREF+, SYSREF– (1) (3) TMSTP+, TMSTP– (2) Input voltage, peak-to-peak differential VID (4) CLK+ to CLK–, SYSREF+ to SYSREF–, TMSTP+ to TMSTP– High-level input voltage CALTRIG, PD, SCLK, SCS, SDI, SYNCSE (1) VIL Low-level input voltage CALTRIG, PD, SCLK, SCS, SDI, SYNCSE (1) IC_TD Temperature diode input current TDIODE+ to TDIODE– CL BG maximum load capacitance IO BG maximum output current DC Input clock duty cycle TA Operating free-air temperature Tj (1) (2) (3) (4) (5) (6) V mV V VPP-DIFF 0.7 V 0.45 100 30% -40 Operating junction temperature UNIT 1.0 (5) INA+ to INA–, INB+ to INB– VIH MAX 50% V µA 100 pF 100 µA 70% 85 ºC (6) ºC 105 Measured to AGND. Measured to DGND. It is strongly recommended that CLK± be AC coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self bias to the optimal input common mode voltage for best performance. TI recommends AC coupling for SYSREF± unless DC coupling is required, in which case LVPECL input mode must be used (SYSREF_LVPECL_EN = 1). TMSTP± does not have internal biasing which requires TMSTP± to be biased externally whether AC coupled with TMSTP_LVPECL_EN = 0 or DC coupled with TMSTP_LVPECL_EN = 1. ADC output code will saturate when VID for INA+/– or INB+/– exceeds the programmed full-scale voltage (VFS) set by FS_RANGE_A for INA± or FS_RANGE_B for INB±. Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 13 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 6.4 Thermal Information ADC12DL3200 THERMAL METRIC (1) ACF (FCBGA) UNIT 256 PINS RθJA Junction-to-ambient thermal resistance 16.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.94 °C/W RθJB Junction-to-board thermal resistance 5.4 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 5.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics: DC Specifications typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC ACCURACY Resolution DNL Differential nonlinearity INL Integral nonlinearity Resolution with no missing codes 12 Maximum positive excursion from ideal step size 0.3 Maximum negative excursion from ideal step size –0.3 Bits LSB Maximum positive excursion from ideal transfer function 1.6 Maximum negative excursion from ideal transfer function –2.0 CAL_OS = 0 ±2.0 mV CAL_OS = 1 ±0.3 mV Available offset correction range (see CAL_OS bit in the CAL_CFGO register or the OADJ_A_FG0_VINA register) ±55 mV Foreground calibration at nominal temperature only 14 LSB ANALOG INPUTS (INA±, INB±) VOFF Offset Error VOFF_ADJ Input offset voltage adjustment range VOFF_ Offset drift DRIFT Foreground calibration at each temperature Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) Analog differential input fullscale range VIN_FSR Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) 750 800 1000 1040 Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) VIN_FSR_ DRIFT VIN_FSR_ MATCH Analog differential input fullscale range drift Analog differential input fullscale range matching 0.037 Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift 0.006 Matching between INA± and INB±, default setting, dual channel mode 0.53% Single-ended input resistance Each input terminal is terminated to AGND, to AGND measured at TA = 25°C RIN_ Input termination linear temperature coefficient TEMPCO 14 480 Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift RIN 850 mVPP 525 %/°C 48 50 13.7 Submit Documentation Feedback µV/°C 4 52 Ω mΩ/°C Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Electrical Characteristics: DC Specifications (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER CIN Single-ended input capacitance TEST CONDITIONS MIN TYP Single-channel mode measured at DC 0.45 Dual-channel mode measured at DC 0.45 MAX UNIT pF TEMPERATURE DIODE CHARACTERISTICS (TDIODE±) ΔVBE Temperature diode voltage slope Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Perform offset measurements with the device unpowered or with the PD pin asserted to minimize device self-heating. -1.33 mV/°C BANDGAP VOLTAGE OUTPUT (BG) VBG Reference output voltage IL ≤ 100 µA 1.1 V VBG_ Reference output temperature drift IL ≤ 100 µA –85 µV/°C DRIFT CLOCK INPUTS (CLK±, SYSREF±, TMSTP±) ZT VCM Internal termination Input common-mode voltage, self-biased Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 100 Ω Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 50 Self-biasing common-mode voltage for CLK± when AC coupled (DEVCLK_LVPECL_EN must be set to 0) 0.3 Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1). 0.3 Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0). VA11 V CL_DIFF Differential input capacitance Between positive and negative differential input pins 0.1 pF CL_SE Single-ended input capacitance Each input to ground 0.5 pF LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±) VDIFF Differential output peak-topeak voltage, DC measurement Default swing (HSM), 100-Ω load 400 720 Low swing (LSM), 100-Ω load 350 Low swing high-Z mode (HZM), high-impedance load 380 VLVDS = 1.9 V 1.3 VLVDS = 1.1 V 0.5 900 mVPPDIFF VCM Output common-mode voltage, tracks with VLVDS IOS_DIFF Differential short-circuit current IOS_GND Short-circuit current to ground Either positive or negative output tied to ground ZDIFF Differential output impedance Positive and negative outputs shorted together Measured at DC 5 mA 20 mA 300 Ω Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 V 15 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Electrical Characteristics: DC Specifications (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE IIH High-level input current IIL Low-level input current CI Input capacitance VOH High-level output voltage ILOAD = –400 µA VOL Low-level output voltage ILOAD = 400 µA 16 40 –40 µA 2 Submit Documentation Feedback µA pF 1.65 V 150 mV Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 6.6 Electrical Characteristics: Power Consumption typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVA19 1.9-V analog supply current 846 mA IVA11 1.1-V analog supply current 508 mA IVD11 1.1-V digital supply current 229 mA IVLVDS LVDS interface supply current 382 mA PDIS Power dissipation 3.15 W IVA19 1.9-V analog supply current 1116 mA IVA11 1.1-V analog supply current 611 mA IVD11 1.1-V digital supply current 271 mA IVLVDS LVDS interface supply current 385 mA PDIS Power dissipation 3.82 W IVA19 1.9-V analog supply current 1195 1300 mA IVA11 1.1-V analog supply current 612 700 mA IVD11 1.1-V digital supply current 266 350 mA IVLVDS LVDS interface supply current 386 450 mA PDIS Power dissipation 3.97 4.5 IVA19 1.9-V analog supply current 1195 mA IVA11 1.1-V analog supply current 612 mA IVD11 1.1-V digital supply current 266 mA IVLVDS LVDS interface supply current 327 mA PDIS Power dissipation 3.60 W IVA19 1.9-V analog supply current 35 mA IVA11 1.1-V analog supply current 23 mA IVD11 1.1-V digital supply current 4 mA IVLVDS LVDS interface supply current 0 mA PDIS Power dissipation 0.1 W Power mode 1: single-channel mode, demux-by-2, foreground calibration, VLVDS = 1.9 V Power mode 2: single-channel mode, demux-by-2, background calibration, VLVDS = 1.9 V Power mode 3: dual-channel mode, demux-by-2, background calibration, VLVDS = 1.9 V Power mode 4: dual-channel mode, demux-by-2, background calibration, VLVDS = 1.1 V Power mode 5: PD pin held high, no clock, VLVDS = 1.9 V Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 W 17 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER FPBW Full-power input bandwidth (–3 dB) (1) XTALK Channel-to-channel crosstalk CER Code error rate Noise spectral density, no input signal NSD NF Noise figure NOISEDC DC input noise standard deviation TEST CONDITIONS MIN Foreground calibration 8.0 Background calibration 8.0 Aggressor = 400 MHz, –1 dBFS –91 Aggressor = 3000 MHz, –1 dBFS –59 Aggressor = 6000 MHz, –1 dBFS –59 10-18 Maximum CER Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, foreground calibration –151.1 Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, foreground calibration –149.8 Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, foreground calibration, no input, ZS = 100 Ω 21.9 Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, foreground calibration, no input, ZS = 100 Ω 23.2 No input, foreground calibration, excludes DC offset, includes fixed interleaving spur (FS/2 spur) 2.9 SNR SNR (1) 18 Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs UNIT GHz dB errors/ sample dB fIN = 347 MHz, AIN = –1 dBFS 57.1 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 57.8 fIN = 2482 MHz, AIN = –1 dBFS MAX dBFS/Hz fIN = 997 MHz, AIN = –1 dBFS Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs TYP LSB 56.9 52 55.6 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 56.3 fIN = 4997 MHz, AIN = –1 dBFS 52.8 fIN = 6397 MHz, AIN = –1 dBFS 51.2 fIN = 8197 MHz, AIN = –1 dBFS 49.7 fIN = 347 MHz, AIN = –16 dBFS 57.7 fIN = 997 MHz, AIN = –16 dBFS 57.7 fIN = 2482 MHz, AIN = –16 dBFS 57.7 fIN = 4997 MHz, AIN = –16 dBFS 57.4 fIN = 6397 MHz, AIN = –16 dBFS 57.1 fIN = 8197 MHz, AIN = –16 dBFS 57.0 dBFS dBFS Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN fIN = 347 MHz, AIN = –1 dBFS SINAD fIN = 2482 MHz, AIN = –1 dBFS 50.0 fIN = 6397 MHz, AIN = –1 dBFS 47.9 fIN = 8197 MHz, AIN = –1 dBFS 46.5 8.9 8.0 SFDR SFDR FS/2 Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs FS/2 fixed interleaving spur, independent of input signal 8.6 fIN = 4997 MHz, AIN = –1 dBFS 8.0 fIN = 6397 MHz, AIN = –1 dBFS 7.7 fIN = 8197 MHz, AIN = –1 dBFS 7.4 fIN = 347 MHz, AIN = –1 dBFS 70 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 69 fIN = 997 MHz, AIN = –1 dBFS Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs fIN = 2482 MHz, AIN = –1 dBFS bits 66 56 64 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 61 fIN = 4997 MHz, AIN = –1 dBFS 57 fIN = 6397 MHz, AIN = –1 dBFS 56 fIN = 8197 MHz, AIN = –1 dBFS 53 fIN = 347 MHz, AIN = –16 dBFS 78 fIN = 997 MHz, AIN = –16 dBFS 77 fIN = 2482 MHz, AIN = –16 dBFS 75 fIN = 4997 MHz, AIN = –16 dBFS 75 fIN = 6397 MHz, AIN = –16 dBFS 78 fIN = 8197 MHz, AIN = –16 dBFS 78 No input dBFS 9.0 fIN = 997 MHz, AIN = –1 dBFS ENOB 53.7 fIN = 4997 MHz, AIN = –1 dBFS fIN = 2482 MHz, AIN = –1 dBFS UNIT 55.1 50 fIN = 347 MHz, AIN = –1 dBFS Effective number of bits, large signal, excluding DC and FS/2 fixed spurs MAX 56.2 fIN = 997 MHz, AIN = –1 dBFS Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs TYP –76 dBFS dBFS –55 dBFS Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 19 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER 2nd-order harmonic HD2 3rd-order harmonic HD3 FS/2-FIN SPUR 20 FS/2-FIN interleaving spur, signal dependent Worst harmonic 4th-order or higher TEST CONDITIONS MIN TYP fIN = 347 MHz, AIN = –1 dBFS –72 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –73 fIN = 997 MHz, AIN = –1 dBFS –68 fIN = 2482 MHz, AIN = –1 dBFS –65 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –63 fIN = 4997 MHz, AIN = –1 dBFS –65 fIN = 6397 MHz, AIN = –1 dBFS –59 fIN = 8197 MHz, AIN = –1 dBFS –65 fIN = 347 MHz, AIN = –1 dBFS –74 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –71 fIN = 997 MHz, AIN = –1 dBFS –69 fIN = 2482 MHz, AIN = –1 dBFS –65 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –61 fIN = 4997 MHz, AIN = –1 dBFS –57 fIN = 6397 MHz, AIN = –1 dBFS –56 fIN = 8197 MHz, AIN = –1 dBFS –53 fIN = 347 MHz, AIN = –1 dBFS –73 fIN = 997 MHz, AIN = –1 dBFS –73 fIN = 2482 MHz, AIN = –1 dBFS –74 fIN = 4997 MHz, AIN = –1 dBFS –73 fIN = 6397 MHz, AIN = –1 dBFS –72 fIN = 8197 MHz, AIN = –1 dBFS –66 fIN = 347 MHz, AIN = –1 dBFS –74 fIN = 997 MHz, AIN = –1 dBFS –72 fIN = 2482 MHz, AIN = –1 dBFS –74 fIN = 4997 MHz, AIN = –1 dBFS –73 fIN = 6397 MHz, AIN = –1 dBFS –72 fIN = 8197 MHz, AIN = –1 dBFS –70 Submit Documentation Feedback MAX –56 –56 –56 –60 UNIT dBFS dBFS dBFS dBFS Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER IMD3 3rd-order intermodulation TEST CONDITIONS MIN TYP fIN = 347 MHz ± 5 MHz, AIN = –7 dBFS per tone –81 fIN = 997 MHz ± 5 MHz, AIN = –7 dBFS per tone –87 fIN = 2482 MHz ± 5 MHz, AIN = –7 dBFS per tone –72 fIN = 4997 MHz ± 5 MHz, AIN = –7 dBFS per tone –61 fIN = 6397 MHz ± 5 MHz, AIN = –7 dBFS per tone –53 fIN = 8197 MHz ± 5 MHz, AIN = –7 dBFS per tone –45 MAX UNIT dBFS Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 21 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN TYP FPBW Full-power input bandwidth (–3 dB) (1) Foreground calibration 7.5 Background calibration 7.5 CER Code error rate Maximum CER Noise spectral density, no input signal, excludes fixed interleaving spurs (FS/2 and FS/4 spurs) NSD NF Noise figure NOISEDC DC input noise standard deviation 10–18 Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration –154.3 Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration –152.5 Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration, no input, ZS = 100 Ω 18.7 Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration, no input, ZS = 100 Ω 20.5 SNR SNR Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs 3.1 fIN = 347 MHz, AIN = –1 dBFS 57.0 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 57.9 SINAD (1) 22 55.8 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 56.5 fIN = 4997 MHz, AIN = –1 dBFS 53.2 fIN = 6397 MHz, AIN = –1 dBFS 51.4 fIN = 8197 MHz, AIN = –1 dBFS 50.1 fIN = 347 MHz, AIN = –16 dBFS 57.8 fIN = 997 MHz, AIN = –16 dBFS 57.7 fIN = 2482 MHz, AIN = –16 dBFS 57.8 fIN = 4997 MHz, AIN = –16 dBFS 57.5 fIN = 6397 MHz, AIN = –16 dBFS 57.1 fIN = 8197 MHz, AIN = –16 dBFS 57.1 fIN = 347 MHz, AIN = –1 dBFS 55.9 fIN = 2482 MHz, AIN = –1 dBFS errors/ sample LSB 56.8 52 fIN = 997 MHz, AIN = –1 dBFS Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs GHz dB No input, foreground calibration, excludes DC offset, includes fixed interleaving spurs (FS/2 and FS/4 spurs) fIN = 2482 MHz, AIN = –1 dBFS UNIT dBFS/Hz fIN = 997 MHz, AIN = –1 dBFS Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs MAX dBFS dBFS 54.0 48 53.3 fIN = 4997 MHz, AIN = –1 dBFS 50.5 fIN = 6397 MHz, AIN = –1 dBFS 48.5 fIN = 8197 MHz, AIN = –1 dBFS 44.0 dBFS Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN fIN = 347 MHz, AIN = –1 dBFS ENOB fIN = 2482 MHz, AIN = –1 dBFS SFDR SFDR Spurious-free dynamic range, small signal, excluding DC, FS/4 and FS/2 fixed spurs 8.6 fIN = 4997 MHz, AIN = –1 dBFS 8.1 fIN = 6397 MHz, AIN = –1 dBFS 7.8 fIN = 8197 MHz, AIN = –1 dBFS 7.0 fIN = 347 MHz, AIN = –1 dBFS 67 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 66 fIN = 2482 MHz, AIN = –1 dBFS 61 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 58 fIN = 4997 MHz, AIN = –1 dBFS 58 fIN = 6397 MHz, AIN = –1 dBFS 56 fIN = 8197 MHz, AIN = –1 dBFS 47 fIN = 347 MHz, AIN = –16 dBFS 78 fIN = 997 MHz, AIN = –16 dBFS 76 fIN = 2482 MHz, AIN = –16 dBFS 73 fIN = 4997 MHz, AIN = –16 dBFS 76 fIN = 6397 MHz, AIN = –16 dBFS 70 fIN = 8197 MHz, AIN = –16 dBFS 62 FS/2 fixed interleaving spur, independent of input signal No input –62 FS/4 FS/4 fixed interleaving spur, independent of input signal No input –69 fIN = 347 MHz, AIN = –1 dBFS –75 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –73 fIN = 997 MHz, AIN = –1 dBFS –68 fIN = 2482 MHz, AIN = –1 dBFS –66 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –64 fIN = 4997 MHz, AIN = –1 dBFS –69 fIN = 6397 MHz, AIN = –1 dBFS –64 fIN = 8197 MHz, AIN = –1 dBFS –68 2nd-order harmonic Bits 62 50 FS/2 HD2 UNIT 8.7 7.7 fIN = 997 MHz, AIN = –1 dBFS Spurious-free dynamic range, large signal, excluding DC, FS/4 and FS/2 fixed spurs MAX 9.0 fIN = 997 MHz, AIN = –1 dBFS Effective number of bits, large signal, excluding DC and FS/2 fixed spurs TYP dBFS dBFS dBFS –55 –56 dBFS dBFS Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 23 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER 3rd-order harmonic HD3 FS/2-FIN FS/4±FIN SPUR IMD3 24 FS/2-FIN interleaving spur, signal dependent FS/4±FIN interleaving spurs, signal dependent Worst harmonic 4th-order or higher rd 3 -order intermodulation TEST CONDITIONS MIN TYP fIN = 347 MHz, AIN = –1 dBFS –74 fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –72 fIN = 997 MHz, AIN = –1 dBFS –66 fIN = 2482 MHz, AIN = –1 dBFS –66 fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –61 fIN = 4997 MHz, AIN = –1 dBFS –59 fIN = 6397 MHz, AIN = –1 dBFS –59 fIN = 8197 MHz, AIN = –1 dBFS –56 fIN = 347 MHz, AIN = –1 dBFS –68 fIN = 997 MHz, AIN = –1 dBFS –63 fIN = 2482 MHz, AIN = –1 dBFS –62 fIN = 4997 MHz, AIN = –1 dBFS –62 fIN = 6397 MHz, AIN = –1 dBFS –56 fIN = 8197 MHz, AIN = –1 dBFS –47 fIN = 347 MHz, AIN = –1 dBFS –75 fIN = 997 MHz, AIN = –1 dBFS –71 fIN = 2482 MHz, AIN = –1 dBFS –77 fIN = 4997 MHz, AIN = –1 dBFS –74 fIN = 6397 MHz, AIN = –1 dBFS –70 fIN = 8197 MHz, AIN = –1 dBFS –68 fIN = 347 MHz, AIN = –1 dBFS –73 fIN = 997 MHz, AIN = –1 dBFS –73 fIN = 2482 MHz, AIN = –1 dBFS –75 fIN = 4997 MHz, AIN = –1 dBFS –74 fIN = 6397 MHz, AIN = –1 dBFS –69 fIN = 8197 MHz, AIN = –1 dBFS –68 fIN = 347 MHz ± 5 MHz, AIN = –7 dBFS per tone –81 fIN = 997 MHz ± 5 MHz, AIN = –7 dBFS per tone –80 fIN = 2482 MHz ± 5 MHz, AIN = –7 dBFS per tone –72 fIN = 4997 MHz ± 5 MHz, AIN = –7 dBFS per tone –62 fIN = 6397 MHz ± 5 MHz, AIN = –7 dBFS per tone –56 fIN = 8197 MHz ± 5 MHz, AIN = –7 dBFS per tone –49 Submit Documentation Feedback MAX –56 –50 –60 –60 UNIT dBFS dBFS dBFS dBFS dBFS Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 6.9 Timing Requirements MIN NOM MAX UNIT 800 3200 MHz 312.5 1250 ps DEVICE (SAMPLING) CLOCK (CLK+, CLK–) fCLK Input clock frequency (CLK+, CLK–), both single-channel and dual-channel modes (1) tCLK Input clock period (CLK+, CLK–), both single-channel and dual-channel modes (1) SYSREF (SYSREF+, SYSREF–) tINV(SYSR EF) Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register (2) 49 ps 0 ps/°C 0.36 ps/mV tINV(TEMP) Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register tINV(VA11) Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register tSTEP(SP) Delay of SYSREF_POS LSB t(PH_SYS) Minimum SYSREF± assertion duration after SYSREF± rising edge event 4 ns t(PL_SYS) Minimum SYSREF± deassertion duration after SYSREF± falling edge event 4 ns SYSREF_ZOOM = 0 77 SYSREF_ZOOM = 1 24 ps SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS) fCLK(SCLK) Serial clock frequency 0 15.625 MHz t(PH) Serial clock high value pulse width 32 ns t(PL) Serial clock low value pulse width 32 ns tSU(SCS) Setup time from SCS to rising edge of SCLK 25 ns tH(SCS) Hold time from rising edge of SCLK to SCS 3 ns tSU(SDI) Setup time from SDI to rising edge of SCLK 25 ns tH(SDI) Hold time from rising edge of SCLK to SDI 3 ns (1) (2) Unless functionally limited to a smaller range than described in the LVDS Output Modes table based on programmed LVDS output mode. Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period (tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that were used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±. 6.10 Switching Characteristics typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEVICE (SAMPLING) CLOCK (CLK+, CLK–) tAD Sampling (aperture) delay from CLK± rising edge (dual channel mode) or rising and falling edge (single channel mode) to sampling instant (1) tAD(MAX) Maximum tAD Adjust programmable delay, not including clock inversion (TAD_INV = 0) tAD(STEP) (1) Aperture delay step size TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0 360 Coarse adjustment (TAD_COARSE = 0xFF) 289 Fine adjustment (TAD_FINE = 0xFF) 4.9 Coarse adjustment (TAD_COARSE) 1.13 ps 19 fs Fine adjustment (TAD_FINE) ps ps Both tAD and tOD increase by the delay introduced by TAD_COARSE, TAD_FINE and TAD_INV when tAD Adjust is used to delay the sampling instant. The total latency through the device does not include the aperture delay. Total latency through device is tLAT = tLAT(DIG) + tOD - tAD. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 25 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Switching Characteristics (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER tAJ TEST CONDITIONS Aperture jitter, rms MIN TYP Minimum tAD Adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) 55 Minimum tAD Adjust coarse setting (TAD_COARSE = 0xFF, TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) 70 MAX UNIT fs Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) 70 (2) Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) 80 (2) LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±) fBIT Output bit rate per output data pair 1.6 Gbps fDCLK DDR data clock frequency 800 MHz tDJ DDR data clock total jitter, peak-topeak, with random jitter portion defined with respect to a BER=1e–15 (Q=7.94) tSKEW(SAME) Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) within the same LVDS bank over operating conditions tSKEW(ALL) Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) in all LVDS banks over operating conditions with tOSAB, tOSAC and tOSBD skew excluded tOSAB (2) 26 Functional timing offset between DACLK± rising edge and DBCLK± rising edge, positive number indicates that DACLK± leads DBCLK± UPAT_CTRL = 0x10 36 ps 75 ps 125 ps DES_EN = 0, LDEMUX = 0, LALIGNED = 0 0 DES_EN = 0, LDEMUX = 0, LALIGNED = 1 0 DES_EN = 0, LDEMUX = 1, LALIGNED = 0 0 DES_EN = 0, LDEMUX = 1, LALIGNED = 1 0 DES_EN = 1, LDEMUX = 0, LALIGNED = 0 0.5 DES_EN = 1, LDEMUX = 0, LALIGNED = 1 0 DES_EN = 1, LDEMUX = 1, LALIGNED = 0 0.5 DES_EN = 1, LDEMUX = 1, LALIGNED = 1 0 tCLK tAJ increases because of additional attenuation on internal clock path. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Switching Characteristics (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER tOSAC tOSBD TEST CONDITIONS Functional timing offset between DACLK± rising edge and DCCLK± rising edge, positive number indicates that DACLK± leads DCCLK± Functional timing offset between DBCLK± rising edge and DDCLK± rising edge, positive number indicates that DBCLK± leads DDCLK± Low-to-high transition time (differential) tTLH tTHL High-to-low transition time (differential) MIN TYP DES_EN = 0, LDEMUX = 1, LALIGNED = 0 1 DES_EN = 0, LDEMUX = 1, LALIGNED = 1 0 DES_EN = 1, LDEMUX = 1, LALIGNED = 0 1 DES_EN = 1, LDEMUX = 1, LALIGNED = 1 0 DES_EN = 0, LDEMUX = 1, LALIGNED = 0 1 DES_EN = 0, LDEMUX = 1, LALIGNED = 1 0 DES_EN = 1, LDEMUX = 1, LALIGNED = 0 1 DES_EN = 1, LDEMUX = 1, LALIGNED = 1 0 MAX UNIT tCLK tCLK 20% to 80%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10 125 20% to 80%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10 200 80% to 20%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10 125 80% to 20%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10 200 TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0 1.5 DES_EN = 0, LDEMUX = 0, LALIGNED = 0 26 DES_EN = 0, LDEMUX = 0, LALIGNED = 1 26 DES_EN = 0, LDEMUX = 1, LALIGNED = 0 26 DES_EN = 0, LDEMUX = 1, LALIGNED = 1 27 DES_EN = 1, LDEMUX = 0, LALIGNED = 0 26 DES_EN = 1, LDEMUX = 0, LALIGNED = 1 26.5 DES_EN = 1, LDEMUX = 1, LALIGNED = 0 26 DES_EN = 1, LDEMUX = 1, LALIGNED = 1 27.5 ps ps LATENCY Output delay from CLK± rising edge (dual-channel mode) or falling edge (single-channel mode) to DACLK± output (1) tOD tLAT(DIG) (3) CLK± edge that samples input signal to CLK± edge that launches data, digital latency only (3) (1) ns tCLK When LDEMUX = 1 the output buses are aligned in time requiring the earlier sample(s) to be delayed before outputting on the LVDS buses to align with the later samples. The latency for the buses will be slightly different due to added delays. The number shown is for the worst case bus. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 27 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Switching Characteristics (continued) typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table PARAMETER tLAT(STB) tLAT(SYNCSE) TEST CONDITIONS Latency from SYSREF± being sampled by rising edge of CLK± to the start of the corresponding data frame (4) Latency from SYNCSE assertion or deassertion to DB0± (LSB) changing from normal data to strobe output or strobe output to normal data, digital latency only MIN TYP DES_EN = 0, LDEMUX = 0, LALIGNED = 0 47 DES_EN = 0, LDEMUX = 0, LALIGNED = 1 47 DES_EN = 0, LDEMUX = 1, LALIGNED = 0 47 DES_EN = 0, LDEMUX = 1, LALIGNED = 1 48 DES_EN = 1, LDEMUX = 0, LALIGNED = 0 46.5 DES_EN = 1, LDEMUX = 0, LALIGNED = 1 47 DES_EN = 1, LDEMUX = 1, LALIGNED = 0 46.5 DES_EN = 1, LDEMUX = 1, LALIGNED = 1 48 MAX UNIT tCLK LDEMUX = 0 26 36+1*L FRAME LDEMUX = 1 26 36+2*L FRAME tCLK SERIAL PROGRAMMING INTERFACE (SDO) t(OZD) Delay from falling edge of 16th SCLK cycle during read operation for SDO transition from tri-state to valid data t(ODZ) Delay from SCS rising edge for SDO to transition from valid data to tri-state t(OD) Delay from falling edge of SCLK during read operation to SDO valid (4) 28 1 1 ns 10 ns 10 ns When LDEMUX = 0 the output buses are staggered in time and therefore the start of data frames occur at staggered times. The number shown is for the earliest output frame. The strobe signals are output at the end of a frame so the start of a data frame corresponds to the data output immediately after a strobe output. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 INA+/t or INB+/t A1/B1 A0/B0 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tSU(SYSREF) tH(SYSREF) tLAT(STB) tSKEW DACLK+/t LVDS Bus A DASTR+/t DA[11:0]+/t A0 A1 A2 B0 B1 B2 DBCLK+/t LVDS Bus B DBSTR+/t DB[11:0]+/t NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 1. Dual-Channel, 2-Bus Mode Timing (LDEMUX = 0, DES_EN = 0, LALIGNED = 0 or 1) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 29 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 A1/B1 A0/B0 INA+/t or INB+/t www.ti.com A2/B2 A3/B3 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tSU(SYSREF) tH(SYSREF) tLAT(STB) tOSAC tOSBD tSKEW DACLK+/t LVDS Bus A DASTR+/t DA[11:0]+/t A0 A2 A4 DCCLK+/t LVDS Bus C DCSTR+/t A1 DC[11:0]+/t A3 DBCLK+/t LVDS Bus B DBSTR+/t DB[11:0]+/t B0 B2 B4 DDCLK+/t LVDS Bus D DDSTR+/t B1 DD[11:0]+/t B3 NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 2. Dual-Channel, 4-Bus, Staggered-Mode Timing (LDEMUX = 1, DES_EN = 0, LALIGNED = 0) 30 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 A1/B1 A0/B0 INA+/t or INB+/t A2/B2 A3/B3 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tSU(SYSREF) tH(SYSREF) tLAT(STB) tSKEW DACLK+/t LVDS Bus A DASTR+/t DA[11:0]+/t A0 A2 A4 A1 A3 A5 B0 B2 B4 B1 B3 B5 DCCLK+/t LVDS Bus C DCSTR+/t DC[11:0]+/t DBCLK+/t LVDS Bus B DBSTR+/t DB[11:0]+/t DDCLK+/t LVDS Bus D DDSTR+/t DD[11:0]+/t NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 3. Dual-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 0, LALIGNED = 1) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 31 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 S0 INA+/t or INB+/t S1 www.ti.com S2 S3 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tSU(SYSREF) tH(SYSREF) tLAT(STB) tSKEW(ALL) tOSAB tSKEW(SAME) DACLK+/t LVDS Bus A DASTR+/t S0 DA[11:0]+/t S2 S4 DBCLK+/t LVDS Bus B DBSTR+/t S1 DB[11:0]+/t S3 NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 4. Single-Channel, 2-Bus, Staggered-Mode Timing (LDEMUX = 0, DES_EN = 1, LALIGNED = 0) 32 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 S0 INA+/t or INB+/t S1 S2 S3 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tSU(SYSREF) tH(SYSREF) tLAT(STB) tSKEW DACLK+/t LVDS Bus A DASTR+/t DA[11:0]+/t S0 S2 S4 S1 S3 S5 DBCLK+/t LVDS Bus B DBSTR+/t DB[11:0]+/t NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 5. Single-Channel, 2-Bus, Aligned-Mode Timing (LDEMUX = 0, DES_EN = 1, LALIGNED = 1) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 33 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 S0 INA+/t or INB+/t S1 S2 www.ti.com S3 S4 S5 S6 S7 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tOSBD tSU(SYSREF) tH(SYSREF) tLAT(STB) tSKEW tOSAC tOSAB DACLK+/t LVDS Bus A DASTR+/t DA[11:0]+/t S0 S4 S8 DBCLK+/t LVDS Bus B DBSTR+/t DB[11:0]+/t S1 S5 DCCLK+/t LVDS Bus C DCSTR+/t DC[11:0]+/t S2 S6 DDCLK+/t LVDS Bus D DDSTR+/t DD[11:0]+/t S3 S7 NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 6. Single-Channel, 4-Bus, Staggered-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 0) 34 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 S0 INA+/t or INB+/t S1 S2 S3 S4 S5 S6 S7 tAD tLAT(DIG) tOD tCLK CLK+ CLKt SYSREF+ SYSREFt tSU(SYSREF) tH(SYSREF) tLAT(STB) tSKEW DACLK+/t LVDS Bus A DASTR+/t DA[11:0]+/t S0 S4 S8 S1 S5 S9 S2 S6 S10 S3 S7 S11 DBCLK+/t LVDS Bus B DBSTR+/t DB[11:0]+/t DCCLK+/t LVDS Bus C DCSTR+/t DC[11:0]+/t DDCLK+/t LVDS Bus D DDSTR+/t DD[11:0]+/t NOTE: tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing. Figure 7. Single-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 1) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 35 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com SYNCSE tLAT(SYNCSE) tLAT(SYNCSE) DxCLK+ DxCLK± Dx0+/± (LSB) X X Frame N Frame 0 Output Determined by SYNC_PAT[3:0] Shown: SYNC_PAT[3:0] = 0x2 (Strobe over LSB) Normal Data X Normal Data Figure 8. SYNCSE Timing Diagram 1st clock 16th clock 24th clock SCLK tSU(SCS) tH(SCS) t(PH) t(PL) tH(SCS) tSU(SCS) t(PH) + t(PL) = t(P) = 1 / ¦CLK(SCLK) SCS tSU(SDI) tSU(SDI) tH(SDI) SDI D7 D0 Write Command COMMAND FIELD SDO D1 tH(SDI) t(OD) Hi-Z D7 t(OZD) D1 D0 Read Command Hi-Z t(ODZ) Figure 9. Serial Interface Timing 36 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 6.11 Typical Characteristics 60 60 58 58 Signal-to-Noise Ratio (dBFS) Signal-to-Noise Ratio (dBFS) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 56 54 52 50 48 46 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 44 42 56 54 52 50 48 46 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 44 42 40 40 0 2000 4000 6000 Input Frequency (MHz) 8000 10000 0 2000 D001 DES_EN = 0, fS = 3200 MHz, foreground (FG) and background (BG) calibration Signal-to-Noise and Distortion Ratio (dBFS) Signal-to-Noise and Distortion Ratio (dBFS) 56 54 52 50 48 46 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 40 0 2000 4000 6000 Input Frequency (MHz) 8000 58 56 54 52 50 48 46 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 44 42 40 0 2000 D003 4000 6000 Input Frequency (MHz) 8000 10000 D004 DES_EN = 1, fS = 6400 MHz, FG and BG calibration Figure 13. SINAD vs Input Frequency Figure 12. SINAD vs Input Frequency 9.5 9.5 9 9 Effective Number of Bits (Bits) Effective Number of Bits (Bits) D002 60 10000 DES_EN = 0, fS = 3200 MHz, FG and BG calibration 8.5 8 7.5 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 7 10000 Figure 11. SNR vs Input Frequency 58 42 8000 DES_EN = 1, fS = 6400 MHz, FG and BG calibration Figure 10. SNR vs Input Frequency 60 44 4000 6000 Input Frequency (MHz) 6.5 8.5 8 7.5 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 7 6.5 0 2000 4000 6000 Input Frequency (MHz) 8000 10000 0 D005 DES_EN = 0, fS = 3200 MHz, FG and BG calibration 2000 4000 6000 Input Frequency (MHz) 8000 10000 D006 DES_EN = 1, fS = 6400 MHz, FG and BG calibration Figure 14. ENOB vs Input Frequency Figure 15. ENOB vs Input Frequency Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 37 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 80 Spurious-Free Dynamic Range (dBFS) Spurious-Free Dynamic Range (dBFS) 80 75 70 65 60 55 50 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 45 75 70 65 60 55 50 -1 dBFS, FG Cal -1 dBFS, BG Cal -7 dBFS, FG Cal -7 dBFS, BG Cal 45 40 40 0 2000 4000 6000 Input Frequency (MHz) 8000 0 10000 2000 D007 DES_EN = 0, fS = 3200 MHz, FG and BG calibration -55 -55 -60 -60 -65 -65 -70 -75 -80 -85 -75 -80 -85 HD2, -1 dBFS HD2, -7 dBFS HD3, -1 dBFS HD3, -7 dBFS -90 -95 -100 0 2000 4000 6000 Input Frequency (MHz) 8000 0 10000 2000 D009 DES_EN = 0, fS = 3200 MHz, FG calibration 8000 10000 D010 Figure 19. HD2 and HD3 vs Input Frequency -40 -45 -45 Worst Interleaving Spur (dBFS) -40 -50 -55 -60 -65 -70 -75 -80 -1 dBFS -7 dBFS -85 4000 6000 Input Frequency (MHz) DES_EN = 1, fS = 6400 MHz, FG calibration Figure 18. HD2 and HD3 vs Input Frequency Worst Interleaving Spur (dBFS) D008 -70 HD2, -1 dBFS HD2, -7 dBFS HD3, -1 dBFS HD3, -7 dBFS -100 -50 -55 -60 -65 -70 -75 -80 -1 dBFS -7 dBFS -85 -90 -90 0 2000 4000 6000 Input Frequency (MHz) 8000 10000 0 2000 D011 DES_EN = 0, fS = 3200 MHz, FG calibration, includes fS / 2 – fIN spur only Figure 20. Worst Interleaving Spur vs Input Frequency 38 10000 Figure 17. SFDR vs Input Frequency -50 Magnitude (dBFS) Magnitude (dBFS) Figure 16. SFDR vs Input Frequency -95 8000 DES_EN = 1, fS = 6400 MHz, FG and BG calibration -50 -90 4000 6000 Input Frequency (MHz) 4000 6000 Input Frequency (MHz) 8000 10000 D012 DES_EN = 1, fS = 6400 MHz, FG calibration, includes fS / 2 – fIN and fS /4 ± fIN spurs only Figure 21. Worst Interleaving Spur vs Input Frequency Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 60 Signal-to-Noise Ratio (dBFS) Signal-to-Noise Ratio (dBFS) 60 55 50 45 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 40 35 800 1200 1600 2000 fS (MSPS) 2400 2800 55 50 45 40 35 1600 3200 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 2400 DES_EN = 0, FG calibration, AIN = –1 dBFS Signal-to-Noise and Distortion Ratio (dBFS) Signal-to-Noise and Distortion Ratio (dBFS) 55 50 45 40 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 30 25 1200 1600 2000 fS (MSPS) 2400 2800 3200 6400 D021 55 50 45 40 35 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 30 25 20 1600 2400 3200 D022 4000 fS (MSPS) 4800 5600 6400 D023 DES_EN = 1, FG calibration, AIN = –1 dBFS Figure 24. SINAD vs Sampling Rate Figure 25. SINAD vs Sampling Rate 9.5 9.5 9 9 8.5 8.5 Effective Number of Bits (Bits) Effective Number of Bits (Bits) 5600 60 DES_EN = 0, FG calibration, AIN = –1 dBFS 8 7.5 7 6.5 6 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 5.5 5 4.5 4 3.5 800 4800 Figure 23. SNR vs Sampling Rate 60 35 4000 fS (MSPS) DES_EN = 1, FG calibration, AIN = –1 dBFS Figure 22. SNR vs Sampling Rate 20 800 3200 D020 1200 1600 2000 fS (MSPS) 2400 2800 8 7.5 7 6.5 6 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 5.5 5 4.5 4 3200 3.5 1600 2400 D024 DES_EN = 0, FG calibration, AIN = –1 dBFS 3200 4000 fS (MSPS) 4800 5600 6400 D025 DES_EN = 1, FG calibration, AIN = –1 dBFS Figure 26. ENOB vs Sampling Rate Figure 27. ENOB vs Sampling Rate Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 39 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 800 Spurious-Free Dynamic Range (dBFS) Spurious-Free Dynamic Range (dBFS) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 1200 1600 2000 fS (MSPS) 2400 2800 3200 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 1600 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 2400 D026 DES_EN = 0, FG calibration, AIN = –1 dBFS 60 60 55 50 45 347 MHz, dBFS 347 MHz, dBc 2488 MHz, dBFS 2488 MHz, dBc 5997 MHz, dBFS 5997 MHz, dBc 30 25 -24 -20 -16 -12 -8 Input Power (dBFS) -4 40 347 MHz, dBFS 347 MHz, dBc 2488 MHz, dBFS 2488 MHz, dBc 5997 MHz, dBFS 5997 MHz, dBc 35 25 -24 0 -20 D030 -4 Spurious-Free Dynamic Range (dB) Spurious-Free Dynamic Range (dB) -4 0 D031 Figure 31. SNR vs Input Power 0 85 80 75 70 65 60 55 50 45 40 35 30 25 20 -24 347 MHz, dBFS 347 MHz, dBc 2488 MHz, dBFS 2488 MHz, dBc 5997 MHz, dBFS 5997 MHz, dBc -20 -16 -12 -8 Input Power (dBFS) -4 0 D033 DES_EN = 1, FG calibration, fS = 6400 MSPS Figure 32. SFDR vs Input Power 40 -16 -12 -8 Input Power (dBFS) DES_EN = 1, FG calibration, fS = 6400 MSPS D032 DES_EN = 0, FG calibration, fS = 3200 MSPS D027 45 30 347 MHz, dBFS 347 MHz, dBc 2488 MHz, dBFS 2488 MHz, dBc 5997 MHz, dBFS 5997 MHz, dBc -16 -12 -8 Input Power (dBFS) 6400 50 Figure 30. SNR vs Input Power -20 5600 55 DES_EN = 0, FG calibration, fS = 3200 MSPS 85 80 75 70 65 60 55 50 45 40 35 30 25 20 -24 4800 Figure 29. SFDR vs Sampling Rate 65 Signal-to-Noise Ratio (dB) Signal-to-Noise Ratio (dB) Figure 28. SFDR vs Sampling Rate 35 4000 fS (MSPS) DES_EN = 1, FG calibration, AIN = –1 dBFS 65 40 3200 Submit Documentation Feedback Figure 33. SFDR vs Input Power Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 70 Spurious-Free Dynamic Range (dBFS) Signal-to-Noise Ratio (dBFS) 60 55 50 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 45 40 65 60 55 50 45 40 347 MHz 997 MHz 2488 MHz 4997 MHz 5997 MHz 8197 MHz 35 30 25 20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Clock Differential Input Voltage (VPP-DIFF) 1.8 2 0 0.2 D038 DES_EN = 1, FG calibration, fS = 6400 MSPS, AIN = –1 dBFS 2 D039 Figure 35. SFDR vs Clock Amplitude 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) 1.8 DES_EN = 1, FG calibration, fS = 6400 MSPS, AIN = –1 dBFS Figure 34. SNR vs Clock Amplitude -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 400 800 Freqency (MHz) 1200 1600 0 800 D040 DES_EN = 0, FG calibration, fS = 3200 MSPS, SNR = 57.2 dBFS, SFDR = 74 dBFS, ENOB = 9.1 bits Figure 36. Single-Tone FFT at fIN = 347 MHz, AIN = –1 dBFS 0 -20 -20 -60 -80 2400 3200 D041 Figure 37. Single-Tone FFT at fIN = 347 MHz, AIN = –1 dBFS 0 -40 1600 Freqency (MHz) DES_EN = 1, FG calibration, fS = 6400 MSPS, SNR = 57.2 dBFS, SFDR = 69 dBFS, ENOB = 9.1 bits Magnitude (dBFS) Magnitude (dBFS) 0.4 0.6 0.8 1 1.2 1.4 1.6 Clock Differential Input Voltage (VPP-DIFF) -40 -60 -80 -100 -100 -120 -120 0 400 800 Freqency (MHz) 1200 1600 0 D042 DES_EN = 0, FG calibration, fS = 3200 MSPS, SNR = 55.6 dBFS, SFDR = 64 dBFS, ENOB = 8.6 bits Figure 38. Single-Tone FFT at fIN = 2488 MHz, AIN = –1 dBFS 800 1600 Freqency (MHz) 2400 3200 D043 DES_EN = 1, FG calibration, fS = 6400 MSPS, SNR = 55.8 dBFS, SFDR = 58 dBFS, ENOB = 8.5 bits Figure 39. Single-Tone FFT at fIN = 2488 MHz, AIN = –1 dBFS Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 41 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) -40 -60 -80 -100 400 800 Freqency (MHz) 1200 1600 0 800 D044 DES_EN = 0, FG calibration, fS = 3200 MSPS, SNR = 56.9 dBFS, SFDR = 71 dBFS, ENOB = 9.1 bits Figure 40. Single-Tone FFT at fIN = 2488 MHz, AIN = –7 dBFS 0 -20 -20 -60 -80 2400 3200 D045 Figure 41. Single-Tone FFT at fIN = 2488 MHz, AIN = –7 dBFS 0 -40 1600 Freqency (MHz) DES_EN = 1, FG calibration, fS = 6400 MSPS, SNR = 57.5 dBFS, SFDR = 65 dBFS, ENOB = 9.0 bits Magnitude (dBFS) Magnitude (dBFS) -80 -120 0 -100 -40 -60 -80 -100 -120 -120 0 400 800 Freqency (MHz) 1200 1600 0 800 D046 DES_EN = 0, FG calibration, fS = 3200 MSPS, SNR = 53.4 dBFS, SFDR = 57 dBFS, ENOB = 8.1 bits Figure 42. Single-Tone FFT at fIN = 4997 MHz, AIN = –1 dBFS 0 -20 -20 -60 -80 -100 2400 3200 D047 Figure 43. Single-Tone FFT at fIN = 4997 MHz, AIN = –1 dBFS 0 -40 1600 Freqency (MHz) DES_EN = 1, FG calibration, fS = 6400 MSPS, SNR = 53.7 dBFS, SFDR = 58 dBFS, ENOB = 8.2 bits Magnitude (dBFS) Magnitude (dBFS) -60 -100 -120 -40 -60 -80 -100 -120 -120 0 400 800 Freqency (MHz) 1200 1600 0 D048 DES_EN = 0, FG calibration, fS = 3200 MSPS, SNR = 50.6 dBFS, SFDR = 53 dBFS, ENOB = 7.5 bits Figure 44. Single-Tone FFT at fIN = 8197 MHz, AIN = –1 dBFS 42 -40 800 1600 Freqency (MHz) 2400 3200 D049 DES_EN = 1, FG calibration, fS = 6400 MSPS, SNR = 50.8 dBFS, SFDR = 45 dBFS, ENOB = 6.9 bits Figure 45. Single-Tone FFT at fIN = 8197 MHz, AIN = –1 dBFS Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Typical Characteristics (continued) 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 400 800 Frequency (MHz) 1200 1600 0 800 D050 1600 Frequency (MHz) 2400 3200 D051 DES_EN = 1, FG calibration, fS = 6400 MSPS, f1 = 342 MHz, f2 = 352 MHz, AIN = –7 dBFS per tone, SFDR = –73 dBFS, IMD3 = –81 dBFS, IMD2 = –88 dBFS Figure 46. Two-Tone FFT at fIN = 347 MHz, AIN = –1 dBFS Figure 47. Two-Tone FFT at fIN = 347 MHz, AIN = –1 dBFS 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) DES_EN = 0, FG calibration, fS = 3200 MSPS, f1 = 342 MHz, f2 = 352 MHz, AIN = –7 dBFS per tone, SFDR = –77 dBFS, IMD3 = –87 dBFS, IMD2 = –77 dBFS -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 400 800 Frequency (MHz) 1200 1600 0 800 D052 1600 Frequency (MHz) 2400 3200 D053 DES_EN = 1, FG calibration, fS = 6400 MSPS, f1 = 2483 MHz, f2 = 2493 MHz, AIN = –7 dBFS per tone, SFDR = –60 dBFS, IMD3 = –72 dBFS, IMD2 = –78 dBFS Figure 48. Two-Tone FFT at fIN = 2488 MHz, AIN = –1 dBFS Figure 49. Two-Tone FFT at fIN = 2488 MHz, AIN = –1 dBFS 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) DES_EN = 0, FG calibration, fS = 3200 MSPS, f1 = 2483 MHz, f2 = 2493 MHz, AIN = –7 dBFS per tone, SFDR = –71 dBFS, IMD3 = –71 dBFS, IMD2 = –75 dBFS -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 400 800 Frequency (MHz) 1200 1600 0 D054 800 1600 Frequency (MHz) 2400 3200 D055 DES_EN = 0, FG calibration, fS = 3200 MSPS, f1 = 4992 MHz, f2 = 5002 MHz, AIN = –7 dBFS per tone, SFDR = –61 dBFS, IMD3 = –61 dBFS, IMD2 = –77 dBFS DES_EN = 1, FG calibration, fS = 6400 MSPS, f1 = 4992 MHz, f2 = 5002 MHz, AIN = –7 dBFS per tone, SFDR = –60 dBFS, IMD3 = –62 dBFS, IMD2 = –78 dBFS Figure 50. Two-Tone FFT at fIN = 4997 MHz, AIN = –1 dBFS Figure 51. Two-Tone FFT at fIN = 4997 MHz, AIN = –1 dBFS Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 43 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 3 0.4 2 Integral Nonlinearity (LSB) Differential Nonlinearity (LSB) 0.3 0.2 0.1 0 -0.1 -0.2 1 0 -1 -2 -0.3 -3 -0.4 0 1024 2048 Code 3072 0 4095 1024 DES_EN = 1, FG calibration, fS = 6400 MSPS, fIN = 247 MHz Figure 52. DNL vs Code SNR SINAD SFDR -40 -45 Magnitude (dBFS) Magnitude (dBFS) HD2 HD3 fS/4+fIN fS/4-fIN fS/2-fIN -35 60 58 56 54 -50 -55 -60 -65 -70 -75 -80 52 -85 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 -90 -75 125 58 Signal-to-Noise Ratio (dBFS) 60 58 56 54 52 50 48 46 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C -50 -25 0 25 50 75 Ambient Temperature (°C) 100 0 25 50 75 Ambient Temperature (°C) 100 125 D071 Figure 55. Performance vs Temperature 60 42 -25 DES_EN = 1, FG calibration, fS = 6400 MSPS, fIN = 2488 MHz, AIN = –1 dBFS Figure 54. Performance vs Temperature 44 -50 D070 DES_EN = 1, FG calibration, fS = 6400 MSPS, fIN = 2488 MHz, AIN = –1 dBFS Signal-to-Noise Ratio (dBFS) D061 Figure 53. INL vs Code 62 44 4095 -30 64 40 -75 3072 DES_EN = 1, FG calibration, fS = 6400 MSPS, fIN = 247 MHz 66 50 -75 2048 Code D060 56 54 52 50 48 46 44 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C 42 125 40 -75 -50 D080 -25 0 25 50 75 Ambient Temperature (°C) 100 125 D081 DES_EN = 0, fS = 3200 MSPS, fIN = 347 MHz, AIN = –1 dBFS DES_EN = 1, fS = 6400 MSPS, fIN = 347 MHz, AIN = –1 dBFS Figure 56. SNR vs Temperature and Calibration Mode Figure 57. SNR vs Temperature and Calibration Mode Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Typical Characteristics (continued) 60 Signal-to-Noise and Distortion Ratio (dBFS) Signal-to-Noise and Distortion Ratio (dBFS) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 58 56 54 52 50 48 46 44 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C 42 40 -75 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 56 54 52 50 48 46 44 40 -75 9 9 Effective Number of Bits (Bits) 9.5 8.5 8 7.5 6.5 -75 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C -50 -25 0 25 50 75 Ambient Temperature (°C) 100 -25 0 25 50 75 Ambient Temperature (°C) 100 125 D083 8.5 8 7.5 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C 7 6.5 -75 125 -50 -25 D084 DES_EN = 0, fS = 3200 MSPS, fIN = 347 MHz, AIN = –1 dBFS 0 25 50 75 Ambient Temperature (°C) 100 125 D085 DES_EN = 1, fS = 6400 MSPS, fIN = 347 MHz, AIN = –1 dBFS Figure 60. ENOB vs Temperature and Calibration Mode Figure 61. ENOB vs Temperature and Calibration Mode 80 Spurious-Free Dynamic Range (dBFS) 80 75 70 65 60 55 50 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C 45 40 -75 -50 Figure 59. SINAD vs Temperature and Calibration Mode 9.5 7 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C 42 DES_EN = 1, fS = 6400 MSPS, fIN = 347 MHz, AIN = –1 dBFS Figure 58. SINAD vs Temperature and Calibration Mode Effective Number of Bits (Bits) 58 D082 DES_EN = 0, fS = 3200 MSPS, fIN = 347 MHz, AIN = –1 dBFS Spurious-Free Dynamic Range (dBFS) 60 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 75 70 65 60 55 50 BG Calibration FG Calibration at Each Temperature FG Calibration at 25°C 45 40 -75 -50 D086 DES_EN = 0, fS = 3200 MSPS, fIN = 347 MHz, AIN = –1 dBFS Figure 62. SFDR vs Temperature and Calibration Mode -25 0 25 50 75 Ambient Temperature (°C) 100 125 D087 DES_EN = 1, fS = 6400 MSPS, fIN = 347 MHz, AIN = –1 dBFS Figure 63. SFDR vs Temperature and Calibration Mode Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 45 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) -35 66 SNR SINAD SFDR 64 -45 60 Magnitude (dBFS) Magnitude (dBFS) 62 HD2 HD3 fS/4+fIN fS/4-fIN fS/2-fIN -40 58 56 54 52 50 -50 -55 -60 -65 -70 -75 48 -80 46 -5 -85 -5 -4 -3 -2 -1 0 1 2 3 Supply Voltage Variation from Nominal (%) 4 5 DES_EN = 1, FG calibration, fS = 6400 MSPS, fIN = 2488 MHz, AIN = –1 dBFS VA11 Supply Current (A) VA19 Supply Current (A) D101 0.7 1 0.9 0.8 BG Calibration FG Calibration LPBG Calibration 0.7 1200 1600 2000 fCLK (MHz) 2400 2800 0.6 0.5 0.4 0.3 0.2 BG Calibration FG Calibration LPBG Calibration 0.1 0 800 3200 1200 1600 D110 2000 fCLK (MHz) 2400 2800 3200 D111 DES_EN = 1, fIN = 2488 MHz, AIN = –1 dBFS DES_EN = 1, fIN = 2488 MHz, AIN = –1 dBFS Figure 66. VA19 Supply Current vs Clock Rate Figure 67. VA11 Supply Current vs Clock Rate 0.5 0.5 BG Calibration FG Calibration LPBG Calibration 0.4 VLVDS Supply Current (A) VD11 Supply Current (A) 5 Figure 65. Performance vs Supply Voltage 1.1 0.3 0.2 0.1 1200 1600 2000 fCLK (MHz) 2400 2800 3200 0.4 0.3 0.2 0.1 BG Calibration FG Calibration LPBG Calibration 0 800 1200 D112 DES_EN = 1, fIN = 2488 MHz, AIN = –1 dBFS Figure 68. VD11 Supply Current vs Clock Rate 46 4 0.8 1.2 0 800 -3 -2 -1 0 1 2 3 Supply Voltage Variation from Nominal (%) DES_EN = 1, FG calibration, fS = 6400 MSPS, fIN = 2488 MHz, AIN = –1 dBFS Figure 64. Performance vs Supply Voltage 0.6 800 -4 D100 1600 2000 fCLK (MHz) 2400 2800 3200 D113 DES_EN = 1, fIN = 2488 MHz, AIN = –1 dBFS, VLVDS = 1.9 V Figure 69. VLVDS Supply Current vs Clock Rate Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 4 0.4 Power Consumption (W) VLVDS Supply Current (A) 0.5 0.3 0.2 0.1 3.5 3 2.5 BG Calibration FG Calibration LPBG Calibration 0 800 1200 1600 2000 fCLK (MHz) 2400 2800 BG Calibration FG Calibration LPBG Calibration 2 800 3200 DES_EN = 1, fIN = 2488 MHz, AIN = –1 dBFS, VLVDS = 1.1 V 1600 2000 fCLK (MHz) 2400 2800 3200 D115 DES_EN = 1, fIN = 2488 MHz, AIN = –1 dBFS, VLVDS = 1.9 V Figure 70. VLVDS Supply Current vs Clock Rate Figure 71. Power Consumption vs Clock Rate 3 Normalized Gain Response (dB) 4.5 Power Consumption (W) 1200 D114 4 3.5 3 BG Calibration FG Calibration LPBG Calibration 2.5 -75 0 -3 -6 -9 Dual-Channel Mode Single-Channel Mode -12 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 0 2000 D116 4000 6000 Input Frequency (MHz) 8000 10000 D_BW DES_EN = 1, fS = 6400 MSPS, fIN = 2488 MHz, AIN = –1 dBFS, VLVDS = 1.9 V Figure 72. Power Consumption vs Temperature Figure 73. Gain Response vs Input Frequency 2200 4000 3500 2000 2500 Sample Value Sample Value 3000 Zoomed Area in Following Plot 2000 1500 1000 1800 1600 500 0 0 5000 10000 15000 20000 25000 Sample Number 30000 35000 1400 14800 D125 15200 15600 Sample Number 16000 16400 D126 DES_EN = 1, fS = 6400 MSPS, fIN = 3199.9 MHz DES_EN = 1, fS = 6400 MSPS, fIN = 3199.9 MHz Figure 74. Background Calibration Core Transition (AC Signal) Figure 75. Background Calibration Core Transition (AC Signal Zoomed) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 47 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Characteristics (continued) typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs) 4096 500 -0.35V Differential 3584 +0.35 V Differential -0.35 V Differential 0 V Differential 400 Sample Value Sample Value 3072 2560 2048 1536 1024 Zoomed Area in Following Plot 300 200 100 512 0 0 1000 2000 3000 4000 5000 Sample Number 6000 7000 8000 1700 D127 DES_EN = 1, fS = 6400 MSPS, DC input Figure 76. Background Calibration Core Transition (DC Signal) 48 0 1600 1800 1900 2000 2100 Sample Number 2200 2300 2400 D128 DES_EN = 1, fS = 6400 MSPS, DC input Figure 77. Background Calibration Core Transition (DC Signal Zoomed) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7 Detailed Description 7.1 Overview The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200MSPS and in single-channel mode up to 6400-MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8 GHz and a useable frequency range that allows direct RF sampling of L-band, S-band, Cband, and X-band for frequency agile systems. The ADC12DL3200 uses a low latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, 4 double data rate (DDR) clocks and 4 strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing. 7.2 Functional Block Diagram CALTRG SCLK SDI SDO SCS PD ORA0 ORA1 ORB0 ORB1 CALSTAT TDIODE+ TDIODE± DACLK+ DACLK± SPI Registers and Device Control Status Indicators DA11+ DA11± LVDS Bus A DA0+ DA0± DASTR+ DASTR± TMSTP+ Demux TMSTP± DCCLK+ DCCLK± DC11+ DC11± INA+ Input MUX Sample Marking ADC A LVDS Bus C DC0+ DC0± INA± DCSTR+ DCSTR± Overrange Strobe Source Strobe Generation and LSB Replacement SYNCSE DBCLK+ DBCLK± INB+ DB11+ DB11± INB± Input MUX ADC B LVDS Bus B Sample Marking DB0+ DB0± Aperture Delay Adjust CLK+ DBSTR+ DBSTR± Demux DDCLK+ DDCLK± Clock Distribution and Synchronization CLK± SYSREF+ DD11+ DD11± LVDS Bus D DD0+ DD0± SYSREF Windowing SYSREF± DDSTR+ DDSTR± Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 49 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.3 Feature Description 7.3.1 Analog Inputs The analog inputs of the ADC12DL3200 have internal buffers to enable high input bandwidth and isolate sampling capacitor glitch noise from the input circuit. The analog inputs must be driven differentially as operation with a single-ended signal is not recommended because of performance degradation. AC-coupling or DCcoupling can be used with the analog inputs. The common-mode voltage of the analog inputs is 0 V and is biased internally through single-ended, 50-Ω resistors to AGND on each input pin. When DC-coupled input signals are used the applied differential signal must have a common-mode voltage that meets the device Input common-mode requirements. See VCMI in the Recommended Operating Conditions table. The 0-V input common-mode voltage simplifies the interface to split-supply differential amplifiers and to a variety of transformers and baluns. In single-channel mode, either analog input (AIN+ and AIN– or BIN+ and BIN–) can be used as the input to the ADC core. There is no degradation in analog input bandwidth when using single-channel mode versus dualchannel mode. The input can be chosen using SINGLE_INPUT in the INPUT_MUX register. In dual-channel mode, the analog inputs can be swapped using DUAL_INPUT in the INPUT_MUX register. 7.3.1.1 Analog Input Protection The analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of sourcing or sinking input currents during overrange conditions; see the voltage and current limits in the Absolute Maximum Ratings table. The overrange protection is also defined for a peak RF input power in the Absolute Maximum Ratings table, which is frequency independent. Operation above the maximum conditions listed in the Recommended Operating Conditions table results in an increase in failure-in-time (FIT) rate, so the system must correct the overdrive condition as quickly as possible. Figure 78 shows the analog input protection diodes. AGND Analog input protection diodes. 50 INA+, INB+ ADC INA±, INB± 50 Input Buffer Figure 78. ADC12DL3200 Analog Input Internal Termination 7.3.1.2 Full-Scale Voltage (VFS) Adjustment Input full-scale voltage (VFS) adjustment is available, in fine increments, for each analog input through the FS_RANGE_A (see the INA full-scale range adjust register) and FS_RANGE_B register settings (see the INB full-scale range adjust register) for INA± and INB±, respectively. The available adjustment range is specified in the Electrical Characteristics: DC Specifications table. Larger full-scale voltages improve SNR performance, but can degrade harmonic distortion. The full-scale voltage adjustment is useful for matching the full-scale range of multiple ADCs when developing a multi-converter system or for external interleaving of multiple ADC12DL3200s to achieve higher sampling rates. 7.3.1.3 Analog Input Offset Adjust The input offset voltage for each input can be adjusted through the OADJ_x_FG0_VINy and OADJ_x_FG90_VINy registers (registers 0x330 to 0x34F), where x represents the ADC core (A or B) and y represents the analog input (INA± or INB±). The adjustment range is approximately 28 mV to –28 mV differential. See the Calibration Modes and Trimming section for more information. 50 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Feature Description (continued) 7.3.2 ADC Core The ADC12DL3200 consists of a total of six ADC cores. The cores are interleaved for higher sampling rates and swapped on-the-fly for calibration as required by the operating mode. In dual-channel mode each ADC channel is two-way interleaved. In single-channel mode the ADC is four-way interleaved. This section highlights the theory of operation and key features of the ADC cores. 7.3.2.1 ADC Theory of Operation The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or by the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the voltage on INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a negative 2's complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–, respectively, then the digital output is a positive 2's complement value. Equation 1 can calculate the differential voltage at the input pins from the digital output. Code VIN V FS 2N where • • • Code is the signed decimation output code (for example, –2048 to +2047) N is the ADC resolution VFS is the full-scale input voltage of the ADC as specified in the Recommended Operating Conditions table, including any adjustment performed by programming FS_RANGE_A or FS_RANGE_B (1) 7.3.2.2 ADC Core Calibration ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be repeated when operating conditions change significantly, namely temperature, in order to maintain optimal performance. The ADC12DL3200 has a built-in calibration routine that can be run as a foreground operation or a background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the input signal, to complete the process. Background calibration can be used to overcome this limitation and allow constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each mode. 7.3.2.3 ADC Overrange Detection To ensure that system gain management has the quickest possible response time, a low-latency configurable overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of the upper eight bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. These thresholds apply to both channel A and channel B in dual-channel mode. Table 1 lists how an ADC sample is converted to an absolute value for a comparison of the thresholds. Table 1. Conversion of ADC Sample for Overrange Comparison ADC SAMPLE (Offset Binary) ADC SAMPLE (2's Complement) ABSOLUTE VALUE UPPER 8 BITS USED FOR COMPARISON 1111 1111 1111 (4095) 0111 1111 1111 (2047) 111 1111 1111 (2047) 1111 1111 (255) 1111 1111 0000 (4080) 0111 1111 0000 (2032) 111 1111 0000 (2032) 1111 1110 (254) 1000 0000 0000 (2048) 0000 0000 0000 (0) 000 0000 0000 (0) 0000 0000 (0) 0000 0001 0000 (16) 1000 0001 0000 (–2032) 111 1111 0000 (2032) 1111 1110 (254) 0000 0000 0000 (0) 1000 0000 0000 (–2048) 111 1111 1111 (2047) 1111 1111 (255) If the upper eight bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is 0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1 corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 51 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be OR'd together to determine whether an over-range condition occurred. OVR_N can be used to set the output pulse duration from the last overrange event. Table 2 lists the overrange pulse durations for the various OVR_N settings (see the overrange configuration register). Table 2. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs OVR_N OVERRANGE PULSE DURATION FROM LAST OVERRANGE EVENT (DEVCLK Cycles) 0 8 1 16 2 32 3 64 4 128 5 256 6 512 7 1024 Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above −12 dBFS). 7.3.2.4 Code Error Rate (CER) ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle codes, resulting from metastability caused by non-ideal comparator limitations. The ADC12DL3200 uses a unique ADC architecture that inherently allows significant code error rate improvements from traditional pipelined flash or successive approximation register (SAR) ADCs. The code error rate of the ADC12DL3200 is multiple orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates, providing significant signal reliability improvements. 7.3.2.5 Internal Dither The ADC12DL3200 includes internal dither to smooth out the integral nonlinearity (INL) curve. Dither improves the high-order harmonic performance of the ADC cores that results in a reduction of spurs in the frequency spectrum for single-tone and narrow-band signals. The dither signal is subtracted out of converted data so that dither does not show up in the output signal and thus reduce the signal-to-noise signal. 7.3.3 Timestamp The TMSTP+ and TMSTP– differential inputs can be used as a timestamp input to mark a specific sample based on the timing of an external trigger event relative to the sampled signal. TIME_STAMP_EN (see the LSB control bit output register) must be set in order to use the timestamp feature and output the timestamp data. When enabled, the LSB of the 12-bit ADC digital output reports the status of the TMSTP± input. In effect, the 12-bit output sample consists of the upper 11-bits of the 12-bit converter and the LSB of the 12-bit output sample is the output of a parallel 1-bit converter (TMSTP±) with the same latency as the ADC core. The trigger must be applied to the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling clock and is sampled at approximately the same time as the analog input. Alternatively, the SYSREF± inputs can be used as the timestamp input when SYSREF_TIME_STAMP_EN is set to 1 in the CLK_CTRL1 register. 52 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.3.4 Clocking The clocking subsystem of the ADC12DL3200 has two input signals: the device clock (CLK+, CLK–) and SYSREF (SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD adjust), a clock duty cycle corrector, and a SYSREF capture block. Figure 79 shows the clocking subsystem. Duty Cycle Correction tAD Adjust Clock Distribution and Synchronization (ADC cores, digital, interface, etc.) CLK+ E _F IN TA D _C E OA TA D TA D _I N V R S CLK± SYSREF Capture SYSREF+ SYSREF Windowing Automatic SYSREF Calibration SYSREF_POS SYSREF_SEL SRC_EN SYSREF± Figure 79. ADC12DL3200 Clocking Subsystem The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing and LVDS outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment (tAD adjust) allows the sampling instance of the ADC to be shifted in fine steps in order to synchronize multiple ADC12DL3200 devices or to fine-tune system latency. Duty cycle correction is implemented in the ADC12DL3200 to ease the requirements on the external device clock while maintaining high performance. Table 3 summarizes the device clock interface in dual-channel mode and single-channel mode. Table 3. Device Clock versus Mode of Operation MODE OF OPERATION SAMPLING RATE VS fCLK SAMPLING INSTANT Dual-channel mode 1 × fCLK Rising edge Single-channel mode 2 × fCLK Rising and falling edge SYSREF is a system timing reference used to reset clock dividers and strobe generation within the ADC12DL3200 that is similar to the SYSREF signal used by JESD204B interface devices. SYSREF is used to synchronize multiple ADC12DL3200 devices. SYSREF must be captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The ADC12DL3200 includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the frame clock frequency. Equation 2 can be used to calculate valid SYSREF frequencies. f CLK f SYSREF LDEMUX 1 u LFRAME u n where • • • LDEMUX and LFRAME are register settings fCLK is the device clock frequency (CLK±) n is any positive integer (2) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 53 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust) The ADC12DL3200 contains a delay adjustment on the device clock (sampling clock) input path, called tAD adjust, that can be used to shift the sampling instance within the device in order to align sampling instances among multiple devices or for external interleaving of multiple ADC12DL3200 devices. Further, tAD adjust can be used for automatic SYSREF calibration to simplify synchronization; see the Automatic SYSREF Calibration section. Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a slight degradation in aperture jitter (tAJ) is possible at large values of TAD_COARSE because of internal clock path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input frequencies (see tAJ in the Switching Characteristics table). This feature is programmed using TAD_INV, TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting in a delay equal to half the clock period. Table 4 summarizes the step sizes and ranges of the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All clocks within the device are shifted by the programmed tAD adjust amount, which results in a shift of the timing of the LVDS data interface and affects the capture of SYSREF. Table 4. tAD Adjust Adjustment Ranges ADJUSTMENT PARAMETER ADJUSTMENT STEP DELAY SETTINGS TAD_INV 1 / (fCLK × 2) 1 MAXIMUM DELAY 1 / (fCLK × 2) TAD_COARSE See tTAD(STEP) in the Switching Characteristics table 256 See tTAD(MAX) in the Switching Characteristics table TAD_FINE See tTAD(STEP) in the Switching Characteristics table 256 See tTAD(MAX) in the Switching Characteristics table In order to maintain timing alignment between converters, stable and matched power-supply voltages and device temperatures must be provided. Aperture delay adjustment can be changed on-the-fly during normal operation, however changing the aperture delay also shifts the clock for the LVDS data interface (DxCLK±, DxSTR±, and Dx[11:0]±). The receiving circuit must be tolerant of shifts in the LVDS data timing. Use of the TAD_RAMP feature may help the receiver avoid loss of synchronization; see the Aperture Delay Ramp Control (TAD_RAMP) section. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP) The ADC12DL3200 contains a function to gradually adjust the tAD adjust setting towards the newly written TAD_COARSE value. This functionality allows the tAD adjust setting to be adjusted with minimal internal clock circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 256 tCLK cycles) or faster ramp (four TAD_COARSE LSBs per 256 tCLK cycles) to be selected. The TAD_RAMP_EN parameter enables the ramp feature and any subsequent writes to TAD_COARSE to initiate a new ramp. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic latency. The SYSREF signal must be captured by a deterministic device clock (CLK±) edge at each system power-on and at each device in the system. This requirement imposes setup and hold constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all system operating conditions. The ADC12DL3200 includes a number of features to simplify this synchronization process and to relax system timing constraints: • The ADC12DL3200 uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input frequency by half and double the timing window for SYSREF (see Table 3) • A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid in meeting setup and hold times over all conditions; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section • Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (tAD adjust) to shift the ADC sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the ADC sampling instance); see the Automatic SYSREF Calibration section 54 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge and then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However, this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system. This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the SYSREF_POS bits of the SYSREF capture position register. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL in clock control register 0 to the value corresponding to that SYSREF_POS position. In general, the middle sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and SYSREF_SEL are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide maximum margin for operating condition variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as system operating conditions change. In general, a single value can be found that meets timing over all conditions for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking device. NOTE SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the Automatic SYSREF Calibration section. The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are finer. See the Switching Characteristics table for delay step sizes when SYSREF_ZOOM is enabled and disabled. In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient information to determine if these settings are close to a timing violation, although the actual valid window can extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS. Table 5 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings. Although 24 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage; however, in the fourth example a value of 15 provides additional margin and can be selected instead. Table 5. Examples of SYSREF_POS Readings and SYSREF_SEL Selections SYSREF_POS[23:0] (1) OPTIMAL SYSREF_SEL SETTING 0x02E[7:0] (Largest Delay) 0x02D[7:0] (1) 0x02C[7:0] (1) (Smallest Delay) b10000000 b01100000 b00011001 b10011000 b00000000 b00110001 12 b10000000 b01100000 b00000001 6 or 7 b10000000 b00000011 b00000001 4 or 15 b10001100 b01100011 b00011001 6 8 or 9 Red coloration indicates the bits that are selected, as given in the last column of this table. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 55 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.3.4.3.2 Automatic SYSREF Calibration The ADC12DL3200 has an automatic SYSREF calibration feature to alleviate the often challenging setup and hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF calibration uses the tAD adjust feature to shift the device clock to maximize the SYSREF setup and hold times or to align the sampling instance based on the SYSREF rising edge. The ADC12DL3200 must have a proper device clock applied and be programmed for normal operation before starting the automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous SYSREF signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic SYSREF calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable register after configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN high, the ADC12DL3200 searches for the optimal tAD adjust setting until the device clock falling edge is internally aligned to the SYSREF rising edge. SRC_DONE in the SYSREF calibration status register can be monitored to ensure that the SYSREF calibration has finished. By aligning the device clock falling edge with the SYSREF rising edge, automatic SYSREF calibration maximizes the internal SYSREF setup and hold times relative to the device clock and also sets the sampling instant based on the SYSREF rising edge. After the automatic SYSREF calibration finishes, the rest of the startup procedure can be performed to finish bringing up the system. For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore trace lengths must be matched from a common SYSREF source to each ADC12DL3200. Any skew between the SYSREF rising edge at each device results in additional error in the sampling instance between devices, however repeatable deterministic latency from system startup to startup through each device must still be achieved. Figure 80 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times are shown as tSU(OPT) and tH(OPT), respectively. The device clock and SYSREF are referred to as internal in this diagram because the phase of the internal signals are aligned within the device and not to the external (applied) phase of the device clock or SYSREF. Sampled Input Signal Internal Unadjusted Device Clock Internal Calibrated Device Clock tTAD(SRC) Internal SYSREF tH(OPT) tCAL(SRC) SRC_EN (SPI register bit) tSU(OPT) Before calibration, device clock falling edge does not align with SYSREF rising edge Calibration enabled TAD_DONE (SPI register bit) After calibration, device clock falling edge aligns with SYSREF rising edge Calibration finished Figure 80. SYSREF Calibration Timing Diagram 56 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 When finished, the tAD adjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in the SYSREF calibration status register. After calibration, the system continues to use the calibrated tAD adjust setting for operation until the system is powered down. However, if desired, the SYSREF calibration can then be disabled and the tAD adjust setting can be fine-tuned according to the systems needs. Alternatively, the use of the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal tAD adjust setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and TAD_FINE) upon system startup. Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If background calibration is the desired use case, disable the background calibration when the SYSREF calibration is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock control register 0 must be set to 0 when using SYSREF calibration. SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the clock path to reduce aperture jitter (tAJ). 7.3.5 LVDS Digital Interface The ADC12DL3200 uses a low-voltage differential signaling (LVDS) interface to output the digital samples. This interface offers simplicity in its implementation compared to serialized interfaces and provides low latency for latency-sensitive applications. The interface uses up to 48 data pairs, four DDR clocks, and four strobe signals arranged in four 12-bit data buses. Strobe signals simplify synchronization across buses and synchronization between multiple devices. The strobe can be generated internally or mirrored from the TMSTP± or SYSREF± inputs. Flexible strobe configurations allow tradeoffs in reliability or number of LVDS pairs and the on-the-fly use of strobe is SPI or pin selectable. Digital interface scrambling is available to avoid spurious noise generated by the digital interface from leaking into the ADC samples. The receiver must undo the scrambling operation to extract the proper digital samples (see the Scrambling section) when used. Scrambling is optional. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes The ADC12DL3200 is able to achieve multi-device synchronization through deterministic latency across the LVDS interface. First, SYSREF is issued to all devices as a known timing reference for synchronization. SYSREF resets internal clock dividers and the strobe generation block within the ADC12DL3200. The ADC12DL3200 issues strobe signals across each bus of the interface to provide timing information to the receiver. The receiver uses this timing information to achieve fixed latency and for alignment among multiple ADC12DL3200 devices. The strobe generator block provides internal generation of a repeating strobe signal to reflect the end of a data frame. The generated strobe can be sent across the interface using a dedicated LVDS pair (DxSTR±) or as a replacement of the sample LSB with the strobe. Strobe generation can be controlled by the SYNC signal through the SPI or by using the SYNCSE or TMSTP± inputs (see SYNC_SEL in the LCTRL register). In all modes, the strobe output can be treated as a data pair with the same timing as the data outputs (Dx[11:0]±) that is sourcesynchronous with the associated data clock (DxCLK±). The strobe generator sets the last unit interval (UI) of a frame high to signal the end of a frame. Frame length is programmable through the LFRAME register. The SYSREF input marks the start of a frame and, if run periodically, then the SYSREF period must be an integer number of frames long. 7.3.5.1.1 Dedicated Strobe Pins Dedicated strobe pins are recommended for applications with robust requirements. Each LVDS bus has a dedicated strobe (DxSTR±), up to four total, which is source synchronous to its associated data clock (DxCLK±). The strobe can run continuously or can be enabled and disabled as needed. When enabled, this mode allows the data bus to still send all 12 bits of the digital samples for highest performance. The tradeoff is that more pins are needed, two per LVDS bus, for up to eight total pins when operating in DMUX-by-2 mode. Table 6 describes the strobe output. The SYNC signal is not required to output the dedicated strobe signal. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 57 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Table 6. Strobe Output for Dedicated Strobe Pins 1 FRAME (LFRAME = 0x08) FRAME SAMPLE NUMBER (UI) 0 1 2 3 4 5 6 7 Dx[11:0] S0[11:0] S1[11:0] S2[11:0] S3[11:0] S4[11:0] S5[11:0] S6[11:0] S7[11:0] DxSTR 0 0 0 0 0 0 0 1 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins In four LVDS output modes (see Table 11), the data clock (DxCLK±) and strobe (DxSTR±) for LVDS buses C and D can be disabled to reduce the total number of LVDS pins by eight. In this mode, the LVDS bus A data clock (DACLK±) and strobe (DASTR±) can be used with the data from bus C and the same signals for bus B can be used for LVDS bus D. The tradeoff is that digital interface timing may become more difficult. See the Reducing the Number of Strobes and Reducing the Number of Data Clocks sections. 7.3.5.1.3 LSB Replacement With a Strobe The strobe signals can also be output over the LSB of the digital sample for each LVDS bus. During transmission of the strobe the LSB of the sample is replaced by the strobe signal and, therefore, the digital sample is only 11 bits wide resulting in a small loss in ENOB. When the strobe is disabled, all 12 bits of the digital sample are sent across the interface for full performance. The strobe can be enabled periodically, allowing a tradeoff in ENOB and robustness and reducing the interface width. Enable this mode by setting SYNC_PAT in the PAT_SEL register to 0x2. Transmission of the strobe is controlled by the source selected by SYNC_SEL in the LCTRL register. The SYNCSE pin controls transmission of the strobe by default. Table 7 describes the strobe output when the LSB is replaced with the strobe signal data when SYNC is asserted. Table 8 describes the strobe output when the active pattern is used (SYNC de-asserted). Table 7. Sync Pattern Output for LSB Replacement With Strobe (SYNC Asserted) 1 FRAME (LFRAME = 0x08) FRAME SAMPLE NUMBER (UI) 0 1 2 3 4 5 6 7 Dx[11:1] S0[11:1] S1[11:1] S2[11:1] S3[11:1] S4[11:1] S5[11:1] S6[11:1] S7[11:1] Dx0 (LSB) 0 0 0 0 0 0 0 1 Table 8. Active Pattern Output for LSB Replacement With Strobe (SYNC De-Asserted) 1 FRAME (LFRAME = 0x08) FRAME SAMPLE NUMBER (UI) 0 1 2 3 4 5 6 7 Dx[11:1] S0[11:1] S1[11:1] S2[11:1] S3[11:1] S4[11:1] S5[11:1] S6[11:1] S7[11:1] Dx0 (LSB) S0[0] S1[0] S2[0] S3[0] S4[0] S5[0] S6[0] S7[0] 7.3.5.1.4 Strobe Over All Data Pairs The strobe signal can also be output over all LVDS lanes. During transmission of the strobe, the entire sample is replaced by the strobe signal and therefore the sampled data are lost. When the strobe is disabled, all 12 bits of the digital sample are sent across the interface for full performance. The strobe can be enabled periodically to ensure synchronization is maintained only if loss of digital samples is allowed by the application. Enable this mode by setting SYNC_PAT in the PAT_SEL register to 0x3. Transmission of the strobe pattern is controlled by the source selected by SYNC_SEL in the LCTRL register. The SYNCSE pin controls transmission of the strobe pattern by default. Table 9 describes the strobe output when the strobe signal is output over all data pairs when SYNC is asserted. Table 10 describes the strobe output when the active pattern is used (SYNC de-asserted). Table 9. Sync Pattern Output for Strobe Over All Data Pairs (SYNC Asserted) 58 1 FRAME (LFRAME = 0x08) FRAME SAMPLE NUMBER (UI) 0 1 2 3 4 5 6 7 Dx[11:0] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0xFFF DxSTR (if enabled) 0 0 0 0 0 0 0 1 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Table 10. Active Pattern Output for Strobe Over All Data Pairs (SYNC De-Asserted) 1 FRAME (LFRAME = 0x08) FRAME SAMPLE NUMBER (UI) 0 1 2 3 4 5 6 7 Dx[11:0] S0[11:0] S1[11:0] S2[11:0] S3[11:0] S4[11:0] S5[11:0] S6[11:0] S7[11:0] DxSTR (if enabled) 0 0 0 0 0 0 0 1 7.3.6 Alarm Monitoring Built-in alarms are available to monitor internal events. Two types of alarms and upsets are detected by this feature: 1. SYSREF caused internal clocks to be realigned 2. An upset that affects the internal clocks When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the host system writes a 1 to clear it. If the alarm type is not masked (see the ALM_MASK register), then the alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output that goes high when an alarm occurs. See CAL_STATUS_SEL in the CAL_PIN_CFG register. 7.3.6.1 Clock Upset Detection The CLK_ALM register bit indicates if the internal clocks may have been upset. The clocks in channel A are continuously compared to channel B. If these clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to function properly, follow this usage model: 1. 2. 3. 4. 5. 6. Program LVDS_EN = 0 Ensure the device is configured to use both channels (PD_ACH = 0, PD_BCH = 0) Program LVDS_EN = 1 Write CLK_ALM = 1 to clear CLK_ALM Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured When exiting global power-down (via MODE in the DEVICE_CONFIG register or via the PD pin), the CLK_ALM status bit can be set and must be cleared by writing a 1 to CLK_ALM 7.3.7 Temperature Monitoring Diode A built-in thermal monitoring diode is available on the TDIODE+ and TDIODE– pins. This diode facilitates temperature monitoring and characterization of the device in higher ambient temperature environments. Although the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the diode voltage slope provided in the Electrical Characteristics: DC Specifications table. Perform offset measurement with the device unpowered or with the PD pin asserted to minimize device self-heating. Recommended monitoring devices include the LM95233 device and similar remote-diode temperature monitoring products from Texas Instruments. 7.3.8 Analog Reference Voltage The reference voltage for the ADC12DL3200 is derived from an internal band-gap reference. A buffered version of the reference voltage is available at the BG pin for convenience. This output has an output-current capability of ±100 µA. The BG output must be buffered if more current is required. No provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register settings. In unique cases, the VA11 supply voltage can act as the reference voltage by setting BG_BYPASS (see the internal reference bypass register). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 59 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.4 Device Functional Modes The ADC12DL3200 can be configured to operate in a number of functional modes. These modes are described in this section. 7.4.1 Dual-Channel Mode (Non-DES Mode) The ADC12DL3200 can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency (fS = fCLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs for each channel in this mode. This mode is chosen simply by setting DES_EN to 0. The analog inputs can be swapped by setting DUAL_INPUT (see the input mux control register). 7.4.2 Internal Dither Modes Dither can be disabled by setting ADC_DITH_EN to 0 in the ADC_DITH register, which can result in a slight improvement in SNR. The amount of dither can be increased by setting ADC_DITH_AMP to 1. The increased dither can result in further spurious improvements, but can also result in a reduction in SNR. Certain dither values, caused by device-to-device variations, can result in rounding errors that can either reduce SNR or reduce fixed spur performance (DC, fS / 4, and fS / 2 spurs). The choice of tradeoff can be made by setting ADC_DITH_ERR to 0 to degrade SNR and 1 to degrade the DC, fS / 4 (single-channel mode only), and fS / 2 spurs. 7.4.3 Single-Channel Mode (DES Mode) The ADC12DL3200 can also be used as a single-channel ADC where the sampling rate is equal to two times the clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by setting DES_EN to 1. Either analog input, INA± or INB±, can serve as the input to the ADC. ADC trim settings are automatically adjusted based on the chosen input. The analog input can be selected using SINGLE_INPUT (see the input mux control register). 7.4.4 LVDS Output Driver Modes The LVDS output drivers can be configured for various swings, terminations and output common-mode levels to meet the needs of different receivers. The swing can be adjusted between high swing (default) and low swing mode to save power by setting LVDS_SWING to 0x1. Further power savings can be gained by choosing the high-Z termination mode by setting LVDS_SWING to 0x3. Only use high-Z termination mode with short transmission lines and for receivers with high-Z termination. The common-mode voltage is adjusted by adjusting the VLVDS supply voltage. The output common-mode voltage roughly tracks the VLVDS supply voltage by VOCM = VLVDS – 0.6 V. 60 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Device Functional Modes (continued) 7.4.5 LVDS Output Modes The LVDS output buses can be configured to demux the output data from each ADC channel by one or two by setting the LDEMUX parameter. When a demux-by-2 option is selected (LDEMUX = 1), the number of output strobes and data clocks can be reduced by using LCS_EN. The two channels of the ADC12DL3200 can be interleaved together to achieve double the sample rate (that is, single-channel mode) by setting DES_EN to 1. Table 11 lists the available interface and configuration modes. When the LSB replacement with strobe option is used (SYNC_PAT = 0x2), the strobe column of Table 11 can be ignored and replaced with 0 because all dedicated strobe outputs can be disabled. Table 11. LVDS Output Modes DES_EN USER-PROGRAMMED VALUES LDEMUX LALIGNED DATA PAIRS DATA CLOCKS STROBES ALLOWED fS RANGE (MSPS) ALLOWED fCLK RANGE (MHz) TIMING DIAGRAM Single channel, 2 LVDS buses, staggered data 1 0 0 24 2 2 1600–3200 800–1600 Figure 4 Single channel, 2 LVDS buses, aligned data 1 0 1 24 2 2 1600–3200 800–1600 Figure 5 Single channel, 4 LVDS buses, staggered data 1 1 0 48 4 4 1600–6400 800–3200 Figure 6 Single channel, 4 LVDS buses, aligned data 1 1 1 48 4 4 1600–6400 800–3200 Figure 7 Dual channel, 2 LVDS buses 0 0 0 or 1 24 2 2 800–1600 800–1600 Figure 1 Dual channel, 4 LVDS buses, staggered data 0 1 0 48 4 4 800–3200 800–3200 Figure 2 Dual channel, 4 LVDS buses, aligned data 0 1 1 48 4 4 800–3200 800–3200 Figure 3 LVDS OUTPUT MODE 7.4.5.1 Staggered Output Mode Setting LALIGNED to 0 results in the LVDS output buses being staggered in time. Staggering the output buses causes an LVDS output switching event to occur at each sampling instance and may result in better spurious performance than what is described in the Aligned Output Mode section. Table 11 provides links to the timing diagrams for staggered output mode. 7.4.5.2 Aligned Output Mode Setting LALIGNED to 1 results in the LVDS outputs buses being aligned in time, meaning that all buses switch at the same time. The switching instance is a sub-harmonic of the sampling clock and may result in additional spurs in the output spectrum as compared to the Staggered Output Mode section. Table 11 provides links to the timing diagrams for aligned output mode. 7.4.5.3 Reducing the Number of Strobes One strobe is provided for each LVDS bus; however, the number of output strobes can either be reduced or the strobes can be disabled altogether. Typical use cases for reduced strobes include sharing a single strobe among multiple buses or implementing a receiver that does not have a FIFO that needs to be synchronized by the strobes. STBx_EN in the LCS_EN register can be used to disable any unused strobe outputs. 7.4.5.4 Reducing the Number of Data Clocks One data clock is provided for each LVDS bus; however, the number of data clocks used in the system can be reduced. The number of data clocks can be reduced if a data clock is shared among multiple buses, which can be applicable at lower data rates. DCLKx_EN in the LCS_EN register can be used to disable any unused data clock outputs. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 61 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.4.5.5 Scrambling The LVDS outputs can be scrambled in order to reduce spectral peaks in the output data, especially for repeating patterns. Spectral peaks can couple back to the ADC analog input and result in degraded noise or spurious performance in the ADC output data. Enable scrambling by setting SCR in the LCTRL register. The scrambler does not require any memory (only uses the current sample) and uses simple XOR operations in order to minimize latency. Scrambling does require the two LSBs of each sample to be random (as is the case for ADC input thermal noise), but also works when the LSB is used as a strobe or timestamp. The scrambler is enabled by setting SCR in the LCTRL register to 1. The scrambling operation changes slightly depending on the LWIDTH parameter, as Table 12 to Table 15 describes. Each table also describes the descrambling operation that the receiving device must implement in order to recover the original samples. In Table 12 to Table 15, d[x] corresponds to bit x of the unscrambled digitized ADC sample at LVDS bus q (q = A, B, C, or D) before scrambling and y[k] corresponds to the scrambled bit k output from the interface over data pair Dqk±. Likewise, strobe is the unscrambled strobe signal at the LVDS bus q (q = A, B, C, or D) and strobe_y is the scrambled strobe output on data pair DqSTR±. The ⊕ symbol denotes the bitwise XOR operation. Table 12. Scrambling and Descrambling Operations (12-Bit Mode, LWIDTH = 0x0) SCRAMBLER DESCRAMBLER y[11] = d[11] ⊕ d[1] ⊕ d[0] d[11] = y[11] ⊕ y[0] y[10] = d[10] ⊕ d[1] ⊕ d[0] d[10] = y[10] ⊕ y[0] y[9] = d[9] ⊕ d[1] ⊕ d[0] d[9] = y[9] ⊕ y[0] y[8] = d[8] ⊕ d[1] ⊕ d[0] d[8] = y[8] ⊕ y[0] y[7] = d[7] ⊕ d[1] ⊕ d[0] d[7] = y[7] ⊕ y[0] y[6] = d[6] ⊕ d[1] ⊕ d[0] d[6] = y[6] ⊕ y[0] y[5] = d[5] ⊕ d[1] ⊕ d[0] d[5] = y[5] ⊕ y[0] y[4] = d[4] ⊕ d[1] ⊕ d[0] d[4] = y[4] ⊕ y[0] y[3] = d[3] ⊕ d[1] ⊕ d[0] d[3] = y[3] ⊕ y[0] y[2] = d[2] ⊕ d[1] ⊕ d[0] d[2] = y[2] ⊕ y[0] y[1] = d[1] d[1] = y[1] y[0] = d[0] ⊕ d[1] d[0] = y[0] ⊕ y[1] strobe_y = strobe ⊕ d[1] ⊕ d[0] strobe = strobe_y ⊕ y[0] Table 13. Scrambling and Descrambling Operations (11-Bit Mode, LWIDTH = 0x1) (1) 62 SCRAMBLER DESCRAMBLER y[11] = d[11] ⊕ d[2] ⊕ d[1] d[11] = y[11] ⊕ y[1] y[10] = d[10] ⊕ d[2] ⊕ d[1] d[10] = y[10] ⊕ y[1] y[9] = d[9] ⊕ d[2] ⊕ d[1] d[9] = y[9] ⊕ y[1] y[8] = d[8] ⊕ d[2] ⊕ d[1] d[8] = y[8] ⊕ y[1] y[7] = d[7] ⊕ d[2] ⊕ d[1] d[7] = y[7] ⊕ y[1] y[6] = d[6] ⊕ d[2] ⊕ d[1] d[6] = y[6] ⊕ y[1] y[5] = d[5] ⊕ d[2] ⊕ d[1] d[5] = y[5] ⊕ y[1] y[4] = d[4] ⊕ d[2] ⊕ d[1] d[4] = y[4] ⊕ y[1] y[3] = d[3] ⊕ d[2] ⊕ d[1] d[3] = y[3] ⊕ y[1] y[2] = d[2] d[2] = y[2] y[1] = d[2] ⊕ d[1] d[1] = y[2] ⊕ y[1] y[0] = d[2] ⊕ d[1] ⊕ d[0] (1) d[0] = y[1] ⊕ y[0] (1) strobe_y = strobe ⊕ d[1] ⊕ d[0] strobe = strobe_y ⊕ y[1] Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Table 14. Scrambling and Descrambling Operations (10-Bit Mode, LWIDTH = 0x2) SCRAMBLER DESCRAMBLER y[11] = d[11] ⊕ d[3] ⊕ d[2] d[11] = y[11] ⊕ y[2] y[10] = d[10] ⊕ d[3] ⊕ d[2] d[10] = y[10] ⊕ y[2] y[9] = d[9] ⊕ d[3] ⊕ d[2] d[9] = y[9] ⊕ y[2] y[8] = d[8] ⊕ d[3] ⊕ d[2] d[8] = y[8] ⊕ y[2] y[7] = d[7] ⊕ d[3] ⊕ d[2] d[7] = y[7] ⊕ y[2] y[6] = d[6] ⊕ d[3] ⊕ d[2] d[6] = y[6] ⊕ y[2] y[5] = d[5] ⊕ d[3] ⊕ d[2] d[5] = y[5] ⊕ y[2] y[4] = d[4] ⊕ d[3] ⊕ d[2] d[4] = y[4] ⊕ y[2] y[3] = d[3] d[3] = y[3] y[2] = d[2] ⊕ d[3] d[2] = y[2] ⊕ y[3] y[1] = 0 (not used) y[0] = d[0] ⊕ d[3] ⊕ d[2] d[1] = 0 (not used) (1) d[0] = y[0] ⊕ y[2] (1) strobe_y = strobe ⊕ d[3] ⊕ d[2] (1) strobe = strobe_y ⊕ y[2] Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1. Table 15. Scrambling and Descrambling Operations (8-Bit Mode, LWIDTH = 0x3) (1) SCRAMBLER DESCRAMBLER y[11] = d[11] ⊕ d[5] ⊕ d[4] d[11] = y[11] ⊕ y[4] y[10] = d[10] ⊕ d[5] ⊕ d[4] d[10] = y[10] ⊕ y[4] y[9] = d[9] ⊕ d[5] ⊕ d[4] d[9] = y[9] ⊕ y[4] y[8] = d[8] ⊕ d[5] ⊕ d[4] d[8] = y[8] ⊕ y[4] y[7] = d[7] ⊕ d[5] ⊕ d[4] d[7] = y[7] ⊕ y[4] y[6] = d[6] ⊕ d[5] ⊕ d[4] d[6] = y[6] ⊕ y[4] y[5] = d[5] d[5] = y[5] y[4] = d[4] ⊕ d[5] d[4] = y[4] ⊕ y[5] y[3] = 0 (not used) d[3] = 0 (not used) y[2] = 0 (not used) d[2] = 0 (not used) y[1] = 0 (not used) d[1] = 0 (not used) y[0] = d[0] ⊕ d[5] ⊕ d[4] (1) d[0] = y[0] ⊕ y[4] (1) strobe_y = strobe ⊕ d[5] ⊕ d[4] strobe = strobe_y ⊕ y[4] Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality A number of device test patterns are available. These modes insert known patterns into the device data path for assistance with system debug, development, or characterization. The test patterns can also be used during system power-up to synchronize the digital interface logic in the receiving device. Two patterns are available at any time, and are referred to as the active pattern and the sychronization pattern. Toggling between the two patterns is controlled by the source selected by SYNC_SEL in the LCTRL register. Selecting the active pattern or synchronization pattern is controlled by the SYNCSE pin by default. The pattern always changes state on a frame boundary (falling edge of the strobe). 7.4.5.6.1 Active Pattern The active pattern is chosen by setting ACT_PAT in the PAT_SEL register. The available active patterns are given below: • Digitized samples from the ADC (normal operation) • All LVDS lanes output the user-defined pattern (see the User-Defined Test Pattern section) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 63 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.4.5.6.2 Synchronization Pattern The synchronization pattern is chosen by setting SYNC_PAT in the PAT_SEL register. The available synchronization patterns are given below: • All LVDS lanes transmit the user-defined pattern (see the User-Defined Test Pattern section) • Frame strobe is transmitted on the LSB of the digital samples of each active LVDS bus. The digitized samples (ADC output data) are still output on the other LVDS lanes. • Frame strobe is transmitted on all active LVDS data lanes 7.4.5.6.3 User-Defined Test Pattern A user-defined test pattern mode allows the user to define a pattern to meet various system needs. Example patterns included strobe patterns to look for inter-symbol interference issues, single-bit patterns to verify TX to RX lane connections, and multi-bit patterns to verify time alignment. The pattern is up to eight samples long and is programmed using the UPAT0 through UPAT7 registers. The user pattern repeats at the beginning of each frame. If the frame length is less than eight samples than the user pattern is truncated. If the frame length is greater than eight samples then the user pattern repeats until the end of the frame. Additionally, there are controls to invert specific bits of the user-defined pattern for each of the LVDS buses in order to allow a unique pattern on each bus. UPAT_INV_x (x = A, B, C, or D) in the UPAT_CTRL register, as shown in Table 16, inverts the specified bit in each LVDS bus when set to 1. The inversion is independent of the other buses. Table 16. UPAT_INV_x Control Definition REGISTER CONTROL LVDS BUS AFFECTED LVDS BUS BIT INVERTED BUS INVERSION MASK UPAT_INV_A A 8 0001 0000 0000 UPAT_INV_B B 9 0010 0000 0000 UPAT_INV_C C 10 0100 0000 0000 UPAT_INV_D D 11 1000 0000 0000 A predefined pattern can also be selected by setting LANE_PAT in the UPAT_CTRL register to 1. LANE_PAT automatically overrides the programmed user pattern. LANE_PAT is a fixed eight sample sequence output on each LVDS bus. The pattern is 0x000, 0xFFF, 0x000, 0x000, 0x000, 0xFFF, 0xFFF, and 0xFFF. The repetition rules regarding frame length defined for the user pattern apply to the lane pattern as well. 7.4.6 Power-Down Modes The PD input pin allows ADC12DL3200 devices to be entirely powered down. Power-down can also be controlled by MODE (see the device configuration register). The LVDS data output drivers are disabled when PD is high. When the device returns to normal operation, the LVDS interface must be re-established, which results in the ADC data pipeline containing meaningless information so the system must wait a sufficient time for the data to be flushed. 7.4.7 Calibration Modes and Trimming The ADC12DL3200 has two calibration modes available: foreground calibration and background calibration. When foreground calibration is initiated the ADCs are automatically taken offline and the output data become mid-code (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC core to take its place. Additional offset calibration features are available in both foreground and background calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user system. The ADC12DL3200 consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples INA± and ADC B samples INB± in dual-channel mode and both ADC A and ADC B sample INA± (or INB±) in single-channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in periodically for ADC A and ADC B so that they can be calibrated without disrupting operation. 64 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Figure 81 shows a diagram of the calibration system including labeling of the banks that make up each ADC core. When calibration is performed the linearity, gain, and offset voltage for each bank are calibrated to an internally generated calibration signal. The analog inputs can be driven during calibration, both foreground and background, except that when offset calibration (see CAL_OS and CAL_BGOS in the CAL_CFG0 register) is used there must be no signals (or aliased signals) near DC for proper estimation of the offset (see the Offset Calibration section). ADC A Interleave Bank 0 MUX INA+ Calibration Signal INA± Bank 1 Calibration Engine MUX ADC A Output ADC C Interleave Bank 2 MUX Calibration Signal Calibration Engine Bank 3 Calibration Engine INB+ ADC B MUX ADC B Output Bank 4 Interleave INB± MUX Calibration Signal Calibration Engine Bank 5 Calibration Engine Figure 81. ADC12DL3200 Calibration System Block Diagram In addition to calibration, a number of ADC parameters are user-controllable to provide trimming for optimal performance. These parameters include input offset voltage, ADC gain, interleaving timing, and input termination resistance. The default trim values are programmed at the factory to unique values for each device that are determined to be optimal at the test system operating conditions. The factory-programmed values can be read from the trim registers and adjusted as desired. The register fields that control the trimming are labeled according to the input that is being sampled (INA± or INB±), the bank that is being trimmed, or the ADC core that is being trimmed. Trim values are not expected to change as operating conditions change, however optimal performance can be obtained by doing so. Any custom trimming must be done on a per device basis because of process variations, meaning that there is no global optimal setting for all parts. See the Trimming section for information about the available trim parameters and associated registers. 7.4.7.1 Foreground Calibration Mode Foreground calibration requires the ADC to stop converting the analog input signals during the procedure. Foreground calibration always runs on power-up and a sufficient period of time must elapse before programming the device to ensure that the calibration is finished. Foreground calibration can be initiated by triggering the calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (see the calibration software trigger register) and is chosen by setting CAL_TRIG_EN (see the calibration pin configuration register). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 65 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.4.7.2 Background Calibration Mode Background calibration mode allows the ADC to continuously operate, with no interruption of data. This continuous operation is accomplished by activating an extra ADC core that is calibrated and then takes over operation for one of the other previously active ADC cores. When that ADC core is taken off-line, that ADC is calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously, ensuring the ADC cores always provide the optimum performance regardless of system operating condition changes. Because of the additional active ADC core, background calibration mode has increased power consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power consumption in comparison with the standard background calibration mode. Background calibration can be enabled by setting CAL_BG (see the calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and CAL_SOFT_TRIG must be set to 1. Great care has been taken to minimize effects on converted data while the core switching process occurs; however, small brief glitches can still occur on the converter data when the cores are swapped. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores. Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the lowpower background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is an increase in power consumption during the ADC core calibration. The power consumption roughly alternates between the power consumption in foreground calibration when the spare ADC core is sleeping to the power consumption in background calibration when the spare ADC is being calibrated. Design the power-supply network to handle the transient power requirements for this mode. 7.4.8 Offset Calibration Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores; however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single-channel mode uncalibrated input buffer offsets can result in a fixed spur at fS / 2. A separate calibration is provided to correct the input buffer offsets. There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration the offsets, requiring the system to ensure this condition during normal operation or have the ability to mute the input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled via CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for operating condition changes. When CAL_BGOS is set, the system must ensure that there are no DC or near DC signals or aliased signals that fall at or near DC during normal operation. Offset calibration can be performed as a foreground operation when using background calibration by setting CAL_OS to 1 before setting CAL_EN, but does not correct for variations as operating conditions change. The offset calibration correction uses the input offset voltage trim registers (see the Trimming section) to correct the offset and therefore must not be written by the user when offset calibration is used. The calibrated values can be read by reading the OADJ_x_FG0_VINy and OADJ_x_FG90_VINy registers, where x is the ADC core (A or B) and y is the input (INA± or INB±), after calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset calibration (CAL_OS = 1) and do not read the values when using background offset calibration (CAL_BGOS = 1). 66 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.4.9 Trimming Table 17 lists the parameters that can be trimmed and the associated registers. Manual trimming is only allowed in foreground calibration mode. Table 17. Trim Register Descriptions TRIM PARAMETER Band-gap reference Input termination resistance TRIM REGISTER BG_TRIM RTRIM_x, where x = A for INA± or B for INB±) NOTES Measurement on the BG output pin. The device must be powered on with a clock applied. A different trim value is allowed for each ADC core (A or B) to allow trimming of the offsets as operating conditions change. OADJ_A_FG90_VINy is used to trim the offsets of ADC A in single-channel mode. Input offset voltage OADJ_x_FG0_VINy and OADJ_A_FG90_VINy, where x = ADC core (A or B) and y = A for INA± or B for INB± INA± and INB± gain GAIN_TRIM_x, where x = A for INA± or B for INB± Set FS_RANGE_A and FS_RANGE_B to default values before trimming the input. Use FS_RANGE_A and FS_RANGE_B to adjust the full-scale input voltage. GAIN_Bx, where x = 0, 1, 2, or 3 Trims the gain of the individual ADC banks to improve gain matching between ADC cores. INA± and INB± full-scale input voltage FS_RANGE_x, where x = A for INA± or B for INB± Full-scale input voltage adjustment for each input. The default value is effected by GAIN_TRIM_x (x = A or B). Trim GAIN_TRIM_x with FS_RANGE_x set to the default value. FS_RANGE_x can then be used to trim the full-scale input voltage. Intra-ADC core timing (bank timing) Bx_TIME_y, where x = bank number (0–5) and y = 0° or –90° clock phase Trims the timing between the two banks of an ADC core (ADC A or B) for two clock phases, either 0° or –90°. The –90° clock phase is used by ADC A in single-channel mode only. TADJ_A, TADJ_B The suffix letter (A or B) indicates the ADC core that is being trimmed. Bank gain trim Inter-ADC core timing (dual-channel mode) Inter-ADC core timing (single-channel mode) TADJ_A_FG90, TADJ_B_FG0 The middle letter (A or B) indicates the ADC core that is being trimmed. The suffix of 0 or 90 indicates the clock phase applied to the ADC core. 0 indicates a 0° clock and is sampling in-phase with the clock input (applies to ADC B). 90 indicates a –90° clock and therefore is sampling out-of-phase with the clock input (applies to ADC A). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 67 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.5 Programming 7.5.1 Using the Serial Interface The serial interface is accessed using the following four pins: serial clock (SCLK), serial data input (SDI), serial data output (SDO), and serial-interface chip-select (SCS). Register access is enabled through the SCS pin. 7.5.1.1 SCS This signal must be asserted low to access a register through the serial interface. Setup and hold times with respect to the SCLK must be followed. 7.5.1.2 SCLK Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement. 7.5.1.3 SDI Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write (R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with respect to the SCLK must be followed (see the Timing Requirements table). 7.5.1.4 SDO The SDO signal provides the output data requested by a read command. This output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles. Figure 82 shows that each register access consists of 24 bits. The first bit is high for a read and low for a write. The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored, and, during this time, the SDO outputs the data from the addressed register. Figure 82 shows the serial protocol details. Single Register Access SCS 1 8 16 17 24 SCLK Command Field SDI R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 Data Field A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Data Field SDO (read mode) High Z D7 D6 D5 D4 D3 D2 D1 D0 High Z Figure 82. Serial Interface Protocol: Single Read/Write Operation 68 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Programming (continued) 7.5.1.5 Streaming Mode The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends (increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit in the USR0 register. Figure 83 shows the streaming mode transaction details. Multiple Register Access SCS 8 1 16 17 24 25 32 SCLK Command Field SDI R/W A14 A13 A12 A1 1 A10 A9 A8 A7 Data Field (write mode) Data Field (write mode) A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 High Z D7 D6 D5 D4 D3 D2 D1 D0 Data Field Data Field SDO (read mode) D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 High Z Figure 83. Serial Interface Protocol: Streaming Read/Write Operation See the Register Maps section for detailed information regarding the registers. NOTE The serial interface must not be accessed during calibration of the ADC. Accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. Writing or reading the serial registers also reduces dynamic performance of the ADC for the duration of the register access time. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 69 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6 Register Maps 7.6.1 SPI_REGISTER_MAP Registers Table 18 lists the memory-mapped registers for the SPI_REGISTER_MAP. All register offset addresses not listed in Table 18 are considered reserved locations and the register contents are not to be modified. Table 18. SPI_REGISTER_MAP Registers Address 70 Acronym Register Name 0x000 CONFIG_A Configuration A (Default: 0x30) Section Go 0x002 DEVICE_CONFIG Device Configuration (Default: 0x00) Go 0x003 CHIP_TYPE Chip Type (Default: 0x03) Go 0x004-0x005 CHIP_ID Chip Identification Go 0x00C-0x00D VENDOR_ID Vendor Identification (Default: 0x0451) Go 0x010 USR0 User SPI Configuration (Default: 0x00) Go 0x029 CLK_CTRL0 Clock Control 0 (Default: 0x00) Go 0x02A CLK_CTRL1 Clock Control 1 (Default: 0x00) Go 0x02C-0x02E SYSREF_POS SYSREF Capture Position (Read-only status) Go 0x030-0x031 FS_RANGE_A Full-Scale Voltage for INA± (Default: 0xA000) Go 0x032-0x033 FS_RANGE_B Full-Scale Voltage for INB± (Default: 0xA000) Go 0x038 BG_BYPASS Band-Gap Bypass (Default: 0x00) Go 0x03B SYNC_CTRL SYNC_SE/TIMESTAMP Control (Default: 0x00) Go 0x048 LVDS_SWING LVDS Swing Mode (Default: 0x00) Go 0x060 INPUT_MUX Input Mux Control (Default: 0x01) Go 0x061 CAL_EN Calibration Enable (Default: 0x01) Go 0x062 CAL_CFG0 Calibration Configuration 0 (Default: 0x01) Go 0x06A CAL_STATUS Calibration Status (Default: undefined; read-only) Go 0x06B CAL_PIN_CFG Calibration Pin Configuration (Default: 0x00) Go 0x06C CAL_SOFT_TRIG Calibration Software Trigger (Default: 0x01) Go 0x06E CAL_LP Low-Power Background Calibration (Default: 0x88) Go 0x070 CAL_DATA_EN Calibration Data Enable (Default: 0x00) Go 0x071 CAL_DATA Calibration Data (Default: undefined) Go 0x07A GAIN_TRIM_A Gain DAC Trim A (Default from fuse ROM) Go 0x07B GAIN_TRIM_B Gain DAC Trim B (Default from fuse ROM) Go 0x07C BG_TRIM Band-Gap Trim (Default from fuse ROM) Go 0x07E RTRIM_A Resistor TRIM for INA± (Default from fuse ROM) Go 0x07F RTRIM_B Resistor TRIM for INB± (Default from fuse ROM) Go 0x09D ADC_DITH ADC Dither register (Default: 0x01) Go 0x102 B0_TIME_0 Time Adjustment for Bank 0 (0° clock) (Default from fuse ROM) Go 0x103 B0_TIME_90 Time Adjustment for Bank 0 (–90° clock) (Default from fuse ROM) Go 0x112 B1_TIME_0 Time Adjustment for Bank 1 (0° clock) (Default from fuse ROM) Go 0x113 B1_TIME_90 Time Adjustment for Bank 1 (–90° clock) (Default from fuse ROM) Go 0x142 B4_TIME_0 Time Adjustment for Bank 4 (0° clock) (Default from fuse ROM) Go 0x152 B5_TIME_0 Time Adjustment for Bank 5 (0° clock) (Default from fuse ROM) Go 0x160 LSB_CTRL LSB Control Bit Output (Default: 0x00) Go 0x161 LSB_SEL LSB Control Bit Position (Default: 0x00) Go 0x180-0x181 UPAT0 User-Defined Pattern (Sample 0; default: 0x0000) Go 0x182-0x183 UPAT1 User-Defined Pattern (Sample 1; default: 0x0FFF; same format as UPAT0) Go 0x184-0x185 UPAT2 User-Defined Pattern (Sample 2; default: 0x0000; same format as UPAT0) Go 0x186-0x187 UPAT3 User-Defined Pattern (Sample 3; default: 0x0FFF; same format as UPAT0) Go 0x188-0x189 UPAT4 User-Defined Pattern (Sample 4; default: 0x0000; same format as UPAT0) Go Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Table 18. SPI_REGISTER_MAP Registers (continued) Acronym Register Name 0x18A-0x18B Address UPAT5 User-Defined Pattern (Sample 5; default: 0x0FFF; same format as UPAT0) Section Go 0x18C-0x18D UPAT6 User-Defined Pattern (Sample 6; default: 0x0000; same format as UPAT0) Go 0x18E-0x18F UPAT7 User-Defined Pattern (Sample 7; default: 0x0FFF; same format as UPAT0) Go 0x190 UPAT_CTRL User-Defined Pattern Control (Default: 0x1E) Go 0x200 LVDS_EN LVDS Subsystem Enable (Default: 0x01) Go 0x201 LMODE LVDS Mode (Default: 0x01) Go 0x202 LFRAME LVDS Frame Length (Default: 0x80; 128 decimal) Go 0x203 LSYNC_N LVDS Manual Sync Request (Default: 0x01) Go 0x204 LCTRL LVDS Control (Default: 0x02) Go 0x205 PAT_SEL LVDS Pattern Control (Default: 0x02) Go 0x206 LCS_EN LVDS Clock and Strobe Enables (Default: 0xFF) Go 0x208 LVDS_STATUS System Status Register Go 0x209 PD_CH ADC Channel Power-Down (Default: 0x00) Go 0x211 OVR_T0 Overrange Threshold 0 (Default: 0xF2) Go 0x212 OVR_T1 Overrange Threshold 1 (Default: 0xAB) Go 0x213 OVR_CFG Overrange Enable/Hold Off (Default: 0x07) Go 0x297 SPIN_ID Chip Spin Identifier (Default from fuse ROM; read-only) Go 0x2B0 SRC_EN SYSREF Calibration Enable (Default: 0x00) Go 0x2B1 SRC_CFG SYSREF Calibration Configuration (Default: 0x05) Go 0x2B2-0x2B4 SRC_STATUS SYSREF Calibration Status (Default: undefined; read-only) Go 0x2B5-0x2B7 TAD CLK± Timing Adjust (Default: 0x00) Go 0x2B8 TAD_RAMP CLK± Timing Adjust Ramp Control (Default: 0x00) Go 0x2C0 ALARM Alarm Interrupt (Read-only) Go 0x2C1 ALM_STATUS Alarm Status (Default: 0x05; write to clear) Go 0x2C2 ALM_MASK Alarm Mask Register (Default: 0x05) Go 0x310 TADJ_A Timing Adjust for A-ADC, Dual Mode (Default from fuse ROM) Go 0x313 TADJ_B Timing Adjust for B-ADC, Dual Mode (Default from fuse ROM) Go 0x314 TADJ_A_FG90_VINA Timing Adjust for A-ADC, DES, Foreground Calibration, INA± (Default from fuse ROM) Go 0x315 TADJ_B_FG0_VINA Timing Adjust for B-ADC, DES, Foreground Calibration, INA± (Default from fuse ROM) Go 0x31A TADJ_A_FG90_VINB Timing Adjust for A-ADC, DES, Foreground Calibration, INB± (Default from fuse ROM) Go 0x31B TADJ_B_FG0_VINB Timing Adjust for B-ADC, DES, Foreground Calibration, INB± (Default from fuse ROM) Go 0x344-0x345 OADJ_A_FG0_VINA Offset Adjustment for A-ADC, Foreground Calibration, 0° Clock, INA± (Default from fuse ROM) Go 0x346-0x347 OADJ_A_FG0_VINB Offset Adjustment for A-ADC, Foreground Calibration, 0° Clock, INB± (Default from fuse ROM) Go 0x348-0x349 OADJ_A_FG90_VINA Offset Adjustment for A-ADC, Foreground Calibration, 90° Clock, INA± (Default from fuse ROM) Go 0x34A-0x34B OADJ_A_FG90_VINB Offset Adjustment for A-ADC, Foreground Calibration, 90° Clock, INB± (Default from fuse ROM) Go 0x34C-0x34D OADJ_B_FG0_VINA Offset Adjustment for B-ADC, Foreground Calibration, INA± (Default from fuse ROM) Go 0x34E-0x34F OADJ_B_FG0_VINB Offset Adjustment for B-ADC, Foreground Calibration, INB± (Default from fuse ROM) Go Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 71 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Table 18. SPI_REGISTER_MAP Registers (continued) Address Acronym Register Name 0x360 GAIN_B0 Fine Gain Adjust for Bank 0 (Default from fuse ROM) Section Go 0x361 GAIN_B1 Fine Gain Adjust for Bank 1 (Default from fuse ROM) Go 0x364 GAIN_B4 Fine Gain Adjust for Bank 4 (Default from fuse ROM) Go 0x365 GAIN_B5 Fine Gain Adjust for Bank 5 (Default from fuse ROM) Go Complex bit access types are encoded to fit into small table cells. Table 19 shows the codes that are used for access types in this section. Table 19. SPI_REGISTER_MAP Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n 72 Value after reset or the default value Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.1 CONFIG_A Register (Address = 0x000) [reset = 0x30] CONFIG_A is shown in Figure 84 and described in Table 20. Return to Summary Table. Configuration A register (default: 0x30). This register controls device reset and SPI interface parameters. Figure 84. CONFIG_A Register 7 SOFT_RESET R/W-0x0 6 RESERVED R/W-0x0 5 ASCEND R/W-0x1 4 SDO_ACTIVE R-0x1 3 2 1 0 RESERVED R/W-0x0 Table 20. CONFIG_A Register Field Descriptions Bit Field Type Reset Description 7 SOFT_RESET R/W 0x0 Setting this bit causes a full reset of the device and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the device may take up to 750 ns to reset. During this time, do not perform any SPI transactions. 6 RESERVED R/W 0x0 Reserved 5 ASCEND R/W 0x1 0 : Address is decremented during streaming reads or writes 1 : Address is incremented during streaming reads or writes (default) 4 SDO_ACTIVE R 0x1 Always returns 1. Always use SDO for SPI reads. No SDIO mode is supported. RESERVED R/W 0x0 Reserved 3-0 7.6.1.2 DEVICE_CONFIG Register (Address = 0x002) [reset = 0x00] DEVICE_CONFIG is shown in Figure 85 and described in Table 21. Return to Summary Table. Device Configuration register (default: 0x00). This device controls the power-down of the device. Figure 85. DEVICE_CONFIG Register 7 6 5 4 3 2 1 RESERVED R/W-0x0 0 MODE R/W-0x0 Table 21. DEVICE_CONFIG Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0x0 Reserved 1-0 MODE R/W 0x0 0 1 2 3 : : : : Normal operation (default) Reserved Reserved Power-down Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 73 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.3 CHIP_TYPE Register (Address = 0x003) [reset = 0x03] CHIP_TYPE is shown in Figure 86 and described in Table 22. Return to Summary Table. Chip Type register (default: 0x03). This register returns the chip type. Figure 86. CHIP_TYPE Register 7 6 5 4 3 2 RESERVED R/W-0x0 1 0 CHIP_TYPE R-0x3 Table 22. CHIP_TYPE Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0x0 Reserved 3-0 CHIP_TYPE R 0x3 Always returns 0x3, indicating that the device is a high-speed ADC. 7.6.1.4 CHIP_ID Register (Address = 0x004) [reset = 0x0022] CHIP_ID is shown in Figure 87 and described in Table 23. Return to Summary Table. Chip Identification register (default: 0x0022). This register returns the chip identification number. Figure 87. CHIP_ID Register 15 14 13 12 11 10 9 8 7 CHIP_ID R-0x0022 6 5 4 3 2 1 0 Table 23. CHIP_ID Register Field Descriptions Bit 15-0 Field Type Reset Description CHIP_ID R 0x0022 Returns 0x0022, indicating the device is an ADC12DL3200. 7.6.1.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0451] VENDOR_ID is shown in Figure 88 and described in Table 24. Return to Summary Table. Vendor Identification register (default = 0x0451). This register returns the vendor identification number. Figure 88. VENDOR_ID Register 15 14 13 12 11 10 9 8 7 VENDOR_ID R-0x0451 6 5 4 3 2 1 0 Table 24. VENDOR_ID Register Field Descriptions Bit 15-0 74 Field Type Reset Description VENDOR_ID R 0x0451 Always returns 0x0451 (vendor ID for Texas Instruments). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.6 USR0 Register (Address = 0x010) [reset = 0x00] USR0 is shown in Figure 89 and described in Table 25. Return to Summary Table. User SPI Configuration register (default: 0x00). This register enables holding of the current address during streaming SPI transactions. Figure 89. USR0 Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 ADDR_HOLD R/W-0x0 Table 25. USR0 Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved ADDR_HOLD R/W 0x0 0 : Use the ASCEND register to select address ascend or descend mode (default) 1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register 0 7.6.1.7 CLK_CTRL0 Register (Address = 0x029) [reset = 0x00] CLK_CTRL0 is shown in Figure 90 and described in Table 26. Return to Summary Table. Clock Control 0 register (default: 0x00). This register is used to control the SYSREF receiver (SYSREF±), processing of the SYSREF signal and the SYSREF windowing zoom and delay settings. Figure 90. CLK_CTRL0 Register 7 RESERVED R/W-0x0 6 SYSREF_PROC_EN R/W-0x0 5 SYSREF_RECV_EN R/W-0x0 4 SYSREF_ZOOM R/W-0x0 3 2 1 SYSREF_SEL R/W-0x0 0 Table 26. CLK_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0x0 Reserved 6 SYSREF_PROC_EN R/W 0x0 This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN. 5 SYSREF_RECV_EN R/W 0x0 Set this bit to enable the SYSREF receiver circuit (default: disabled). 4 SYSREF_ZOOM R/W 0x0 Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. SYSREF_SEL R/W 0x0 Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. These bits must be set to 0 to use SYSREF calibration; see the Automatic SYSREF Calibration section. 3-0 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 75 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.8 CLK_CTRL1 Register (Address = 0x02A) [reset = 0x00] CLK_CTRL1 is shown in Figure 91 and described in Table 27. Return to Summary Table. Clock Control 1 register (default: 0x00). This register allows SYSREF to be used as the timestamp input, allows inversion of the SYSREF signal, and enables the DC-coupled receiver mode for the CLK± and SYSREF± inputs. Figure 91. CLK_CTRL1 Register 7 6 5 RESERVED 4 3 SYSREF_TIME_STAMP_ EN R/W-0x0 R/W-0x0 2 DEVCLK_LVPECL_EN 1 SYSREF_LVPECL_EN 0 SYSREF_INVERTED R/W-0x0 R/W-0x0 R/W-0x0 Table 27. CLK_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0x0 Reserved 3 SYSREF_TIME_STAMP_ EN R/W 0x0 The SYSREF signal is output on the LSB of the LVDS output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. This bit allows SYSREF± to be used as the timestamp input. 2 DEVCLK_LVPECL_EN R/W 0x0 Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table. 1 SYSREF_LVPECL_EN R/W 0x0 Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table. 0 SYSREF_INVERTED R/W 0x0 This bit inverts the SYSREF signal used for alignment. 7.6.1.9 SYSREF_POS Register (Address = 0x02C-0x02E) [reset = Undefined] SYSREF_POS is shown in Figure 92 and described in Table 28. Return to Summary Table. SYSREF Capture Position register (read-only status). This register is used by the SYSREF windowing feature to report back the valid SYSREF capture windows; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. Figure 92. SYSREF_POS Register 23 22 21 15 14 13 7 6 5 20 19 SYSREF_POS[23:16] R-Undefined 12 11 SYSREF_POS[15:8] R-Undefined 4 3 SYSREF_POS[7:0] R-Undefined 18 17 16 10 9 8 2 1 0 Table 28. SYSREF_POS Register Field Descriptions Bit 23-0 76 Field Type Reset Description SYSREF_POS R/W Undefined Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this field to program SYSREF_SEL. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.10 INA Full-Scale Range Adjust Register (Address = 0x030-0x031) [reset = 0xA000] FS_RANGE_A is shown in Figure 93 and described in Table 29. Return to Summary Table. INA± Full-Scale Range Adjust register (default: 0xA000). This register is used to change the full-scale input voltage of the INA± input. Calibration must be performed after changing this register; see the Full-Scale Voltage (VFS) Adjustment section. Figure 93. FS_RANGE_A Register 15 14 13 12 11 10 9 8 7 FS_RANGE_A R/W-0xA000 6 5 4 3 2 1 0 Table 29. FS_RANGE_A Register Field Descriptions Bit 15-0 Field Type Reset Description FS_RANGE_A R/W 0xA000 These bits enable adjustment of the analog full-scale range for INA±. 0x0000: Settings below 0x2000 result in degraded performance 0x2000: 500 mVPP - Recommended minimum setting 0xA000: 800 mVPP (default) 0xFFFF: 1000 mVPP - Maximum setting 7.6.1.11 INB Full-Scale Range Adjust Register (Address = 0x032-0x033) [reset = 0xA000] FS_RANGE_B is shown in Figure 94 and described in Table 30. Return to Summary Table. INB± Full-Scale Range Adjust register (default: 0xA000). This register is used to change the full-scale input voltage of the INB± input. Calibration must be performed after changing this register; see the Full-Scale Voltage (VFS) Adjustment section. Figure 94. FS_RANGE_B Register 15 14 13 12 11 10 9 8 7 FS_RANGE_B R/W-0xA000 6 5 4 3 2 1 0 Table 30. FS_RANGE_B Register Field Descriptions Bit 15-0 Field Type Reset Description FS_RANGE_B R/W 0xA000 These bits enable adjustment of the analog full-scale range for INB±. 0x0000: Settings below 0x2000 result in degraded performance 0x2000: 500 mVPP - Recommended minimum setting 0xA000: 800 mVPP (default) 0xFFFF: 1000 mVPP - Maximum setting Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 77 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.12 BG_BYPASS Register (Address = 0x038) [reset = 0x00] BG_BYPASS is shown in Figure 95 and described in Table 31. Return to Summary Table. Band-Gap Bypass register (default: 0x00). This register can be used to bypass the internal reference and use the VA11 supply voltage instead. Figure 95. BG_BYPASS Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 BG_BYPASS R/W-0x0 Table 31. BG_BYPASS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved 0 BG_BYPASS R/W 0x0 When set, VA11 is used as the voltage reference instead of the band-gap voltage. 7.6.1.13 TMSTP_CTRL Register (Address = 0x03B) [reset = 0x00] TMSTP_CTRL is shown in Figure 96 and described in Table 32. Return to Summary Table. TMSTP± and Differential SYNC Control register (default: 0x00). This register enables or disables the TMSTP± input and determines the termination scheme for this input. Figure 96. TMSTP_CTRL Register 7 6 5 4 3 2 RESERVED R/W-0x0 1 TMSTP_LVPECL_EN R/W-0x0 0 TMSTP_RECV_EN R/W-0x0 Table 32. SYNC_CTRL Register Field Descriptions 78 Bit Field Type Reset Description 7-2 RESERVED R/W 0x0 Reserved 1 TMSTP_LVPECL_EN R/W 0x0 When set, this bit activates the DC-coupled, low-voltage PECL mode for the differential TMSTP± receiver; see the Pin Functions table. 0 TMSTP_RECV_EN R/W 0x0 This bit enables the differential TMSTP± receiver. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.14 LVDS_SWING Register (Address = 0x048) [reset = 0x00] LVDS_SWING is shown in Figure 97 and described in Table 33. Return to Summary Table. LVDS Swing Mode register (default: 0x00). This register determines the operating mode of the LVDS output drivers. Figure 97. LVDS_SWING Register 7 6 5 4 3 2 1 RESERVED R/W-0x0 0 LVDS_SWING R/W-0x0 Table 33. LVDS_SWING Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0x0 Reserved 1-0 LVDS_SWING R/W 0x0 These bits set the swing mode of the LVDS output buffers: 0 : High-swing mode (HSM) (default) 1 : Low-swing mode (LSM) 2 : Reserved (do not use) 3 : Low-swing mode for use with receivers that have a high-Z load termination (HZM). Only use with short transmission lines to avoid reflections caused by a high-Z receiver. 7.6.1.15 INPUT_MUX Register (Address = 0x060) [reset = 0x01] INPUT_MUX is shown in Figure 98 and described in Table 34. Return to Summary Table. Input Mux Control register (default: 0x01). This register controls the input used in single-channel mode and the swapping of inputs in dual-channel mode; see the Analog Inputs section. Figure 98. INPUT_MUX Register 7 6 RESERVED R/W-0x0 5 4 DUAL_INPUT R/W-0x0 3 2 1 RESERVED R/W-0x0 0 SINGLE_INPUT R/W-0x1 Table 34. INPUT_MUX Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0x0 Reserved DUAL_INPUT R/W 0x0 This bit selects the input for dual-channel mode (non-DES mode). Only applies if DES_EN = 0. 0 : Channel A samples INA±, channel B samples INB± (no swap) (default) 1 : Channel A samples INB±, channel B samples INA± (swap) 3-2 RESERVED R/W 0x0 Reserved 1-0 SINGLE_INPUT R/W 0x1 These bits define which chip input is sampled in single-channel mode (DES mode). Only applies if DES_EN = 1. 0 : Reserved 1 : INA± is sampled (DESA mode) 2 : INB± is sampled (DESB mode) 3 : Reserved 4 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 79 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.16 CAL_EN Register (Address = 0x61) [reset = 0x01] CAL_EN is shown in Figure 99 and described in Table 35. Return to Summary Table. Calibration Enable register (default: 0x01). This register is used to enable or disable ADC core calibration. Figure 99. CAL_EN Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 CAL_EN R/W-0x1 Table 35. CAL_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved CAL_EN R/W 0x1 This bit enables calibration. Set this bit high to run calibration. Set this bit low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the encoders and LVDS interface. Note 1: Many calibration SPI registers are not synchronized to the internal clock that runs the calibration logic. Changing these registers may corrupt the calibration state machine. Always clear CAL_EN before making any changes to these registers. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings. Note 2: Always set CAL_EN before setting LVDS_EN. Note 3: Always clear LVDS_EN before clearing CAL_EN. 0 7.6.1.17 CAL_CFG0 Register (Address = 0x062) [reset = 0x01] CAL_CFG0 is shown in Figure 100 and described in Table 36. Return to Summary Table. Calibration Configuration 0 register (default: 0x01). This register controls offset calibration and sets whether foreground or background calibration is used. Only change this register when CAL_EN is 0. Figure 100. CAL_CFG0 Register 7 6 5 4 RESERVED R/W-0x0 3 CAL_BGOS R/W-0x0 2 CAL_OS R/W-0x0 1 CAL_BG R/W-0x0 0 CAL_FG R/W-0x1 Table 36. CAL_CFG0 Register Field Descriptions 80 Bit Field Type Reset Description 7-4 RESERVED R/W 0x0 Reserved 3 CAL_BGOS R/W 0x0 0 : Disable background offset calibration (default) 1 : Enable background offset calibration (requires CAL_BG to be set). 2 CAL_OS R/W 0x0 0 : Disable foreground offset calibration (default) 1 : Enable foreground offset calibration (requires CAL_FG to be set) 1 CAL_BG R/W 0x0 0 : Disable background calibration (default) 1 : Enable background calibration 0 CAL_FG R/W 0x1 0 : Reset calibration values, skip foreground calibration. 1 : Reset calibration values, then run foreground calibration (default). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.18 CAL_AVG Register (Address = 0x68) [reset = 0x61] CAL_AVG is shown in Figure 101 and described in Table 37. Return to Summary Table. Calibration Averaging register (default: 0x61). This address determines the amount of averaging used for offset calibration. Figure 101. CAL_AVG Register 7 RESERVED R/W-0x0 6 5 OS_AVG R/W-0x6 4 3 2 1 0 RESERVED R-0x1 Table 37. CAL_AVG Register Field Descriptions Bit Field Type Reset Description RESERVED R/W 0x0 Reserved 6-4 OS_AVG R/W 0x6 Select the amount of averaging used for each measurement of the offset correction search. A larger number corresponds to more averaging. 3-0 RESERVED R 0x1 Always write 0x1. 7 7.6.1.19 CAL_STATUS Register (Address = 0x06A) [reset = Undefined] CAL_STATUS is shown in Figure 102 and described in Table 38. Return to Summary Table. Calibration Status register (default: Undefined) (read-only). This register is used to read out the calibration status information. Figure 102. CAL_STATUS Register 7 6 RESERVED R-Undefined 5 4 3 CAL_STAT R-Undefined 2 1 CAL_STOPPED R-Undefined 0 FG_DONE R-Undefined Table 38. CAL_STATUS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R Undefined Reserved 4-2 CAL_STAT R Undefined Calibration status code 1 CAL_STOPPED R Undefined This bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped. 0 FG_DONE R Undefined This bit is high to indicate that foreground calibration has completed (or was skipped). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 81 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.20 CAL_PIN_CFG Register (Address = 0x06B) [reset = 0x00] CAL_PIN_CFG is shown in Figure 103 and described in Table 39. Return to Summary Table. Calibration Pin Configuration register (default: 0x00). This register sets the function of the CALSTAT pin and selects whether hardware or software CALTRIG is used. Figure 103. CAL_PIN_CFG Register 7 6 5 RESERVED R/W-0x0 4 3 2 1 CAL_STATUS_SEL R/W-0x0 0 CAL_TRIG_EN R/W-0x0 Table 39. CAL_PIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0x0 Reserved 2-1 CAL_STATUS_SEL R/W 0x0 0 1 2 3 CAL_TRIG_EN R/W 0x0 This bit selects the hardware or software trigger source. 0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored). 1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored. 0 : : : : CALSTAT CALSTAT CALSTAT CALSTAT output pin matches FG_DONE output pin matches CAL_STOPPED output pin matches ALARM output is always low 7.6.1.21 CAL_SOFT_TRIG Register (Address = 0x06C) [reset = 0x01] CAL_SOFT_TRIG is shown in Figure 104 and described in Table 40. Return to Summary Table. Calibration Software Trigger register (default: 0x01). This register is used as the software CALTRIG. Figure 104. CAL_SOFT_TRIG Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 CAL_SOFT_TRIG R/W-0x1 Table 40. CAL_SOFT_TRIG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved CAL_SOFT_TRIG R/W 0x1 CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN = 0 to use CAL_SOFT_TRIG for the calibration trigger. Note: If no calibration trigger is needed, leave CAL_TRIG_EN = 0 and CAL_SOFT_TRIG = 1 (trigger set high). 0 82 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.22 Low-Power Background Calibration Register (Address = 0x6E) [reset = 0x88] CAL_LP is shown in Figure 105 and described in Table 41. Return to Summary Table. Low-Power Background Calibration register (default: 0x88). This register enables low-power background calibration and sets the parameters for low-power background calibration. Figure 105. CAL_LP Register 7 6 LP_SLEEP_DLY R/W-0x4 5 4 3 LP_WAKE_DLY R/W-0x1 2 RESERVED R/W-0x0 1 LP_TRIG R/W-0x0 0 LP_EN R/W-0x0 Table 41. CAL_LP Register Field Descriptions Bit Field Type Reset Description 7-5 LP_SLEEP_DLY R/W 0x4 These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits. 0: Sleep delay = (23 + 1) × 256 × tCLK 1: Sleep delay = (215 + 1) × 256 × tCLK 18 2: Sleep delay = (2 + 1) × 256 × tCLK 3: Sleep delay = (221 + 1) × 256 × tCLK 4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately 1.338 seconds with a 3.2-GHz clock) 5: Sleep delay = (227 + 1) × 256 × tCLK 6: Sleep delay = (230 + 1) × 256 × tCLK 7: Sleep delay = (233 + 1) × 256 × tCLK 4-3 LP_WAKE_DLY R/W 0x1 These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins. 0: Wake delay = (23 + 1) × 256 × tCLK 1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21 ms with a 3.2-GHz clock) 2: Wake delay = (221 + 1) × 256 × tCLK 3: Wake delay = (224 + 1) × 256 × tCLK 2 RESERVED Must write 0x0. 1 LP_TRIG R/W 0x0 0: ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode). 1: ADCs sleep until woken by a trigger. An ADC is woken when the calibration trigger (the CAL_SOFT_TRIG bit or CAL_TRIG input) is low. 0 LP_EN R/W 0x0 0: Disable low-power background calibration (default) 1: Enable low-power background calibration (only applies when CAL_BG = 1). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 83 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.23 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00] CAL_DATA_EN is shown in Figure 106 and described in Table 42. Return to Summary Table. Calibration Data Enable register (default: 0x00). This register enables reading calibration data. Figure 106. CAL_DATA_EN Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 CAL_DATA_EN R/W-0x0 Table 42. CAL_DATA_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved CAL_DATA_EN R/W 0x0 Set this bit to enable the CAL_DATA register to enable reading and writing of calibration data; see the CAL_DATA register for more information. 0 7.6.1.24 CAL_DATA Register (Address = 0x71) [reset = Undefined] CAL_DATA is shown in Figure 107 and described in Table 43. Return to Summary Table. Calibration Data register (default: Undefined). This register is used to read out the calibration data. Figure 107. CAL_DATA Register 7 6 5 4 3 2 1 0 CAL_DATA R/W-0x0 Table 43. CAL_DATA Register Field Descriptions 84 Bit Field Type Reset Description 7-0 CAL_DATA R/W 0x0 After setting CAL_DATA_EN, repeated reads of this register return all calibration values for the ADCs. Repeated writes of this register input all calibration values for the ADCs. To read the calibration data, read the register 673 times. To write the vector, write the register 673 times with previously stored calibration data. To speed up the read or write operation, set ADDR_HOLD = 1 and use streaming read or write process. IMPORTANT: Accessing the CAL_DATA register when CAL_STOPPED = 0 corrupts the calibration. Also, stopping the process before reading or writing 673 times leaves the calibration data in an invalid state. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.25 GAIN_TRIM_A Register (Address = 0x07A) [reset = Undefined] GAIN_TRIM_A is shown in Figure 108 and described in Table 44. Return to Summary Table. Gain DAC Trim A register (default from fuse ROM). This register is used for trimming the INA± gain. Figure 108. GAIN_TRIM_A Register 7 6 5 4 3 2 1 0 GAIN_TRIM_A R/W-Undefined Table 44. GAIN_TRIM_A Register Field Descriptions Bit Field Type Reset Description 7-0 GAIN_TRIM_A R/W Undefined This register enables gain trim of channel A. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±. 7.6.1.26 GAIN_TRIM_B Register (Address = 0x07B) [reset = Undefined] GAIN_TRIM_B is shown in Figure 109 and described in Table 45. Return to Summary Table. Gain DAC Trim B register (default from fuse ROM). This register is used for trimming the INB± gain. Figure 109. GAIN_TRIM_B Register 7 6 5 4 3 2 1 0 GAIN_TRIM_B R/W-Undefined Table 45. GAIN_TRIM_B Register Field Descriptions Bit Field Type Reset Description 7-0 GAIN_TRIM_B R/W Undefined This register enables gain trim of channel B. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 85 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.27 BG_TRIM Register (Address = 0x07C) [reset = Undefined] BG_TRIM is shown in Figure 110 and described in Table 46. Return to Summary Table. Band-Gap Trim register (default from fuse ROM). Use this register to trim the internal band-gap reference. The voltage can be measured on the BG pin. Figure 110. BG_TRIM Register 7 6 5 4 3 2 RESERVED R/W-0x0 1 0 BG_TRIM R/W-Undefined Table 46. BG_TRIM Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0x0 Reserved 3-0 BG_TRIM R/W Undefined This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required. 7.6.1.28 RTRIM_A Register (Address = 0x07E) [reset = Undefined] RTRIM_A is shown in Figure 111 and described in Table 47. Return to Summary Table. Resistor TRIM for INA± register (default from fuse ROM). This register can be used to trim the input termination resistance of INA±. Figure 111. RTRIM_A Register 7 6 5 4 3 2 1 0 RTRIM_A R/W-Undefined Table 47. RTRIM_A Register Field Descriptions 86 Bit Field Type Reset Description 7-0 RTRIM_A R/W Undefined This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.29 RTRIM_B Register (Address = 0x7F) [reset = Undefined] RTRIM_B is shown in Figure 112 and described in Table 48. Return to Summary Table. Resistor TRIM for INB± (default from fuse ROM). This register can be used to trim the input termination resistance of INB±. Figure 112. RTRIM_B Register 7 6 5 4 3 2 1 0 RTRIM_B R/W-Undefined Table 48. RTRIM_B Register Field Descriptions Bit Field Type Reset Description 7-0 RTRIM_B R/W Undefined This register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 87 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.30 ADC_DITH Register (Address = 0x9D) [reset = 0x01] ADC_DITH is shown in Figure 113 and described in Table 49. Return to Summary Table. ADC Dither register (default: 0x01). This register can be used enable or disable ADC dither and to adjust the amount of dither used. Figure 113. ADC_DITH Register 7 6 5 RESERVED R/W-0x00 4 3 2 ADC_DITH_ERR 0x0 1 ADC_DITH_AMP 0x0 0 ADC_DITH_EN 0x1 Table 49. ADC_DITH Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0x00 Reserved 2 ADC_DITH_ERR R/W 0x0 Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode. 0 : Rounding error degrades SNR 1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur 1 ADC_DITH_AMP R/W 0x0 0 : Small dither for better SNR (default) 1 : Large dither for better spurious performance 0 ADC_DITH_EN R/W 0x1 Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance. 7.6.1.31 Timing Adjustment for Bank 0 (0° Clock) Register (Address = 0x102) [reset = Undefined] B0_TIME_0 is shown in Figure 114 and described in Table 50. Return to Summary Table. Timing Adjustment for Bank 0 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 0 ADC when ADC A is configured for a 0° clock phase (dual channel mode). Figure 114. B0_TIME_0 Register 7 6 5 4 3 2 1 0 B0_TIME_0 R/W-Undefined Table 50. B0_TIME_0 Register Field Descriptions 88 Bit Field Type Reset Description 7-0 B0_TIME_0 R/W Undefined Timing adjustment for bank 0 when ADC A is configured for 0° clock phase (dual channel mode). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.32 Timing Adjustment for Bank 0 (90° Clock) Register (Address = 0x103) [reset = Undefined] B0_TIME_90 is shown in Figure 115 and described in Table 51. Return to Summary Table. Timing Adjustment for Bank 0 (–90° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 0 ADC when ADC A is configured for a –90° clock phase (single channel mode). Figure 115. B0_TIME_90 Register 7 6 5 4 3 2 1 0 B0_TIME_90 R/W-Undefined Table 51. B0_TIME_90 Register Field Descriptions Bit Field Type Reset Description 7-0 B0_TIME_90 R/W Undefined Time adjustment for bank 0 applied when ADC is configured for –90° clock phase (single channel mode). 7.6.1.33 Timing Adjustment for Bank 1 (0° Clock) Register (Address = 0x112) [reset = Undefined] B1_TIME_0 is shown in Figure 116 and described in Table 52. Return to Summary Table. Timing Adjustment for Bank 1 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 1 ADC when ADC A is configured for a 0° clock phase (dual channel mode). Figure 116. B1_TIME_0 Register 7 6 5 4 3 2 1 0 B1_TIME_0 R/W-Undefined Table 52. B1_TIME_0 Register Field Descriptions Bit Field Type Reset Description 7-0 B1_TIME_0 R/W Undefined Timing adjustment for bank 1 applied when ADC is configured for 0° clock phase (dual channel mode). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 89 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.34 Timing Adjustment for Bank 1 (90° Clock) Register (Address = 0x113) [reset = Undefined] B1_TIME_90 is shown in Figure 117 and described in Table 53. Return to Summary Table. Timing Adjustment for Bank 1 (–90° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 1 ADC when ADC A is configured for a –90° clock phase (single channel mode). Figure 117. B1_TIME_90 Register 7 6 5 4 3 2 1 0 B1_TIME_90 R/W-Undefined Table 53. B1_TIME_90 Register Field Descriptions Bit Field Type Reset Description 7-0 B1_TIME_90 R/W Undefined Time adjustment for bank 1 applied when ADC is configured for –90° clock phase (single channel mode). 7.6.1.35 Timing Adjustment for Bank 4 (0° Clock) Register (Address = 0x142) [reset = Undefined] B4_TIME_0 is shown in Figure 118 and described in Table 54. Return to Summary Table. Timing Adjustment for Bank 4 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 4 ADC when ADC B is configured for a 0° clock phase (dual channel mode and single channel mode). Figure 118. B4_TIME_0 Register 7 6 5 4 3 2 1 0 B4_TIME_0 R/W-Undefined Table 54. B4_TIME_0 Register Field Descriptions Bit Field Type Reset Description 7-0 B4_TIME_0 R/W Undefined Timing adjustment for bank 4 applied when ADC is configured for 0° clock phase (dual channel mode and single channel mode). 7.6.1.36 Timing Adjustment for Bank 5 (0° Clock) Register (Address = 0x152) [reset = Undefined] B5_TIME_0 is shown in Figure 119 and described in Table 55. Return to Summary Table. Timing Adjustment for Bank 5 (0° clock) register (default from fuse ROM). This register is used to adjust the timing of the Bank 5 ADC when ADC B is configured for a 0° clock phase (dual channel mode and single channel mode). Figure 119. B5_TIME_0 Register 7 6 5 4 3 2 1 0 B5_TIME_0 R/W-Undefined Table 55. B5_TIME_0 Register Field Descriptions 90 Bit Field Type Reset Description 7-0 B5_TIME_0 R/W Undefined Timing adjustment for bank 5 applied when ADC is configured for 0° clock phase (dual channel mode and single channel mode). Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.37 LSB_CTRL Register (Address = 0x160) [reset = 0x00] LSB_CTRL is shown in Figure 120 and described in Table 56. Return to Summary Table. LSB Control Bit Output register (default: 0x00). This register enables output of the timestamp signal on the LSB of the output samples. Figure 120. LSB_CTRL Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 TIME_STAMP_EN R/W-0x0 Table 56. LSB_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved TIME_STAMP_EN R/W 0x0 When set, the timestamp signal is transmitted on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) matches the latency of the analog ADC inputs. Also set SYNC_RECV_EN when using TIME_STAMP_EN. 0 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 91 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.38 LSB_SEL Register (Address = 0x161) [reset = 0x00] LSB_SEL is shown in Figure 121 and described in Table 57. Return to Summary Table. LSB Control Bit Position register (default: 0x00). This register defines the position of the timestamp signal output on the LSB of the samples. Figure 121. LSB_SEL Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 LSB_SEL R/W-0x0 Table 57. LSB_SEL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved LSB_SEL R/W 0x0 0 : Place timestamp on lane 0 (Dx0±) of each LVDS output bus, independent of the LWIDTH setting. Lane 0 of each bus is enabled regardless of LWIDTH. 1 : Place timestamp on the LSB of the effective sample size as set by the LWIDTH parameter. The timestamp is placed on the LSB of the output sample. The lane that carries timestamp depends on the selected output sample width (LWIDTH). For 12-bit samples, lane 0 carries the control data. For 11-bit samples, lane 1 carries the control data. For 10-bit samples, lane 2 carries the control data. For 8-bit samples, lane 4 carries the control data. 0 7.6.1.39 UPAT0 Register (Address = 0x180) [reset = 0x0000] UPAT0 is shown in Figure 122 and described in Table 58. Return to Summary Table. User-Defined Pattern (sample 0) register (default: 0x0000). This register, and the UPATx registers that follow, define the user defined test pattern that can be used to test various aspects of the LVDS interface. Figure 122. UPAT0 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT0 R/W-0x0 5 4 3 2 UPAT0 R/W-0x0 Table 58. UPAT0 Register Field Descriptions Bit 92 Field Type Reset Description 15-12 RESERVED R/W 0x0 Reserved 11-0 UPAT0 R/W 0x0 Defines the value for sample 0 of the user defined pattern. See the PAT_SEL register and the Digital Interface Test Patterns and LVSD SYNC Functionality section. Note: Only change this register when LVDS_EN = 0. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.40 UPAT1 Register (Address = 0x182) [reset = 0x0FFF] UPAT1 is shown in Figure 123 and described in Table 59. Return to Summary Table. User-Defined Pattern (sample 1) register (default: 0x0FFF). Figure 123. UPAT1 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT1 R/W-0xF 5 4 3 2 UPAT1 R/W-0xFF Table 59. UPAT1 Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W 0x0 Reserved 11-0 UPAT1 R/W 0xFFF Defines the value for sample 1 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. 7.6.1.41 UPAT2 Register (Address = 0x184) [reset = 0x0000] UPAT2 is shown in Figure 124 and described in Table 60. Return to Summary Table. User-Defined Pattern (sample 2) register (default: 0x0000). Figure 124. UPAT2 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT2 R/W-0x0 5 4 3 2 UPAT2 R/W-0x00 Table 60. UPAT2 Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W 0x0 Reserved 11-0 UPAT2 R/W 0x000 Defines the value for sample 2 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 93 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.42 UPAT3 Register (Address = 0x186) [reset = 0x0FFF] UPAT3 is shown in Figure 125 and described in Table 61. Return to Summary Table. User-Defined Pattern (sample 3) register (default: 0x0FFF) Figure 125. UPAT3 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT3 R/W-0xF 5 4 3 2 UPAT3 R/W-0xFF Table 61. UPAT3 Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W 0x0 Reserved 11-0 UPAT3 R/W 0xFFF Defines the value for sample 3 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. 7.6.1.43 UPAT4 Register (Address = 0x188) [reset = 0x0000] UPAT4 is shown in Figure 126 and described in Table 62. Return to Summary Table. User-Defined Pattern (sample 4) register (default: 0x0000). Figure 126. UPAT4 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT4 R/W-0x0 5 4 3 2 UPAT4 R/W-0x00 Table 62. UPAT4 Register Field Descriptions Bit 94 Field Type Reset Description 15-12 RESERVED R/W 0x0 Reserved 11-0 UPAT4 R/W 0x000 Defines the value for sample 4 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.44 UPAT5 Register (Address = 0x18A) [reset = 0x0FFF] UPAT5 is shown in Figure 127 and described in Table 63. Return to Summary Table. User-Defined Pattern (sample 5) register (default: 0x0FFF). Figure 127. UPAT5 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT5 R/W-0xF 5 4 3 2 UPAT5 R/W-0xFF Table 63. UPAT5 Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W 0x0 Reserved 11-0 UPAT5 R/W 0xFFF Defines the value for sample 5 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. 7.6.1.45 UPAT6 Register (Address = 0x18C) [reset = 0x0000] UPAT6 is shown in Figure 128 and described in Table 64. Return to Summary Table. User-Defined Pattern (sample 6) register (default: 0x0000). Figure 128. UPAT6 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT6 R/W-0x0 5 4 3 2 UPAT6 R/W-0x00 Table 64. UPAT6 Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W 0x0 Reserved 11-0 UPAT6 R/W 0x000 Defines the value for sample 6 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 95 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.46 UPAT7 Register (Address = 0x18E) [reset = 0x0FFF] UPAT7 is shown in Figure 129 and described in Table 65. Return to Summary Table. User-Defined Pattern (sample 7) register (default: 0x0FFF). Figure 129. UPAT7 Register 15 14 13 12 11 10 RESERVED R/W-0x0 7 6 9 8 1 0 UPAT7 R/W-0xF 5 4 3 2 UPAT7 R/W-0xFF Table 65. UPAT7 Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W 0x0 Reserved 11-0 UPAT7 R/W 0xFFF Defines the value for sample 7 of the user defined pattern. See UPAT0 register. Note: Only change this register when LVDS_EN = 0. 7.6.1.47 UPAT_CTRL Register (Address = 0x190) [reset = 0x1E] UPAT_CTRL is shown in Figure 130 and described in Table 66. Return to Summary Table. User-Defined Pattern Control register (default: 0x1E). This register allows selection of the predefined lane pattern instead of the user defined pattern and the inversion of specified bits for each lane during user defined pattern transmission. Figure 130. UPAT_CTRL Register 7 6 RESERVED R/W-0x0 5 4 LANE_PAT R/W-0x1 3 UPAT_INV_D R/W-0x1 2 UPAT_INV_C R/W-0x1 1 UPAT_INV_B R/W-0x1 0 UPAT_INV_A R/W-0x0 Table 66. UPAT_CTRL Register Field Descriptions 96 Bit Field Type Reset Description 7-5 RESERVED R/W 0x0 Reserved 4 LANE_PAT R/W 0x1 When set, the UPATn registers are ignored, and the user-defined pattern is set to: 0x000, 0xFFF, 0x000, 0x000, 0x000, 0xFFF, 0xFFF, 0xFFF. This bit acts as a shortcut to avoid programming the UPATn registers. PAT_SEL register must still be programmed to configure the interface to select the user-defined pattern. The UPAT_INV_* registers still apply when using LANE_PAT. 3 UPAT_INV_D R/W 0x1 When set, bit [11] of the user-defined pattern is inverted on the bus D output. 2 UPAT_INV_C R/W 0x1 When set, bit [10] of the user-defined pattern is inverted on the bus C output. 1 UPAT_INV_B R/W 0x1 When set, bit [9] of the user-defined pattern is inverted on the bus B output. 0 UPAT_INV_A R/W 0x0 When set, bit [8] of the user-defined pattern is inverted on the bus A output. Note: Only change this register when LVDS_EN = 0. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.48 LVDS_EN Register (Address = 0x200) [reset = 0x01] LVDS_EN is shown in Figure 131 and described in Table 67. Return to Summary Table. LVDS Subsystem Enable register (default: 0x01). Use this register to enable or disable the LVDS interface. Figure 131. LVDS_EN Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 LVDS_EN R/W-0x1 Table 67. LVDS_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved LVDS_EN R/W 0x1 0 : Disable LVDS interface 1 : Enable LVDS interface Note 1: Before altering other LVDS registers, you must clear LVDS_EN. When LVDS_EN is 0, the LVDS interface block is held in reset and the outputs are powered down. The clocks are gated off to save power. The frame counter is also held in reset, so SYSREF will not align the frame counter. Note 2: Always set CAL_EN before setting LVDS_EN. Note 3: Always clear LVDS_EN before clearing CAL_EN. 0 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 97 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.49 LMODE Register (Address = 0x201) [reset = 0x01] LMODE is shown in Figure 132 and described in Table 68. Return to Summary Table. LVDS Mode register (default: 0x01). This register is used to define the configuration of the LVDS interface. LVDS_EN must be 0 before making any changes to this register. Additionally, CAL_EN must be 0 before changing DES_EN. Figure 132. LMODE Register 7 6 5 RESERVED R/W-0x0 4 LWIDTH R/W-0x0 3 RESERVED R/W-0x0 2 DES_EN R/W-0x0 1 LALIGNED R/W-0x0 0 LDEMUX R/W-0x1 Table 68. LMODE Register Field Descriptions 98 Bit Field Type Reset Description 7-6 RESERVED R/W 0x0 Reserved 5-4 LWIDTH R/W 0x0 Specifies the sample width for the LVDS output interface. 0 : 12-bit sample width (default) 1 : 11-bit sample width 2 : 10-bit sample width 3 : 8-bit sample width 3 RESERVED R/W 0x0 Reserved 2 DES_EN R/W 0x0 0 : Disable DES mode (enable dual channel mode) 1 : Enable DES mode (enable single channel CAL_EN must be 0 before changing DES_EN. mode) 1 LALIGNED R/W 0x0 0 : The LVDS buses are staggered for optimized switching noise and latency. 1 : The LVDS buses are aligned for simplified timing. 0 LDEMUX R/W 0x1 0 : Demux-by-1, uses 2 LVDS buses total 1 : Demux-by-2, uses 4 LVDS buses total Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.50 LFRAME Register (Address = 0x202) [reset = 0x80] LFRAME is shown in Figure 133 and described in Table 69. Return to Summary Table. LVDS Frame Length register (default: 0x80) (128 decimal). This register sets the length of the frame and subsequently the period of the strobe signal. Only change this register when LVDS_EN = 0. Figure 133. LFRAME Register 7 6 5 4 3 2 1 0 LFRAME R/W-0x80 Table 69. LFRAME Register Field Descriptions Bit Field Type Reset Description 7-0 LFRAME R/W 0x80 Defines the number of UIs in each LVDS frame. Any multiple of 4 from 4 to 128 is supported. All other values are unsupported. When LDEMUX=0, one UI is one CLK± cycle. When LDEMUX=1, one UI is two CLK± cycles. Note: Setting LFRAME to 4 is not recommended, as it may be difficult to achieve deterministic latency over all process, voltage, and temperature conditions. The propagation delay variation may be larger than the frame period. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 99 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.51 LSYNC_N Register (Address = 0x203) [reset = 0x01] LSYNC_N is shown in Figure 134 and described in Table 70. Return to Summary Table. LVDS Manual Sync Request register (default: 0x01). This register can be used as a software replacement for the LVDS SYNC signal. Figure 134. LSYNC_N Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 LSYNC_N R/W-0x1 Table 70. LSYNC_N Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved LSYNC_N R/W 0x1 Set this bit to 0 to request LVDS synchronization (equivalent to the hardware SYNC signal being asserted, as selected by SYNC_SEL). For normal operation, leave this bit set to 1. Note: The LSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL setting in the LCTRL register. However, if the selected sync pin is stuck low, the synchronization request cannot be de-asserted unless SYNC_SEL=2. 0 7.6.1.52 LCTRL Register (Address = 0x204) [reset = 0x02] LCTRL is shown in Figure 135 and described in Table 71. Return to Summary Table. LVDS Control register (default: 0x02). This register is used to configure aspects of the LVDS interface including scrambling, hardware SYNC input and the output format. Only change this register when LVDS_EN = 0. Figure 135. LCTRL Register 7 6 RESERVED R/W-0x0 5 4 SCR R/W-0x0 3 2 SYNC_SEL R/W-0x0 1 SFORMAT R/W-0x1 0 RESERVED R/W-0x0 Table 71. LCTRL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0x0 Reserved SCR R/W 0x0 When set, all LVDS data and strobes are scrambled. This also includes the part-time strobes or timestamp signals (since they are output on the data lanes). See the Scrambling section. 3-2 SYNC_SEL R/W 0x0 0 : Use the SYNC_SE input for SYNC function (default) 1 : Use the TMSTP± input for SYNC function. also set SYNC_RECV_EN to use the differential TMSTP± input. 2 : Do not use any SYNC input pin, set if using LSYNC_N. 1 SFORMAT R/W 0x1 Output sample format for LVDS output samples 0 : Offset binary 1 : Signed 2’s complement (default) 0 RESERVED R/W 0x0 Reserved 4 100 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.53 PAT_SEL Register (Address = 0x205) [reset = 0x02] PAT_SEL is shown in Figure 136 and described in Table 72. Return to Summary Table. LVDS Pattern Control register (default: 0x02). This register controls the output data or pattern used during active mode (SYNC de-asserted) and sync mode (SYNC asserted). During normal operation, the active pattern should be set to the ADC output data and the SYNC pattern can be set to the mode used by the receiver for synchronizing the interface. The input used for SYNC is chosen by SYNC_SEL. Figure 136. PAT_SEL Register 7 6 5 4 3 ACT_PAT R/W-0x0 2 1 0 SYNC_PAT R/W-0x2 Table 72. PAT_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 ACT_PAT R/W 0x0 This selects the output pattern that is generated when the SYNC signal is de-asserted. 0: ADC output data 1: All LVDS lanes output the user-defined pattern (see UPAT registers) 2-15: Reserved 3-0 SYNC_PAT R/W 0x2 This selects the output pattern that is generated when the SYNC signal is asserted. 0: Reserved 1: All LVDS lanes output the user-defined pattern (see UPAT registers) 2: Frame strobe is transmitted on the LSB of the output samples only. The other bits transmit data based on ACT_PAT. 3: The frame strobe is transmitted on all active LVDS data lanes and strobes. 4-15: Reserved Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 101 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.54 LCS_EN Register (Address = 0x206) [reset = 0xFF] LCS_EN is shown in Figure 137 and described in Table 73. Return to Summary Table. LVDS Clock and Strobe Enables register (default: 0xFF). Use these registers to enable or disable specific LVDS output clocks (DxCLK±) and frame strobes (DxSTB±) if the receiver will not use them. If an entire LVDS bus is disabled (because of PD_CH or LDEMUX) then its associated clock and frame strobe are disabled automatically, regardless of this register. Note: Only change this register when LVDS_EN = 0. Figure 137. LCS_EN Register 7 DDSTB_EN R/W-0x1 6 DCSTB_EN R/W-0x1 5 DBSTB_EN R/W-0x1 4 DASTB_EN R/W-0x1 3 DDCLK_EN R/W-0x1 2 DCCLK_EN R/W-0x1 1 DBCLK_EN R/W-0x1 0 DACLK_EN R/W-0x1 Table 73. LCS_EN Register Field Descriptions Bit 102 Field Type Reset Description 7 DDSTB_EN R/W 0x1 Enable DDSTB± output 6 DCSTB_EN R/W 0x1 Enable DCSTB± output 5 DBSTB_EN R/W 0x1 Enable DBSTB± output 4 DASTB_EN R/W 0x1 Enable DASTB± output 3 DDCLK_EN R/W 0x1 Enable DDCLK± output 2 DCCLK_EN R/W 0x1 Enable DCCLK± output 1 DBCLK_EN R/W 0x1 Enable DBCLK± output 0 DACLK_EN R/W 0x1 Enable DACLK± output Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.55 LVDS_STATUS Register (Address = 0x208) [reset = Undefined] LVDS_STATUS is shown in Figure 138 and described in Table 74. Return to Summary Table. System Status register (default: undefined). This register returns status bits for the device including SYNC status for the LVDS interface and internal clock status. Figure 138. LVDS_STATUS Register 7 6 RESERVED R/W-0x0 5 SYNC_STATUS R/W-Undefined 4 REALIGNED R/W-Undefined 3 ALIGNED R/W-Undefined 2 1 RESERVED R/W-0x0 0 Table 74. LVDS_STATUS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0x0 Reserved 5 SYNC_STATUS R/W Undefined Returns the instantaneous state of the LVDS interface SYNC signal (SYNC_SE or TMSTP±). 0 : SYNC asserted 1 : SYNC de-asserted 4 REALIGNED R/W Undefined When high, indicates that SYSREF realigned internal clocks. REALIGNED_ALM should be used for monitoring of realignment events instead of this bit. Writing a 1 to this bit will clear it, but will not affect the REALIGNED_ALM bit. 3 ALIGNED R/W Undefined When high, indicates that internal clock phases have been established by SYSREF. Any SYSREF rising edge that is processed after enabling the LVDS system will set this bit. This bit can be monitored during startup to verify that SYSREF has been processed before continuing system initialization. Writing a 1 to this bit will clear it and the next SYSREF event will set it again. RESERVED R/W 0x0 Reserved 2-0 7.6.1.56 PD_CH Register (Address = 0x209) [reset = 0x00] PD_CH is shown in Figure 139 and described in Table 75. Return to Summary Table. ADC Channel Power Down (default: 0x00). This register allows individual channels to be powered down. LVDS_EN and CAL_EN must be set to 0 before changing PD_CH. Figure 139. PD_CH Register 7 6 5 4 3 2 1 PD_BCH R/W-0x0 RESERVED R/W-0x0 0 PD_ACH R/W-0x0 Table 75. PD_CH Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0x0 Reserved 1 PD_BCH R/W 0x0 When set, the “B” ADC channel is powered down. 0 PD_ACH R/W 0x0 When set, the “A” ADC channel is powered down. Important notes: LVDS_EN and CAL_EN must be set to 0 before changing PD_CH. PD_CH disables the LVDS lanes (Dx[11:0], DxSTB, DxCLK) for the powered down channel. To power down both ADC channels, use MODE or the PD pin. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 103 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.57 OVR_T0 Register (Address = 0x211) [reset = 0xF2] OVR_T0 is shown in Figure 140 and described in Table 76. Return to Summary Table. Overrange Threshold 0 register (default: 0xF2). This register sets threshold 0 for ADC overrange detection. Figure 140. OVR_T0 Register 7 6 5 4 3 2 1 0 OVR_T0 R/W-0xF2 Table 76. OVR_T0 Register Field Descriptions Bit Field Type Reset Description 7-0 OVR_T0 R/W 0xF2 This parameter defines the absolute sample level that causes OVA0 or OVB0 to be set. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (default: 0xF2 = 242 –> -0.5dBFS) 7.6.1.58 OVR_T1 Register (Address = 0x212) [reset = 0xAB] OVR_T1 is shown in Figure 141 and described in Table 77. Return to Summary Table. Overrange Threshold 1 register (default: 0xAB). This register sets threshold 1 for ADC overrange detection. Figure 141. OVR_T1 Register 7 6 5 4 3 2 1 0 OVR_T1 R/W-0xAB Table 77. OVR_T1 Register Field Descriptions 104 Bit Field Type Reset Description 7-0 OVR_T1 R/W 0xAB This parameter defines the absolute sample level that causes OVA1 or OVB1 to be set. The detection level in dBFS (peak) is 20log10(OVR_T1/256) (default: 0xAB = 171 –> -3.5dBFS) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.59 OVR_CFG Register (Address = 0x213) [reset = 0x07] OVR_CFG is shown in Figure 142 and described in Table 78. Return to Summary Table. Overrange Enable/Hold Off register (default: 0x07). This register enables overrange detection and sets the output pulse duration for an overrange event. The maximum overrange pulse duration is recommended to avoid excess switching noise. Figure 142. OVR_CFG Register 7 6 5 4 3 OVR_EN R/W-0x0 RESERVED R/W-0x0 2 1 OVR_N R/W-0x7 0 Table 78. OVR_CFG Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0x0 Reserved OVR_EN R/W 0x0 ORA0, ORA1, ORB0 and ORB1 outputs pins are enabled and output the overrange status when this bit is set high. The outputs are held low when this bit is set low. OVR_N R/W 0x7 Program this register to adjust the pulse length for the ORA0, ORA1 and ORB0, ORB1 outputs. The minimum pulse duration of the overrange outputs is 8 × 2OVR_N CLK± cycles. 3 2-0 7.6.1.60 SPIN_ID Register (Address = 0x297) [reset = 0x00] SPIN_ID is shown in Figure 143 and described in Table 79. Return to Summary Table. Chip Spin Identifier register (default from fuse ROM, read-only). This register returns the spin identification number of the device. Figure 143. SPIN_ID Register 7 6 RESERVED R/W-0x0 5 4 3 2 SPIN_ID R/W-0x0 1 0 Table 79. SPIN_ID Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0x0 Reserved 4-0 SPIN_ID R/W 0x0 Returns 0 to indicate that this device is ADC12DL3200. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 105 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.61 SRC_EN Register (Address = 0x2B0) [reset = 0x00] SRC_EN is shown in Figure 144 and described in Table 80. Return to Summary Table. SYSREF Calibration Enable register (default: 0x00). This register starts the SYSREF calibration process. Figure 144. SRC_EN Register 7 6 5 4 RESERVED R/W-0x0 3 2 1 0 SRC_EN R/W-0x0 Table 80. SRC_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0x0 Reserved SRC_EN R/W 0x0 0 : SYSREF calibration disabled (default). Use the TAD register to manually control the tAD Adjust setting and adjust the CLK± aperture delay. 1: SYSREF calibration enabled. The CLK± delay is automatically calibrated. The TAD register is ignored. A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Ensure that ADC calibration is not running before setting SRC_EN. 0 106 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.62 SRC_CFG Register (Address = 0x2B1) [reset = 0x05] SRC_CFG is shown in Figure 145 and described in Table 81. Return to Summary Table. SYSREF Calibration Configuration register (default: 0x05). This register determines the amount of averaging performed for automatic SYSREF calibration and sets the maximum supported SYSREF cycle. The total duration of SYSREF calibration will be no longer than: TSYSREFCAL (in CLK± cycles) = 256 * 19 * 4 * (SRC_AVG + SRC_HDUR + 2). Figure 145. SRC_CFG Register 7 6 5 4 3 RESERVED R/W-0x0 2 1 SRC_AVG R/W-0x1 0 SRC_HDUR R-0x1 Table 81. SRC_CFG Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0x0 Reserved 3-2 SRC_AVG R/W 0x1 Specifies the amount of averaging used for SYSREF Calibration. Larger values will increase calibration time and reduce the variance of the calibrated value. 0: 4 high-speed accumulations for each SYSREF measurement 1: 16 high-speed accumulations for each SYSREF measurement 2: 64 high-speed accumulations for each SYSREF measurement 3: 256 high-speed accumulations for each SYSREF measurement 1-0 SRC_HDUR R/W 0x1 Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, calibration will fail. Larger values will increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values will also reduce the variance of the calibrated value. 0: 4 cycles per accumulation, supporting SYSREF periods of up to 85 CLK± cycles 1: 16 cycles per accumulation, supporting SYSREF periods of up to 1100 CLK± cycles 2: 64 cycles per accumulation, supporting SYSREF periods of up to 5200 CLK± cycles 3: 256 cycles per accumulation, supporting SYSREF periods of up to 21580 CLK± cycles Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 107 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.63 SRC_STATUS Register (Address = 0x2B2) [reset = Undefined] SRC_STATUS is shown in Figure 146 and described in Table 82. Return to Summary Table. SYSREF Calibration Status register (read-only, default: undefined). This register indicates that the SYSREF calibration process has completed and outputs the result of the SYSREF calibration process. Figure 146. SRC_STATUS Register 23 22 21 20 19 18 10 17 SRC_DONE R-Undefined 9 16 SRC_TAD[16] R-Undefined 8 12 11 SRC_TAD[15:8] R-Undefined 4 3 SRC_TAD[7:0] R-Undefined 2 1 0 RESERVED R-Undefined 15 14 13 7 6 5 Table 82. SRC_STATUS Register Field Descriptions Field Type Reset Description 23-18 Bit RESERVED R/W 0x0 Reserved 17 SRC_DONE R/W 0x0 This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has been completed. SRC_TAD R/W 0x0 This field returns the value for t AD Adjust computed by SYSREF Calibration. It is only valid if SRC_DONE=1. SRC_TAD[16] indicates if CLK± has been inverted. SRC_TAD[15:8] indicates the coarse delay adjustment. SRC_TAD[7:0] indicates the fine delay adjustment. SRC_TAD can be read out and manually written to the TAD register during subsequent boot cycles for repeatability. 16-0 108 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.64 TAD Register (Address = 0x2B5-2B7) [reset = 0x000000] TAD is shown in Figure 147 and described in Table 83. Return to Summary Table. CLK± Timing Adjust register (default: 0x00). This register sets the tAD Adjust delay when automatic SYRSEF calibration is not used. Figure 147. TAD Register 23 22 21 15 14 13 7 6 5 20 RESERVED R-Undefined 12 TAD[15:8] R-0x00 4 TAD[7:0] R-0x00 19 18 17 11 10 9 16 TAD[16] R-0x0 8 3 2 1 0 Table 83. TAD Register Field Descriptions Field Type Reset Description 23-17 Bit RESERVED R/W 0x0 Reserved 16-0 TAD R/W 0x0 This register controls tAD Adjust when SRC_EN=0. Use this register to manually control the CLK± inversion and delay when SYSREF Calibration is disabled. TAD[16] inverts CLK± when set. TAD[15:8] controls the coarse delay adjustment. TAD[7:0] controls the fine delay adjustment. If ADC calibration is enabled (CAL_EN=1), or the LVDS interface is enabled (LVDS_EN=1), the following rules must be obeyed to avoid clock glitches and unpredictable behavior: Do not change TAD[16]. CAL_EN and LVDS_EN must be set to 0 before changing TAD[16]. TAD[15:8] must be increased or decreased gradually (no more than 4 codes at a time). This rule can be obeyed manually via SPI writes or by setting TAD_RAMP_EN. TAD[7:0] may be changed to any value at any time since its resolution is too fine to cause clock glitches. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 109 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.65 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00] TAD_RAMP is shown in Figure 148 and described in Table 84. Return to Summary Table. CLK± Timing Adjust Ramp Control register (default: 0x00). This register enables the tAD adjust ramping feature and sets the ramp rate. Figure 148. TAD_RAMP Register 7 6 5 4 3 2 RESERVED R/W-0x0 1 TAD_RAMP_RATE R/W-0x0 0 TAD_RAMP_EN R/W-0x0 Table 84. TAD_RAMP Register Field Descriptions 110 Bit Field Type Reset Description 7-2 RESERVED R/W 0x0 Reserved 1 TAD_RAMP_RATE R/W 0x0 Specify the ramp rate for tAD adjust when the TAD[15:8] register is written while TAD_RAMP_EN is 1. 0 : tAD adjust ramps up or down one code per 256 CLK± cycles. 1 : tAD adjust ramps up or down four codes per 256 CLK± cycles. 0 TAD_RAMP_EN R/W 0x0 TAD ramp enable. Set this bit if ramping of the coarse tAD adjust is desired. 0 : After writing the TAD[15:8] register, tAD adjust is updated fully within 1024 CLK± cycles (ramp feature disabled). 1 : After writing the TAD[15:8] register, tAD adjust ramps up or down gradually until it matches the TAD[15:8] register. When TAD_RAMP_EN is 1, and the user writes the TAD[15:8] register, a digital counter will automatically ramp tAD adjust up or down until it matches the TAD[15:8] register value. This ensures that the coarse delay changes gradually and does not cause glitches in the delayed CLK± waveform. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.66 ALARM Register (Address = 0x2C0) [reset = Undefined] ALARM is shown in Figure 149 and described in Table 85. Return to Summary Table. Alarm Interrupt register (read-only). This register indicates if any unmasked alarm in has been triggered in the ALM_STATUS register. Figure 149. ALARM Register 7 6 5 4 RESERVED R-Undefined 3 2 1 0 ALARM R-Undefined Table 85. ALARM Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R Undefined Reserved ALARM R Undefined This bit returns a ‘1’ whenever any unmasked alarm is set in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms. CAL_STATUS_SEL can be used to drive the ALARM bit onto the CAL_STAT pin to provide a hardware alarm interrupt signal. 0 7.6.1.67 ALM_STATUS Register (Address = 0x2C1) [reset = 0x05] ALM_STATUS is shown in Figure 150 and described in Table 86. Return to Summary Table. Alarm Status register (default: 0x05, write to clear). This register indicates if the individual alarms have been triggered. Figure 150. ALM_STATUS Register 7 6 5 RESERVED R/W-0x0 4 3 2 REALIGNED_ALM R/W-0x1 1 RESERVED R/W-0x0 0 CLK_ALM R/W-0x1 Table 86. ALM_STATUS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0x0 Reserved 2 REALIGNED_ALM R/W 0x1 Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the frame counter) to be realigned to a new phase. Write a ‘1’ to clear this bit. 1 RESERVED R/W 0x0 Reserved 0 CLK_ALM R/W 0x1 Clock Alarm: This bit can be used to detect an upset to the internal clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to Alarm Monitoring for the proper usage of this register. Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’ Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 111 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.68 ALM_MASK Register (Address = 0x2C2) [reset = 0x05] ALM_MASK is shown in Figure 151 and described in Table 87. Return to Summary Table. Alarm Mask register (default: 0x05). This register is used to mask out alarms that should not trigger the ALARM interrupt. Figure 151. ALM_MASK Register 7 6 5 RESERVED R/W-0x0 4 3 2 MASK_REALIGNED_ALM R/W-0x1 1 RESERVED R/W-0x0 0 MASK_CLK_ALM R/W-0x1 Table 87. ALM_MASK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0x0 Reserved 2 MASK_REALIGNED_ALM R/W 0x1 When set, REALIGNED_ALM is masked and will not impact the ALARM register bit. 1 RESERVED R/W 0x0 Reserved 0 MASK_CLK_ALM R/W 0x1 When set, CLK_ALM is masked and will not impact the ALARM register bit. 7.6.1.69 TADJ_A Register (Address = 0x310) [reset = Undefined] TADJ_A is shown in Figure 152 and described in Table 88. Return to Summary Table. Timing Adjust for A-ADC, Dual Mode register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information. Figure 152. TADJ_A Register 7 6 5 4 3 2 1 0 TADJ_A R/W-Undefined Table 88. TADJ_A Register Field Descriptions 112 Bit Field Type Reset Description 7-0 TADJ_A R/W Undefined This register (and other TADJ* registers that follow it) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes of operation. The default values for all TADJ* registers are loaded from the fuse ROM. The factory trimmed values can be read out and adjusted as required. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.70 TADJ_B Register (Address = 0x313) [reset = Undefined] TADJ_B is shown in Figure 153 and described in Table 89. Return to Summary Table. Timing Adjust for B-ADC, Dual Mode register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information. Figure 153. TADJ_B Register 7 6 5 4 3 2 1 0 TADJ_B R/W-Undefined Table 89. TADJ_B Register Field Descriptions Bit Field Type Reset Description 7-0 TADJ_B R/W Undefined See TADJ_A register for description. 7.6.1.71 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = Undefined] TADJ_A_FG90_VINA is shown in Figure 154 and described in Table 90. Return to Summary Table. Timing Adjust for A-ADC, DES, Foreground Calibration, INA± register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information. Figure 154. TADJ_A_FG90_VINA Register 7 6 5 4 3 TADJ_A_FG90_VINA R/W-Undefined 2 1 0 Table 90. TADJ_A_FG90_VINA Register Field Descriptions Bit Field Type Reset Description 7-0 TADJ_A_FG90_VINA R/W Undefined See TADJ_A register for description. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 113 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.72 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = Undefined] TADJ_B_FG0_VINA is shown in Figure 155 and described in Table 91. Return to Summary Table. Timing Adjust for B-ADC, DES, Foreground Calibration, INA± regsiter (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information. Figure 155. TADJ_B_FG0_VINA Register 7 6 5 4 3 TADJ_B_FG0_VINA R/W-Undefined 2 1 0 Table 91. TADJ_B_FG0_VINA Register Field Descriptions Bit Field Type Reset Description 7-0 TADJ_B_FG0_VINA R/W Undefined See TADJ_A register for description. 7.6.1.73 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = Undefined] TADJ_A_FG90_VINB is shown in Figure 156 and described in Table 92. Return to Summary Table. Timing Adjust for A-ADC, DES, Foreground Calibration, INB± register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information. Figure 156. TADJ_A_FG90_VINB Register 7 6 5 4 3 TADJ_A_FG90_VINB R/W-Undefined 2 1 0 Table 92. TADJ_A_FG90_VINB Register Field Descriptions 114 Bit Field Type Reset Description 7-0 TADJ_A_FG90_VINB R/W Undefined See TADJ_A register for description. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.74 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0] TADJ_B_FG0_VINB is shown in Figure 157 and described in Table 93. Return to Summary Table. Timing Adjust for B-ADC, DES, Foreground Calibration, INB± register (default from fuse ROM). This register is used for ADC timing trim. Refer to the Trimming section for more information. Figure 157. TADJ_B_FG0_VINB Register 7 6 5 4 3 TADJ_B_FG0_VINB R/W-Undefined 2 1 0 Table 93. TADJ_B_FG0_VINB Register Field Descriptions Bit Field Type Reset Description 7-0 TADJ_B_FG0_VINB R/W Undefined See TADJ_A register for description. 7.6.1.75 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = Undefined] OADJ_A_FG0_VINA is shown in Figure 158 and described in Table 94. Return to Summary Table. Offset Adjustment for A-ADC / Foreground Calibration / 0° Clock / INA± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details. Figure 158. OADJ_A_FG0_VINA Register 15 14 13 RESERVED R/W-Undefined 7 6 5 12 11 4 3 OADJ_A_FG0_VINA R/W-Undefined 10 9 OADJ_A_FG0_VINA R/W-Undefined 2 1 8 0 Table 94. OADJ_A_FG0_VINA Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R/W Undefined Reserved 11-0 OADJ_A_FG0_VINA R/W Undefined Offset adjustment value applied to A-ADC when it samples INA± using 0° clock phase and foreground calibration is enabled. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 115 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.76 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = Undefined] OADJ_A_FG0_VINB is shown in Figure 159 and described in Table 95. Return to Summary Table. Offset Adjustment for A-ADC / Foreground Calibration / 0° Clock / INB± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details. Figure 159. OADJ_A_FG0_VINB Register 15 14 13 RESERVED R/W-Undefined 7 6 5 12 11 4 3 OADJ_A_FG_VINB R/W-Undefined 10 9 OADJ_A_FG_VINB R/W-Undefined 8 2 0 1 Table 95. OADJ_A_FG0_VINB Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R/W Undefined Reserved 11-0 OADJ_A_FG0_VINB R/W Undefined Offset adjustment value applied to A-ADC when it samples INB± using 0° clock phase and foreground calibration is enabled. 7.6.1.77 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = Undefined] OADJ_A_FG90_VINA is shown in Figure 160 and described in Table 96. Return to Summary Table. Offset Adjustment for A-ADC / Foreground Calibration / 90° Clock / INA± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details. Figure 160. OADJ_A_FG90_VINA Register 15 14 13 RESERVED R/W-Undefined 7 6 5 12 11 4 3 OADJ_A_FG90_VINA R/W-Undefined 10 9 OADJ_A_FG90_VINA R/W-Undefined 2 1 8 0 Table 96. OADJ_A_FG90_VINA Register Field Descriptions Bit 116 Field Type Reset Description 15-12 RESERVED R/W Undefined Reserved 11-0 OADJ_A_FG90_VINA R/W Undefined Offset adjustment value applied to A-ADC when it samples INA± using 90° clock phase and foreground calibration is enabled. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.78 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = Undefined] OADJ_A_FG90_VINB is shown in Figure 161 and described in Table 97. Return to Summary Table. Offset Adjustment for A-ADC / Foreground Calibration / 90° Clock / INB± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details. Figure 161. OADJ_A_FG90_VINB Register 15 14 13 RESERVED R/W-Undefined 7 6 5 12 11 4 3 OADJ_A_FG90_VINB R/W-Undefined 10 9 OADJ_A_FG90_VINB R/W-Undefined 2 1 8 0 Table 97. OADJ_A_FG90_VINB Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R/W Undefined Reserved 11-0 OADJ_A_FG90_VINB R/W Undefined Offset adjustment value applied to A-ADC when it samples INB± using 90° clock phase and foreground calibration is enabled. 7.6.1.79 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = Undefined] OADJ_B_FG0_VINA is shown in Figure 162 and described in Table 98. Return to Summary Table. Offset Adjustment for B-ADC / Foreground Calibration / INA± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details. Figure 162. OADJ_B_FG0_VINA Register 15 14 13 RESERVED R/W-Undefined 7 6 5 12 11 4 3 OADJ_B_FG0_VINA R/W-Undefined 10 9 OADJ_B_FG0_VINA R/W-Undefined 2 1 8 0 Table 98. OADJ_B_FG0_VINA Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R/W Undefined Reserved 11-0 OADJ_B_FG0_VINA R/W Undefined Offset adjustment value applied to B-ADC when it samples INA± using 0° clock phase and foreground calibration is enabled. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 117 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.80 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = Undefined] OADJ_B_FG0_VINB is shown in Figure 163 and described in Table 99. Return to Summary Table. Offset Adjustment for B-ADC / Foreground Calibration / INB± register (default from fuse ROM). This register is used for ADC core offset trimming. See the Trimming section for more details. Figure 163. OADJ_B_FG0_VINB Register 15 14 13 RESERVED R/W-Undefined 7 6 5 12 11 10 9 OADJ_B_FG0_VINB R/W-Undefined 4 3 OADJ_B_FG0_VINB R/W-Undefined 2 1 8 0 Table 99. OADJ_B_FG0_VINB Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R/W Undefined Reserved 11-0 OADJ_B_FG0_VINB R/W Undefined Offset adjustment value applied to B-ADC when it samples INB± using 0° clock phase and foreground calibration is enabled. 7.6.1.81 GAIN_B0 Register (Address = 0x360) [reset = Undefined] GAIN_B0 is shown in Figure 164 and described in Table 100. Return to Summary Table. Fine Gain Adjust for Bank 0 register (default from fuse ROM). This register adjusts the gain of the Bank 0 ADC. Figure 164. GAIN_B0 Register 7 6 RESERVED R/W-Undefined 5 4 3 2 GAIN_B0 R/W-Undefined 1 0 Table 100. GAIN_B0 Register Field Descriptions 118 Bit Field Type Reset Description 7-5 RESERVED R/W Undefined Reserved 4-0 GAIN_B0 R/W Undefined Fine gain adjustment for bank 0. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 7.6.1.82 GAIN_B1 Register (Address = 0x361) [reset = Undefined] GAIN_B1 is shown in Figure 165 and described in Table 101. Return to Summary Table. Fine Gain Adjust for Bank 1 register (default from fuse ROM). This register adjusts the gain of the Bank 1 ADC. Figure 165. GAIN_B1 Register 7 6 RESERVED R/W-Undefined 5 4 3 2 GAIN_B1 R/W-Undefined 1 0 Table 101. GAIN_B1 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W Undefined Reserved 4-0 GAIN_B1 R/W Undefined Fine gain adjustment for bank 1. 7.6.1.83 GAIN_B4 Register (Address = 0x364) [reset = Undefined] GAIN_B4 is shown in Figure 166 and described in Table 102. Return to Summary Table. Fine Gain Adjust for Bank 4 register (default from fuse ROM). This register adjusts the gain of the Bank 4 ADC. Figure 166. GAIN_B4 Register 7 6 RESERVED R/W-Undefined 5 4 3 2 GAIN_B4 R/W-Undefined 1 0 Table 102. GAIN_B4 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W Undefined Reserved 4-0 GAIN_B4 R/W Undefined Fine gain adjustment for bank 4. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 119 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 7.6.1.84 GAIN_B5 Register (Address = 0x365) [reset = Undefined] GAIN_B5 is shown in Figure 167 and described in Table 103. Return to Summary Table. Fine Gain Adjust for Bank 5 register (default from fuse ROM). This register adjusts the gain of the Bank 5 ADC. Figure 167. GAIN_B5 Register 7 6 RESERVED R/W-Undefined 5 4 3 2 GAIN_B5 R/W-Undefined 1 0 Table 103. GAIN_B5 Register Field Descriptions 120 Bit Field Type Reset Description 7-5 RESERVED R/W Undefined Reserved 4-0 GAIN_B5 R/W Undefined Fine gain adjustment for bank 5. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ADC12DL3200 can be used in a wide range of applications including radar, electronic warfare, satellite communications, test equipment (communications testers and oscilloscopes) and software-defined radios (SDRs). The wide input bandwidth enables direct RF sampling to at least 10 GHz and the high sampling rate allows signal bandwidths of greater than 3 GHz. The ADC12DL3200 can also be DC-coupled to meet the needs of oscilloscopes or wideband digitizers. The Typical Applications section describes two configurations that meet the needs of a number of these applications. 8.2 Typical Applications 8.2.1 Wideband RF Sampling Receiver This section demonstrates the use of the ADC12DL3200 as a wideband RF sampling receiver. The solution is flexible and can be used as either a 2-channel receiver (such as a diversity receiver) or as a single channel allowing double the signal bandwidth. The ADC is driven by single-ended RF amplifiers and the conversion to differential signaling is achieved by a transformer (balun). The ADC12DL3200 uses a low-latency LVDS interface in order to achieve quick event detection for latency-sensitive applications. LNA LNA Up to 56 LVDS pairs Anti-Alias BPF ADC A LVDS SYNC~ LNA LNA Anti-Alias BPF ADC B LVDS FPGA or ASIC Clocking Subsystem User Control Logic SPI LMK04832 Device Clock ÷ SYSREF N÷ R÷ PFD 10 MHz Reference ÷ Device Clock ÷ ÷ SYSREF Figure 168. Typical Configuration for Wideband RF Sampling Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 121 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Typical Applications (continued) 8.2.1.1 Design Requirements 8.2.1.1.1 Input Signal Path Use appropriate band-limiting filters to reject unwanted frequencies in the input signal path. A 1:2 balun transformer is needed to convert the 50-Ω, single-ended signal to 100-Ω differential for input to the ADC. The balun outputs can be either AC-coupled, or directly connected to the ADC differential inputs, which are terminated internally to GND. Drivers must be selected to provide any needed signal gain and that have the necessary bandwidth capabilities. In general, baluns must be selected to cover the needed frequency range, have a 1:2 impedance ratio, and have acceptable gain and phase balance over the frequency range of interest. Mount baluns with poor differential output return loss as close to the ADC inputs as possible to avoid ripples in the frequency response at high input frequencies. Resistive attenuators (Pi- or T-type) can also help dampen ripples caused by poor return loss. Table 104 lists a number of recommended baluns for different frequency ranges. Table 104. Recommended Baluns (1) PART NUMBER MANUFACTURER (1) MINIMUM FREQUENCY (MHz) MAXIMUM FREQUENCY (MHz) BAL-0009SMG Marki Microwave 0.5 9000 BAL-0208SMG Marki Microwave 2000 8000 TCM2-43X+ Mini-Circuits 10 4000 TCM2-33WX+ Mini-Circuits 10 3000 B0430J50100AHF Anaren 400 3000 See the Device and Documentation Support section. 8.2.1.1.2 Clocking The ADC12DL3200 clock inputs must be AC-coupled to the device to ensure rated performance. The clock source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended clock synthesizers include the LMX2594, LMX2592, and LMX2582. For multi-device synchronization the data converter system (ADC plus FPGA) requires a SYSREF signal in addition to the device (sampling) clock, which is similar to that used for JESD204B converters. Therefore, JESD204B-compatible clock devices are a good choice for clocking the ADC12DL3200. The LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DL3200 devices are used in a system. 8.2.1.2 Detailed Design Procedure Certain component values used in conjunction with the ADC12DL3200 must be calculated based on system parameters. Those items are covered in this section. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors AC-coupling capacitors are used in the input CLK± pair. The capacitor values must be large enough to address the lowest frequency signals of interest, but not so large as to cause excessively long startup biasing times, or unwanted parasitic inductance. The minimum capacitor value can be calculated based on the lowest frequency signal that is transferred through the capacitor. Given a 50-Ω, single-ended clock or data path impedance, good practice is to set the capacitor impedance to be less than 1 Ω at the lowest frequency of interest. This setting ensures minimal impact on signal level at that frequency. For the CLK± path, the minimum-rated clock frequency is 800 MHz. Therefore, the minimum capacitor value can be calculated from: ZC = 1/ (2 ´ p ´ ¦ CLK ´ C ) 122 (3) Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Setting Zc = 1 Ω and rearranging gives: C = 1/ (2 ´ p ´ 800 MHz ´ 1 W ) = 199 pF (4) Therefore, a capacitance value of at least 199 pF is needed to provide the low-frequency response for the CLK± path. If the minimum clock frequency is higher than 800 MHz, this calculation can be revisited for that frequency. Capacitors must also be selected for good response at high frequencies, usually identified by low inductance or high self-resonance frequency, and with dimensions that match the high-frequency signal traces they are connected to. Capacitors of the 0201 size are frequently well-suited to these applications. 8.2.1.3 Application Curves The ADC12DL3200 can be used in either dual-channel mode or single-channel mode to suit different applications and system architectures. Figure 169 and show operation with a 497.77-MHz input signal in the following configurations: • 6.4 GSPS, single-channel mode (DES_EN = 1), four LVDS buses (LDEMUX = 1), and staggered output data (LALIGNED = 0) • 3.2 GSPS, dual-channel mode (DES_EN = 0), four LVDS buses (LDEMUX = 1), and staggered output data (LALIGNED = 0) Figure 169. FFT for 497.77-MHz Input Signal in SingleChannel Mode at 6.4 GSPS Figure 170. FFT for 497.77-MHz Input Signal in DualChannel Mode at 3.2 GSPS 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope This section demonstrates the use of the ADC12DL3200 in a reconfigurable oscilloscope. The oscilloscope can operate as a dual-channel oscilloscope running at 2.5 GSPS or can be reconfigured through SPI programming as a single-channel, 5-GSPS oscilloscope. This reconfigurable setup allows tradeoffs between the number of channels and the sampling rate of the oscilloscope as needed without changing the hardware. Set the input bandwidth to the desired maximum signal bandwidth through the use of an antialiasing, low-pass filter. Digital filtering can then be used to reconfigure the analog bandwidth as required. For instance, the maximum bandwidth can be set to 1 GHz for use during pulsed transient detection and then reconfigured to 100 MHz through digital filtering for low-noise, power-supply ripple observation. Figure 171 shows the application block diagram for a reconfigurable oscilloscope. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 123 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Up to 56 LVDS pairs LMH5401 Front Panel Channel A LMH6401 ADC A DAC LMH6559 OPA703 LVDS DC Offset Adjustment SYNC~ DAC8560 LMH5401 Front Panel Channel B Anti-Alias LPF Programmable Termination LMH6401 Anti-Alias LPF Programmable Termination ADC B DAC LMH6559 OPA703 DC Offset Adjustment DAC8560 LVDS FPGA or ASIC Clocking Subsystem User Control Logic SPI LMK04832 Device Clock ÷ SYSREF N÷ R÷ PFD 10 MHz Reference ÷ Device Clock ÷ ÷ SYSREF Figure 171. Typical Configuration for a Reconfigurable Oscilloscope 8.2.2.1 Design Requirements 8.2.2.1.1 Input Signal Path Most oscilloscopes are required to be DC-coupled in order to monitor DC or low-frequency signals. This requirement forces the design to use DC-coupled, fully differential amplifiers to convert from single-ended signaling at the front panel to differential signaling at the ADC. This design uses two differential amplifiers. The first amplifier shown in Figure 171 is the LMH5401 that converts from single-ended to differential signaling. The LMH5401 interfaces with the front panel through a programmable termination network and has an offset adjustment input. The amplifier has an 8-GHz, gain-bandwidth product that is sufficient to support a 1-GHz bandwidth oscilloscope. A second amplifier, the LMH6401, comes after the LMH5401 to provide a digitally programmable gain control for the oscilloscope. The LMH6401 supports a gain range from –6 dB to 26 dB in 1dB steps. If gain control is not necessary or is performed in a different location in the signal chain, then this amplifier can be replaced with a second LMH5401 for additional fixed gain or omitted altogether. The input of the oscilloscope contains a programmable termination block that is not covered in detail here. This block enables the front-panel input termination to be programmed. For instance, many oscilloscopes allow the termination to be programmed as either 50-Ω or 1-MΩ to meet the needs of various applications. A 75-Ω termination can also be desired to support cable infrastructure use cases. This block can also contain an option for DC blocking to remove the DC component of the external signal and therefore pass only AC signals. A precision digital-to-analog converter (DAC) is used to configure the offset of the oscilloscope front-end to prevent saturation of the analog signal chain for input signals containing large DC offsets. The DAC8560 is shown in Figure 171 along with signal-conditioning amplifiers OPA703 and LMH6559. The first differential amplifier, LMH5401, is driven by the front panel input circuitry on one input, and the DC offset bias on the second input. The impedance of these driving signals must be matched at DC and over frequency to ensure good evenorder harmonic performance in the single-ended to differential conversion operation. The high bandwidth of the LMH6559 allows the device to maintain low impedance over a wide frequency range. An antialiasing, low-pass filter is positioned at the input of the ADC to limit the bandwidth of the input signal into the ADC. This amplifier also band-limits the front-end noise to prevent aliased noise from degrading the signal-tonoise ratio of the overall system. Design this filter for the maximum input signal bandwidth specified by the oscilloscope. The input bandwidth can then be reconfigured through the use of digital filters in the FPGA or ASIC to limit the oscilloscope input bandwidth to a bandwidth less than the maximum. 124 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 8.2.2.1.2 Clocking The ADC12DL3200 clock inputs must be AC-coupled to the device to ensure rated performance. The clock source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended clock synthesizers include the LMX2594, LMX2592, and LMX2582. For multi-device synchronization or deterministic latency the data converter system (ADC plus FPGA) requires a SYSREF signal in addition to the device (sampling) clock, which is similar to that used for JESD204B converters. Therefore, JESD204B compatible clock devices are a good choice for clocking the ADC12DL3200. The LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DL3200 devices are used in a system. 8.2.2.1.3 The ADC12DL3200 The ADC12DL3200 is ideally suited for oscilloscope applications. The ability to tradeoff channel count and sampling speed allows designers to build flexible hardware to meet multiple needs. This flexibility saves development time and cost, allows hardware reuse for various projects, and enables software upgrade paths for additional functionality. The low code-error rate eliminates concerns about undesired time-domain glitches or sparkle codes. This rate makes the ADC12DL3200 a perfect fit for long-duration transient detection measurements and reduces the probability of false triggers. The input common-mode voltage of 0 V allows the driving amplifiers to use equal split power supplies that center the amplifier output common-mode voltage at 0 V and eliminates the need for common-mode voltage shifting before the ADC inputs. The high input bandwidth of the ADC12DL3200 simplifies the design of the driving amplifier circuit and antialiasing, low-pass filter. The use of dual-edge sampling (DES) in single-channel mode eliminates the need to change the clock frequency when switching between dual- and single-channel modes and simplifies synchronization by relaxing the setup and hold timing requirements of SYSREF. The tAD adjust circuit allows the user to time-align the sampling instances of multiple ADC12DL3200 devices. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 125 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 8.2.2.2 Application Curves The following application curves demonstrate performance and results only of the ADC. The amplifier front-end is not included in these measurements. Figure 172 to Figure 178 illustrate the following configurations and measurements: • 12-bit, 5-GSPS, single-channel oscilloscope – Idle-channel noise (no input) – 40-MHz, square-wave time domain – 200-MHz, sine-wave time domain – 200-MHz, sine-wave frequency domain (FFT) • 12-bit, 2.5-GSPS, dual-channel oscilloscope – Idle-channel noise (no input) – 40-MHz, square-wave (channel B) and 200-MHz, sine-wave (channel A) time domain – 40-MHz, square-wave (channel B) time domain and 200-MHz, sine-wave (channel A) frequency domain (FFT) 126 Figure 172. Idle-Channel Noise (No Input) for 5-GSPS, Single-Channel Oscilloscope Figure 173. 40-MHz, Square-Wave Time Domain for 5GSPS, Single-Channel Oscilloscope Figure 174. 200-MHz, Sine-Wave Time Domain for 5-GSPS, Single-Channel Oscilloscope Figure 175. 200-MHz, Sine-Wave Frequency Domain (FFT) for 5-GSPS, Single-Channel Oscilloscope Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Figure 176. Idle-Channel Noise (No Input) for 2.5-GSPS, Dual-Channel Oscilloscope Figure 177. 200-MHz, Sine-Wave (Channel A) and 40-MHz, Square-Wave (Channel B) Time Domain for 5-GSPS, Single-Channel Oscilloscope Figure 178. 200-MHz, Sine-Wave (Channel A) Frequency Domain (FFT) and 40-MHz, Square-Wave (Channel B) Time Domain for 5-GSPS, Single-Channel Oscilloscope Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 127 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 8.3 Initialization Set Up The device requires a specific startup and alignment sequence. The general order of that sequence is listed in the following steps. 1. Power-up or reset the device. 2. Apply a stable device CLK signal at the desired frequency. 3. Program LVDS_EN = 0 to stop the LVDS state machine and allow setting changes. 4. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes. 5. Program the LMODE register to the desired LVDS output mode. 6. Program SYNC_SEL as needed. Choose SYNCSE or the TMSTP± differential inputs. 7. Configure device calibration settings as desired. Select foreground or background calibration modes and offset calibration as needed. 8. Program CAL_EN = 1 to enable the calibration state machine. 9. Enable overrange via OVR_EN and adjust settings if desired. 10. Program LVDS_EN = 1 to enable the LVDS interface and allow the receiver to initialize. 11. Assert the SYNC signal (set by SYNC_SEL) if required to send the strobe signal or user-defined pattern. 12. Program CAL_SOFT_TRIG = 0. 13. Program CAL_SOFT_TRIG = 1 to initiate a calibration. 128 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 9 Power Supply Recommendations The device requires two different power-supply voltages. 1.9 V DC is required for the VA19 power bus and 1.1 V DC is required for the VA11 and VD11 power buses. VLVDS can be set to any voltage between 1.9 V and 1.1 V. The LVDS output driver common-mode voltage tracks the VLVDS supply voltage. In general, a 1.9-V supply voltage for VLVDS can be used for standard LVDS receivers. The power-supply voltages must be low noise and provide the needed current to achieve rated device performance. There are two recommended power-supply architectures: 1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide switching noise reduction and improved voltage accuracy. 2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent degraded ADC performance. TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements needed: see the WEBENCH® Power Designer Recommended switching regulators for the first stage include the TPS62085, TPS82130, TPS62130A, and similar devices. Recommended low dropout (LDO) linear regulators include the TPS7A7200, TPS74401, and similar devices. For the switcher only approach, the ripple filter must be designed with a notch frequency that aligns with the switching ripple frequency of the DC/DC converter. Make a note of the switching frequency reported from WEBENCH® and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure 179 and Figure 180 illustrate the two approaches. Do not share VLVDS with the analog supply voltages in order to prevent digital switching noise from coupling into the analog signal chain. If VLVDS must be shared with either VA11 or VA19, apply careful power supply filtering to limit digital noise at the analog supply pins. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 129 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 5V-12V www.ti.com 2.2V Buck FB + VA19 1.9V LDO 47 …F 47 …F FB 10 …F 0.1 …F 0.1 …F ± GND GND Power Good 1.4V Buck GND GND VA11 1.1V FB LDO 47 …F 47 …F GND FB GND 10 …F 0.1 …F 0.1 …F GND VD11 FB 10 …F 0.1 …F 0.1 …F GND VLVDS 1.1V to 1.9V Buck FB = Ferrite Bead Filter FB 47 …F FB GND 10 …F 0.1 …F 0.1 …F GND NOTE: FB = ferrite bead filter. Figure 179. LDO Linear Regulator Approach Example 130 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 1.9V 5V-12V Buck Ripple Filter FB + 10 …F 10 …F VA19 10 …F FB 10 …F 0.1 …F 0.1 …F ± GND Power Good GND 1.1V Buck GND Ripple Filter FB 10 …F 10 …F VA11 10 …F FB 10 …F 0.1 …F 0.1 …F GND GND VD11 FB 10 …F 0.1 …F 0.1 …F GND 1.1V to 1.9V Buck FB VLVDS 47 …F FB 10 …F 0.1 …F 0.1 …F GND GND Ripple Filter Notch Frequency to Match Fs of Buck Converter FB = Ferrite Bead Filter NOTE: Ripple filter notch frequency to match the fs of the buck converter. NOTE: FB = ferrite bead filter. Figure 180. Switcher-Only Approach Example 9.1 Power Sequencing The voltage regulators must be sequenced using the power-good outputs and enable inputs to ensure that the Vx11 regulator is enabled after the VA19 supply is good. Similarly, as soon as the VA19 supply drops out of regulation on power-down, the Vx11 regulator is disabled. The general requirement for the ADC is that VA19 ≥ Vx11 during power-up, operation, and power-down. TI also recommends that VA11 and VD11 are derived from a common 1.1-V regulator. This recommendation ensures that all 1.1-V blocks are at the same voltage, and no sequencing problems exist between these supplies. Also use ferrite bead filters to isolate any noise on the VA11 and VD11 buses from affecting each other. If VA11 and VD11 are powered from separate regulators, then the device is sensitive to voltage drops that affect the VA11 input. In this case, if the VA11 voltage is brought down below 0.6 V, the device must be reset through the SOFT_RESET bit in the CONFIG_A register. VLVDS can be powered up independently of the other supplies. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 131 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 10 Layout 10.1 Layout Guidelines There are many critical signals that require specific care during board design: 1. Analog input signals 2. CLK and SYSREF 3. LVDS data outputs at up to 1.6 Gbps 4. Power connections 5. Ground connections Items 1 and 2 must be routed for excellent signal quality at high frequencies. Use the following general practices for these signals: A. Route using loosely coupled 100-Ω differential traces. This routing minimizes impact of corners and lengthmatching serpentines on pair impedance. B. Provide adequate pair-to-pair spacing to minimize crosstalk. C. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. D. Use smoothly radiused corners. Avoid 45- or 90-degree bends. E. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. Cutout below the landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50-Ω, single-ended impedance. F. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane clearances associated with power and signal vias and through-hole component leads. G. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias. H. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs. The LVDS data outputs must be routed with sufficient signal quality using the following general practices: A. Route using tightly coupled 100-Ω differential traces to minimize the routing area and decrease crosstalk between adjacent data pairs. B. Use smoothly radiused corners or 45-degree bends. Avoid 90-degree bends. C. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane clearances associated with power and signal vias and through-hole component leads. D. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias. E. Data, clock, and strobe pairs must be sufficiently delay matched to provide adequate timing margin at the receiver. If routing on multiple layers, trace lengths must be compensated for the delay mismatch introduced by the effective dielectric constant of each layer. In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to fabrication. Perform insertion loss, return loss, and time domain reflectometry (TDR) evaluations. The power and ground connections for the device are also very important. These rules must be followed: 1. Provide low-resistance connection paths to all power and ground pins. 2. Use multiple power layers if necessary to access all pins. 3. Avoid narrow isolated paths that increase connection resistance. 4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power planes. 10.2 Layout Example Figure 181 to Figure 183 provide examples of the critical traces routed on the device evaluation module (EVM). Figure 184 provides an example printed circuit board (PCB) layer stackup. 132 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Layout Example (continued) Figure 181. Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 133 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Layout Example (continued) Figure 182. GND1 Cutouts to Optimize Impedance of Component Pads 134 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 Layout Example (continued) Figure 183. Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 135 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com Layout Example (continued) L1 - SIG Panasonic R-5670K 0.0056" Panasonic R-5775K 0.0030" Panasonic R-5670K 0.0042" Panasonic R-5775K 0.0030" Panasonic R-5670K 0.0040" Panasonic R-5775K 0.0026" Panasonic R-5670K 0.0039" Panasonic R-5775K 0.0026" Panasonic R-5670K 0.0040" Panasonic R-5775K 0.0030" Panasonic R-5670K 0.0042" Panasonic R-5775K 0.0030" Panasonic R-5670K 0.0056" L2 - GND L3 - SIG L4 - GND L5 - SIG L6 - GND L7 - POW 0.0576" L8 - POW L9 - GND L10 - SIG L11 - GND L12 - SIG L13 - GND L14 - SIG 1/4 oz Copper on L1 and L14 1/2 oz Copper on L2, L3, L4, L5, L10, L11, L12 and L13 1 oz Copper on L6, L7, L8 and L9 100-O differential signaling on SIG layers Finished thickness is 0.0620" including plating and solder mask Figure 184. Example PCB Stackup 136 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support WEBENCH® Power Designer 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • LM95233 Dual Remote Diode and Local Temperature Sensor with SMBus Interface and TruTherm™ Technology • LMX2594 15-GHz Wideband PLLatinum™ RF Synthesizer With Phase Synchronization and JESD204B Support • LMX2592 High Performance, Wideband PLLatinum™ RF Synthesizer With Integrated VCO • LMX2582 High Performance, Wideband PLLatinum™ RF Synthesizer With Integrated VCO • LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs • LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier • LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier • DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C Internal Reference • OPAx703, OPAx704 CMOS, Rail-to-Rail, I/O Operational Amplifiers • LMH6559 High-Speed, Closed-Loop Buffer • TPS6208x 3-A Step-Down Converter With Hiccup Short-Circuit Protection In 2 × 2 QFN Package • TPS82130 17-V Input 3-A Step-Down Converter MicroSiP™ Module with Integrated Inductor • TPS6213x 3-V to17-V, 3-A Step-Down Converter In 3x3 QFN Package • TPS7A7200 2-A, Fast-Transient, Low-Dropout Voltage Regulator • TPS74401 3.0-A, Ultra-LDO with Programmable Soft-Start • Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design • Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 137 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com 11.5 Trademarks (continued) All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 138 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 PACKAGE OUTLINE ACF0256A FCBGA - 3.31 mm max height SCALE 0.900 BALL GRID ARRAY 17.2 16.8 B A BALL A1 CORNER PIN 1 ID (OPTIONAL) 17.2 16.8 ( 13) ( 11) 3.31 MAX C SEATING PLANE 0.7 TYP 0.3 BALL TYP 0.2 C 15 TYP 1 TYP (1) TYP SYMM (1) TYP SYMM 256X 0.25 0.1 0.74 0.54 C A B C T R P N M L K J H G F E D C B A 15 TYP 1 2 3 4 5 6 7 8 9 10 14 12 11 13 16 15 1 TYP 4223888/A 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pb-Free die bump and solder ball. www.ti.com Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 139 ADC12DL3200 SLVSDR3B – MAY 2018 – REVISED JUNE 2020 www.ti.com EXAMPLE BOARD LAYOUT ACF0256A FCBGA - 3.31 mm max height BALL GRID ARRAY (1) TYP 256X ( 0.55) 1 (1) TYP 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G SYMM H J K L M N P R T SYMM LAND PATTERN EXAMPLE EXPOSED METAL SNOWN SCALE:6X 0.07 MAX 0.07 MIN ( 0.55) METAL METAL UNDER SOLDER MASK EXPOSED METAL SOLDER MASK OPENING ( 0.55) SOLDER MASK OPENING EXPOSED METAL NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4223888/A 09/2017 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811). www.ti.com 140 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 ADC12DL3200 www.ti.com SLVSDR3B – MAY 2018 – REVISED JUNE 2020 EXAMPLE STENCIL DESIGN ACF0256A FCBGA - 3.31 mm max height BALL GRID ARRAY (1) TYP 256X 0.45 1 (1) TYP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C METAL TYP D E F G SYMM H J K L M N P R T SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE: 6X 4223888/A 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Product Folder Links: ADC12DL3200 141 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) ADC12DL3200ACF ACTIVE FCBGA ACF 256 1 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 ADC12DL32 ADC12DL3200ALJ ACTIVE FCBGA ALJ 256 1 Non-RoHS & Green Call TI Level-3-220C-168 HR -40 to 85 ADC12DL32Z (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of