ADC12J4000NKE

Product Folder Order Now Support & Community Tools & Software Technical Documents ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 ADC12J4000 12-Bit, 4-GSPS ADC With Integrated DDC 1 Features 2 Applications • • • • • • • • • 1 • • • • • • • • • • Excellent Noise and Linearity up to and beyond FIN = 3 GHz Configurable DDC Decimation Factors from 4 to 32 (Complex Baseband Out) Usable Output Bandwidth of 800 MHz at 4x Decimation and 4000 MSPS Usable Output Bandwidth of 100 MHz at 32x Decimation and 4000 MSPS Bypass Mode for Full Nyquist Output Bandwidth Low Pin-Count JESD204B Subclass 1 Interface Automatically Optimized Output Lane Count Embedded Low Latency Signal Range Indication Low Power Consumption Key Specifications: – Max Sampling Rate: 4000 MSPS – Min Sampling Rate: 1000 MSPS – DDC Output Word Size: 15-Bit Complex (30 bits total) – Bypass Output Word Size: 12-Bit Offset Binary – Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz – IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS) – FPBW (–3 dB): 3.2 GHz – Peak NPR: 46 dB – Supply Voltages: 1.9 V and 1.2 V – Power Consumption – Bypass (4000 MSPS): 2 W – Decimate by 10 (4000 MSPS): 2 W – Power Down Mode: 1) complex (I,Q) data is output at a lower sample rate as determined by the decimation factor (4, 8, 10, 16, 20, and 32). 7.4.3 Calibration Calibration adjusts the ADC core to optimize the following device parameters: • ADC core linearity • ADC core-to-core offset matching • ADC core-to-core full-scale range matching • ADC core 4-way interleave timing All calibration processes occur internally. Calibration does not require any external signals to be present and works properly as long as the device is maintained within the values listed in the Recommended Operating Conditions table. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 45 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com Device Functional Modes (continued) 7.4.3.1 Foreground Calibration Mode In foreground mode the calibration process interrupts normal ADC operation and no output data is available during this time (the output code is forced to a static value). The calibration process should be repeated if the device temperature changes by more than 20ºC to ensure rated performance is maintained. Foreground calibration is initiated by setting the CAL_SFT bit (register 0x050, bit 3) which is self clearing. The foreground calibration process finishes within t(CAL) number of DEVCLK cycles. The process occurs somewhat longer when the timing calibration mode is enabled. NOTE Initiating a foreground calibration asynchronously resets the calibration control logic and may glitch internal device clocks. Therefore after setting the CAL_SFT bit clearing and then setting JESD_EN is necessary. If resetting the JESD204B link is undesirable for system reasons, background calibration mode may be preferred. 7.4.3.2 Background Calibration Mode In background mode an additional ADC core is powered-up for a total of 5 ADC cores. At any given time, one core is off-line and not used for data conversion. This core is calibrated in the background and then placed online simultaneous with another core going off-line for calibration. This process operates continuously without interrupting data flow in the application and ensures that all cores are optimized in performance regardless of any changes of temperature. The background calibration cycle rate is fixed and is not adjustable by the user. Because of the additional circuitry active in background calibration mode, a slight degradation in performance occurs in comparison to foreground calibration mode at a fixed temperature. As a result of this degradation, using foreground calibration mode is recommended if the expected change in operating temperature is 30°C. The exact difference in performance is dependent on the DEVCLK (sampling clock) frequency, and the analog input signal frequency and amplitude. For this reason, device and system performance should be evaluated using both calibration modes before finalizing the choice of calibration mode. To enable the background calibration feature, set the CAL_BCK bit (register 0x057, bit 0) and the CAL_CONT bit (register 0x057, bit 1). The value written to the register 0x057 to enable background calibration is therefore 0x013h. After writing this value to register 0x057, set the CAL_SFT bit in register 0x050 to perform the one-time foreground calibration to begin the process. NOTE The ADC offset-adjust feature has no effect when background calibration mode is enabled. 7.4.4 Timing Calibration Mode The timing calibration process optimizes the matching of sample timing for the 4 internally interleaved converters. This process minimize the presence of any timing related interleaving spurs in the captured spectrum. The timing calibration feature is disabled by default, but using this feature is highly recommended. To enable timing calibration, set the T_AUTO bit (register 0x066, bit 0). When this bit is set, the timing calibration performs each time the CAL_SFT bit is set. 46 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 Device Functional Modes (continued) Table 32. Calibration Cycle Timing for Different Calibration Modes and Options CAL_CONT, CAL_BCK T_AUTO LOW_SIG_EN INITIAL ONE-TIME CALIBRATION CAL_SFT 0 → 1 (tDEVCLK) BACKGROUND CALIBRATION CYCLE (1) (ALL CORES) (tDEVCLK) 0 0 0 102 E+6 N/A 0 0 1 64 E+6 N/A 0 1 0 227 E+6 N/A 0 1 1 189 E+6 N/A 1 0 0 127.5 E+6 816 E+6 1 0 1 80 E+6 512 E+6 1 1 0 283.75 E+6 816 E+6 1 1 1 236.25 E+6 512 E+6 (1) N/A = not applicable 7.4.5 Test-Pattern Modes A number of device test modes are available. These modes insert known patterns of information into the device data path for assistance with system debug, development, or characterization. 7.4.5.1 ADC Test-Pattern Mode The 12-bit ADC core has a built-in test-pattern generator. This mode is helpful for verifying the full data link from the ADC to the data receiver when in DDC bypass mode. When the test-pattern mode is enabled, the ADC output data is replaced by a pattern that repeats every two frames. The data sequence is is shown in Table 33 (shown for default settings with foreground calibration mode). Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 47 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com Table 33. ADC Test Pattern (1) LANE (CONVERTER ID) (1) SAMPLE NUMBER (SID) 0 1 2 3 4 5 6 7 8 9 0 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 1 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 2 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 3 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 4 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 5 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 6 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 7 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF When background-calibration mode is enabled, the pattern values are dynamic because the internal converter banks are output on different lanes during the calibration bank-switching process. Each converter bank has dedicated pattern values as listed in Table 34. Table 34. ADC Bank Pattern Values BANK LOCATION LOW VALUE Lane n 0x000 0xFFF Lane n+4 0x040 0xFBF 0 1 2 3 4 HIGH VALUE Lane n 0x004 0xFFE Lane n+4 0x080 0xF7F Lane n 0x008 0xFF7 Lane n+4 0x100 0xEFF Lane n 0x010 0xFEF Lane n+4 0x200 0xDFF Lane n 0x020 0xFDF Lane n+4 0x400 0xBFF 7.4.5.2 Serializer Test-Mode Details Test modes are enabled by setting the appropriate configuration of the JESD204B_TEST setting (Register 0x202, Bits 3:0). Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer outputs are powered up based on the configuration decimation and DDR settings. The test modes should only be enabled while the JESD204B link is disabled. ADC DDC JESD204B Transport Layer Scrambler JESD204B Link Layer 8b10b Encoder JESD204B TX Active Lanes and Serial Rates Set by D, DDR, and P54 Parameters ADC Test Pattern Enable Long or Short Transport Octet Ramp Test Mode Enable Repeated ILA Modified RPAT Test Mode Enable PRBSn D21.5 K28.5 Serial Outputs High/Low Test Mode Enable Figure 51. Test-Mode Insertion Points 48 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.4.5.3 PRBS Test Modes The PRBS test modes bypass the 8B10B encoder. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150 specification. These bit streams are used with lab test equipment that can selfsynchronize to the bit pattern and therefore the initial phase of the pattern is not defined. The sequences are defined by a recursive equation. For example, the PRBS7 sequence is defined as shown in Equation 9. y[n] = y[n – 6]y[n – 7] where • Bit n is the XOR of bit [n – 6] and bit [n – 7] which are previously transmitted bits (9) Table 35. PBRS Mode Equations PRBS TEST MODE SEQUENCE SEQUENCE LENGTH (bits) PRBS7 y[n] = y[n – 6]y[n – 7] 127 PRBS15 y[n] = y[n – 14]y[n – 15] 32767 PRBS23 y[n] = y[n – 18]y[n – 23] 8388607 The initial phase of the pattern is unique for each lane. 7.4.5.4 Ramp Test Mode In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the input from the formatter is ignored. After the ILA sequence, each lane transmits an identical octet stream that increments from 0x00 to 0xFF and repeats. 7.4.5.5 Short and Long-Transport Test Mode The short-transport test mode is available when the device is operated in DDC bypass mode (decimation = 1). The short transport pattern has a length of one frame. Table 36 lists the formula followed by each sample of the pattern. Table 36. Short Transport Test Pattern Definition BIT 11 10 9 8 7 6 5 ~LID 4 3 2 LID 1 0 SID+1 LID is the lane ID (0 to 7) and SID is the sample number within the frame (0 to 4). The entire pattern has a length of one frame and is listed in Table 37. Table 37. Short Transport Test Pattern LANE (CONVERTER ID) 0 SAMPLE NUMBER (SID) 0 1 2 3 4 0xF01 0xF02 0xF03 0xF04 0xF05 1 0xE11 0xE12 0xE13 0xE14 0xE15 2 0xD21 0xD22 0xD23 0xD24 0xD25 3 0xC31 0xC32 0xC33 0xC34 0xC35 4 0xB41 0xB42 0xB43 0xB44 0xB45 5 0xA51 0xA52 0xA53 0xA54 0xA55 6 0x961 0x962 0x963 0x964 0x965 7 0x871 0x872 0x873 0x874 0x875 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 49 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com The long-transport test mode is available in all DDC modes (decimation > 1). Patterns are generated in accordance with the JESD204B standard and are different for each output format. Table 38 lists one example of the long transport test pattern: Table 38. Long Transport Test Pattern - Decimate-by-4, DDR = 1, P54 = 1, K=10 TIME → CHAR NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Lane 0 0x0003 0x0002 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0003 Lane 1 0x0002 0x0005 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0002 Lane 2 0x0004 0x0002 0x8001 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 Lane 3 0x0004 0x0004 0x8000 0x8001 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 Frame n Frame n+1 Frame n+2 Frame n+3 Frame n+4 Frame n+5 Frame n+6 Frame n+7 Frame n+8 Frame n+9 Frame n + 10 If multiple devices are all programmed to the transport layer test mode (while JESD_EN = 0), then JESD_EN is set to 1, and then SYSREF is used to align the LMFC of the devices, the patterns will be aligned to the SYSREF event (within the skew budget of JESD204B). For more details see JESD204B, section 5.1.6.3. 7.4.5.6 D21.5 Test Mode In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s). 7.4.5.7 K28.5 Test Mode In this test mode, the controller transmits a continuous stream of K28.5 characters. 7.4.5.8 Repeated ILA Test Mode In this test mode, the JESD204B link layer operates normally with one exception: when the ILA sequence completes, the sequence repeats indefinitely. Whenever the receiver issues a synchronization request, the transmitter will initiate code group synchronization. Upon completion of code group synchronization, the transmitter will repeatedly transmit the ILA sequence. If there is no active code group synchronization request at the moment the transmitter enters the test mode, the transmitter will behave as if it received one. 7.4.5.9 Modified RPAT Test Mode A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white spectral content for JESD204B compliance and jitter testing. Table 39 lists the pattern before and after 8b10b encoding. Table 39. Modified RPAT Pattern Values 50 OCTET NUMBER Dx.y NOTATION 8-BIT INPUT TO 8b10b ENCODER 0 D30.5 0xBE 1 D23.6 0xD7 2 D3.1 0x23 3 D7.2 0x47 4 D11.3 0x6B 5 D15.4 0x8F 6 D19.5 0xB3 7 D20.0 0x14 8 D30.2 0x5E 9 D27.7 0xFB 10 D21.1 0x35 11 D25.2 0x59 Submit Documentation Feedback 20b OUTPUT OF 8b10b ENCODER (2 CHARACTERS) 0x86BA6 0xC6475 0xD0E8D 0xCA8B4 0x7949E 0xAA665 Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.5 Programming 7.5.1 Using the Serial Interface The serial interface is accessed using the following four pins: serial clock (SCLK), serial-data in (SDI), serial-data out (SDO), and serial-interface chip-select (SCS). Registers access is enabled through the SCS pin. SCS This signal must be asserted low to access a register through the serial interface. Setup and hold times with respect to the SCLK must be observed. SCLK Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement. SDI Each register access requires a specific 24-bit pattern at this input. This pattern consists of a readand-write (R/W) bit, register address, and register value. The data is shifted in MSB first. Setup and hold times with respect to the SCLK must be observed (see Figure 2). SDO The SDO signal provides the output data requested by a read command. This output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles. Each register access consists of 24 bits, as shown in Figure 2. The first bit is high for a read and low for a write. The next 15 bits are the address of the register that is to be written to. During write operations, the last 8 bits are the data written to the addressed register. During read operations, the last 8 bits on SDI are ignored, and, during this time, the SDO outputs the data from the addressed register. The serial protocol details are illustrated in Figure 52. Single Register Access SCS 1 8 16 17 24 SCLK Command Field SDI R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 Data Field A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Data Field SDO (read mode) Hi Z D7 D6 D5 D4 D3 D2 D1 D0 Hi Z Figure 52. Serial Interface Protocol - Single Read / Write Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 51 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com Programming (continued) 7.5.1.1 Streaming Mode The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends (increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_STATIC bit (register 010h, bit 0). The streaming mode transaction details are shown in Figure 53. Multiple Register Access SCS 8 1 16 17 A0 D7 24 32 25 SCLK Command Field SDI SDO (read mode) R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 Data Field (write mode) A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 Data Field (write mode) D0 D7 D6 D5 D4 Data Field Hi Z D7 D6 D5 D4 D3 D2 D3 D2 D1 D0 Data Field D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Hi Z Figure 53. Serial Interface Protocol - Streaming Read / Write See the Register Map section for detailed information regarding the registers. NOTE The serial interface must not be accessed during calibration of the ADC. Accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. Writing or reading the serial registers also reduces dynamic performance of the ADC for the duration of the register access time. 52 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6 Register Map Several groups of registers provide control and configuration options for this device. Each following register description also shows the power-on reset (POR) state of each control bit. NOTE All multi-byte registers are arranged in little-endian format (the least-significant byte is stored at the lowest address) unless explicitly stated otherwise. Memory Map Address Reset Type Register Standard SPI-3.0 (0x000 to 0x00F) 0x000 0x3C R/W Configuration A Register 0x001 0x002 0x00 R Configuration B Register 0x00 R/W 0x003 0x03 R Chip Type Register 0x004-0x005 Undefined R RESERVED 0x006 0x13 R Chip Version Register 0x007-0x00B Undefined R RESERVED 0x00C-0x00D 0x0451 R Vendor Identification Register 0x00E-0x00F Undefined R RESERVED Device Configuration Register User SPI Configuration (0x010 to 0x01F) 0x010 0x00 R/W 0x011-0x01F Undefined R User SPI Configuration Register RESERVED General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) 0x020 0x9D R/W RESERVED 0x021 0x00 R/W Power-On Reset Register 0x022 0x40 R/W I/O Gain 0 Register 0x023 0x00 R/W I/O Gain 1 Register 0x024 0x00 R/W RESERVED 0x025 0x40 R/W I/O Offset 0 Register 0x026 0x00 R/W I/O Offset 1 Register 0x027 0x06 R/W RESERVED 0x028 0xBA R/W RESERVED 0x029 0xD4 R/W RESERVED 0x02A 0xEA R/W RESERVED 0x02B-0x02F Undefined R RESERVED Clock (0x030 to 0x03F) 0x030 0xC0 R/W Clock Generator Control 0 Register 0x031 0x07 R 0x032 0x80 R/W Clock Generator Control 2 Register 0x033 0xC3 R/W Analog Miscellaneous Register 0x034 0x2F R/W Input Clamp Enable Register 0x035 0xDF R/W RESERVED 0x036 0x00 R/W RESERVED 0x037 0x45 R/W RESERVED 0x038-0x03F Undefined R/W Clock Generator Status Register RESERVED Serializer (0x040 to 0x04F) 0x040 0x04 R/W 0x041-0x04F Undefined R Serializer Configuration Register RESERVED Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 53 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com Register Map (continued) Memory Map (continued) Address Reset Type Register ADC Calibration (0x050 to 0x1FF) 0x050 0x06 R/W Calibration Configuration 0 Register 0x051 0xF4 R/W Calibration Configuration 1 Register 0x052 0x00 R/W RESERVED 0x053 0x5C R/W RESERVED 0x054 0x1C R/W RESERVED 0x055 0x92 R/W RESERVED 0x056 0x20 R/W RESERVED 0x057 0x10 R/W Calibration Background Control Register 0x058 0x00 R/W ADC Pattern and Over-Range Enable Register 0x059 0x00 R/W RESERVED 0x05A 0x00 R/W Calibration Vectors Register 0x05B Undefined R Calibration Status Register 0x05C 0x00 R/W RESERVED 0x05D-0x05E Undefined R/W RESERVED 0x05F 0x00 R/W RESERVED 0x060 Undefined R RESERVED 0x061 Undefined R RESERVED 0x062 Undefined R RESERVED 0x063 Undefined R RESERVED 0x064 Undefined R RESERVED 0x065 Undefined R RESERVED 0x066 0x02 R/W Timing Calibration Register 0x067 0x01 R/W RESERVED 0x068 Undefined R RESERVED 0x069 Undefined R RESERVED 0x06A 0x00 R/W RESERVED 0x06B 0x20 R/W RESERVED 0x06C-0x1FF Undefined R RESERVED Digital Down Converter and JESD204B (0x200-0x27F) 0x200 0x10 R/W Digital Down-Converter (DDC) Control 0x201 0x0F R/W JESD204B Control 1 0x202 0x00 R/W JESD204B Control 2 0x203 0x00 R/W JESD204B Device ID (DID) 0x204 0x00 R/W JESD204B Control 3 0x205 Undefined R/W JESD204B and System Status Register 0x206 0xF2 R/W Overrange Threshold 0 0x207 0xAB R/W Overrange Threshold 1 0x208 0x00 R/W Overrange Period 0x209-0x20B 0x00 R/W RESERVED 0x20C 0x00 R/W DDC Configuration Preset Mode 0x20D 0x00 R/W DDC Configuration Preset Select 0x20E-0x20F 0x0000 R/W Rational NCO Reference Divisor 0x210-0x213 0xC0000000 R/W NCO Frequency (Preset 0) 0x214-0x215 0x0000 R/W NCO Phase (Preset 0) PRESET 0 54 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 Register Map (continued) Memory Map (continued) Address Reset Type 0x216 0xFF R/W DDC Delay (Preset 0) Register 0x217 0x00 R/W RESERVED PRESET 1 0x218-0x21B 0xC0000000 R/W NCO Frequency (Preset 1) 0x21C-0x21D 0x0000 R/W NCO Phase (Preset 1) 0x21E 0xFF R/W DDC Delay (Preset 1) 0x21F 0x00 R/W RESERVED 0x220-0x223 0xC0000000 R/W NCO Frequency (Preset 2) 0x224-0x225 0x0000 R/W NCO Phase (Preset 2) 0x226 0xFF R/W DDC Delay (Preset 2) 0x227 0x00 R/W RESERVED PRESET 2 PRESET 3 0x228-0x22B 0xC0000000 R/W NCO Frequency (Preset 3) 0x22C-0x22D 0x0000 R/W NCO Phase (Preset 3) 0x22E 0xFF R/W DDC Delay (Preset 3) 0x22F 0x00 R/W RESERVED 0x230-0x233 0xC0000000 R/W NCO Frequency (Preset 4) 0x234-0x235 0x0000 R/W NCO Phase (Preset 4) 0x236 0xFF R/W DDC Delay (Preset 4) 0x237 0x00 R/W RESERVED PRESET 4 PRESET 5 0x238-0x23B 0xC0000000 R/W NCO Frequency (Preset 5) 0x23C-0x23D 0x0000 R/W NCO Phase (Preset 5) 0x23E 0xFF R/W DDC Delay (Preset 5) 0x23F 0x00 R/W RESERVED 0x240-0x243 0xC0000000 R/W NCO Frequency (Preset 6) 0x244-0x245 0x0000 R/W NCO Phase (Preset 6) 0x246 0xFF R/W DDC Delay (Preset 6) 0x247 0x00 R/W RESERVED PRESET 6 PRESET 7 0x248-0x24B 0xC0000000 R/W NCO Frequency (Preset 7) 0x24C-0x24D 0x0000 R/W NCO Phase (Preset 7) 0x24E 0xFF R/W DDC Delay (Preset 7) 0x24F-0x251 0x00 R/W RESERVED 0x252-0x27F Undefined R RESERVED 0x0280-0x7FFF Undefined R RESERVED Reserved Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 55 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1 Register Descriptions 7.6.1.1 Standard SPI-3.0 (0x000 to 0x00F) Table 40. Standard SPI-3.0 Registers Address Reset Acronym Register Name 0x000 0x3C CFGA Configuration A Register Section Go 0x001 0x00 CFGB Configuration B Register Go 0x002 0x00 DEVCFG Device Configuration Register Go 0x003 0x03 CHIP_TYPE Chip Type Register Go 0x004-0x005 0x0000 RESERVED RESERVED 0x006 0x13 CHIP_VERSION Chip Version Register 0x007-0x00B Undefined RESERVED RESERVED 0x00C-0x00D 0x0451 VENDOR_ID Vendor Identification Register 0x00E-0x00F Undefined RESERVED RESERVED Go Go 7.6.1.1.1 Configuration A Register (address = 0x000) [reset = 0x3C] All writes to this register must be a palindrome (for example: bits [3:0] are a mirror image of bits [7:4]). If the data is not a palindrome, the entire write is ignored. Figure 54. Configuration A Register (CFGA) 7 SWRST R/W-0 6 RESERVED R/W-0 5 ADDR_ASC R/W-1 4 RESERVED R/W-1 3 RESERVED R/W-1 2 ADDR_ASC R/W-1 1 RESERVED R/W-0 0 SWRST R/W-0 Table 41. CFGA Field Descriptions Bit Field Type Reset Description 7 SWRST R/W 0 Setting this bit causes all registers to be reset to their default state. This bit is self-clearing. 6 RESERVED R/W 0 5 ADDR_ASC R/W 1 This bit is NOT reset by a soft reset (SWRST) 0 : descend – decrement address while streaming (address wraps from 0x0000 to 0x7FFF) 1 : ascend – increment address while streaming (address wraps from 0x7FFF to 0x0000) (default) 4 RESERVED R/W 1 Always returns 1 3 RESERVED R/W 2 ADDR_ASC R/W 1 RESERVED R/W 1100 Palindrome bits bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, bit 0 = bit 7 0 SWRST R/W 7.6.1.1.2 Configuration B Register (address = 0x001) [reset = 0x00] Figure 55. Configuration B Register (CFGB) 7 6 5 4 3 2 1 0 RESERVED R - 0x00h Table 42. CFGB Field Descriptions 56 Bit Field Type Reset 7:0 RESERVED R 0000 0000 Description Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.1.3 Device Configuration Register (address = 0x002) [reset = 0x00] Figure 56. Device Configuration Register (DEVCFG) 7 6 5 4 3 2 1 RESERVED R/W-000000 0 MODE R/W-00 Table 43. DEVCFG Field Descriptions Bit Field Type Reset 7-2 RESERVED R/W 0000 00 1-0 MODE R/W 00 Description SPI 3.0 specification has 1 as low power functional mode and 2 as low power fast resume. This chip does not support these modes. 0: Normal Operation – full power and full performance (default) 1: Normal Operation – full power and full performance (default) 2: Power Down – Everything powered down 3: Power Down – Everything powered down 7.6.1.1.4 Chip Type Register (address = 0x003) [reset = 0x03] Figure 57. Chip Type Register (CHIP_TYPE) 7 6 5 4 3 2 RESERVED R-0000 1 0 CHIP_TYPE R-0011 Table 44. CHIP_TYPE Field Descriptions Bit Field Type Reset 7-4 RESERVED R 0000 3-0 CHIP_TYPE R 0011 Description Always returns 0x3, indicating that the part is a high speed ADC. 7.6.1.1.5 Chip Version Register (address = 0x006) [reset = 0x13] Figure 58. Chip Version Register (CHIP_VERSION) 7 6 5 4 3 CHIP_VERSION R-0001 0011 2 1 0 Table 45. CHIP_VERSION Field Descriptions Bit Field Type Reset 7-0 CHIP_VERSION R 0001 0011 Chip version, returns 0x13 Description Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 57 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451] Figure 59. Vendor Identification Register (VENDOR_ID) 15 14 13 12 11 10 9 8 3 2 1 0 VENDOR_ID R-0x04h 7 6 5 4 VENDOR_ID R-0x51h Table 46. VENDOR_ID Field Descriptions Bit 15-0 Field Type Reset Description VENDOR_ID R 0x0451h Always returns 0x0451 (TI Vendor ID) 7.6.1.2 User SPI Configuration (0x010 to 0x01F) Table 47. User SPI Configuration Registers Address Reset Acronym Register Name 0x010 0x00 USR0 User SPI Configuration Register Section 0x011-0x01F Undefined RESERVED RESERVED Go 7.6.1.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00] Figure 60. User SPI Configuration Register (USR0) 7 6 5 4 RESERVED R/W-0000 000 3 2 1 0 ADDR_STATIC R/W-0 Table 48. USR0 Field Descriptions Bit Field Type Reset 7-1 RESERVED R/W 0000 000 ADDR_STATIC R/W 0 0 58 Description 0 : Use ADDR_ASC bit to define what happens to address during streaming (default). 1 : Address stays static throughout streaming operation. Useful for reading/writing calibration vector information at CAL_VECTOR register. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) Table 49. General Analog, Bias, Band Gap, and Track and Hold Registers Address Reset Acronym Register Name 0x020 0x9D RESERVED RESERVED Section 0x021 0x00 POR Power-On Reset Register Go 0x022 0x40 IO_GAIN_0 I/O Gain 0 Register Go 0x023 0x00 IO_GAIN_1 I/O Gain 1 Register Go 0x024 0x00 RESERVED RESERVED 0x025 0x40 IO_OFFSET_0 I/O Offset 0 Register Go 0x026 0x00 IO_OFFSET_1 I/O Offset 1 Register Go 0x027 0x06 RESERVED RESERVED 0x028 0xBA RESERVED RESERVED 0x029 0xD4 RESERVED RESERVED 0x02A 0xAA RESERVED RESERVED 0x02B-0x02F Undefined RESERVED RESERVED 7.6.1.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00] Figure 61. Power-On Reset Register (POR) 7 6 5 4 RESERVED R/W-0000 000 3 2 1 0 SPI_RES R/W-0 Table 50. POR Field Descriptions Bit Field Type Reset 7-1 RESERVED R/W 0000 000 SPI_RES R/W 0 0 Description Reset all digital. Emulates a power on reset (not self-clearing). Write a 0 and then write a 1 to emulate a reset. Transition from 0—>1 initiates reset. Default: 0 7.6.1.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40] Figure 62. I/O Gain 0 Register (IO_GAIN_0) 7 RESERVED R/W-0 6 GAIN_FS[14] R/W-1 5 GAIN_FS[13] R/W-0 4 GAIN_FS[12] R/W-0 3 GAIN_FS[11] R/W-0 2 GAIN_FS[10] R/W-0 1 GAIN_FS[9] R/W-0 0 GAIN_FS[8] R/W-0 Table 51. IO_GAIN_0 Field Descriptions Bit 7 6-0 Field Type Reset RESERVED R/W 0 GAIN_FS[14:8] R/W 100 0000 Description MSB Bits for GAIN_FS[14:0]. (See the IO_GAIN_1 description in General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)) Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 59 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00] Figure 63. IO_GAIN_1 Register (IO_GAIN_1) 7 GAIN_FS[7] R/W-0 6 GAIN_FS[6] R/W-0 5 GAIN_FS[5] R/W-0 4 GAIN_FS[4] R/W-0 3 GAIN_FS[3] R/W-0 2 GAIN_FS[2] R/W-0 1 GAIN_FS[1] R/W-0 0 GAIN_FS[0] R/W-0 Table 52. IO_GAIN_1 Field Descriptions Bit Field Type Reset 7-0 GAIN_FS[7:0] R/W 0000 0000 LSB bits for GAIN_FS[14:0] GAIN_FS[14:0] Value 0x0000 500 mVp-p 0x4000 725 mVp-p (default) 0x7FFF 950 mVp-p Description 7.6.1.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40] Figure 64. I/O Offset 0 Register (IO_OFFSET_0) 7 RESERVED R/W-0 6 OFFSET_FS[1 4] R/W-1 5 OFFSET_FS[1 3] R/W-0 4 OFFSET_FS[1 2] R/W-0 3 OFFSET_FS[1 1] R/W-0 2 OFFSET_FS[1 0] R/W-0 1 0 OFFSET_FS[9] OFFSET_FS[8] R/W-0 R/W-0 Table 53. IO_OFFSET_0 Field Descriptions Bit 7 6-0 Field Type Reset RESERVED R/W 0 OFFSET_FS[14:8] R/W 100 0000 Description MSB Bits for OFFSET_FS[14:0]. The ADC offset adjust feature has no effect when Background Calibration Mode is enabled. (See IO_OFFSET_1 description in the General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) section). 7.6.1.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00] Figure 65. I/O Offset 1 Register (IO_OFFSET_1) 7 6 5 4 3 2 1 0 OFFSET_FS[7] OFFSET_FS[6] OFFSET_FS[5] OFFSET_FS[4] OFFSET_FS[3] OFFSET_FS[2] OFFSET_FS[1] OFFSET_FS[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 54. IO_OFFSET_1 Field Descriptions 60 Bit Field Type Reset Description 7-0 OFFSET_FS[7:0] R/W 0000 0000 LSB bits for OFFSET_FS[14:0]. OFFSET_FS[14:0] adjusts the offset of the entire ADC (all banks are impacted). OFFSET_FS[14:0] Value 0x0000 –28-mV offset 0x4000 no offset (default) 0x7FFF 28-mV offset The ADC offset adjust feature has no effect when Background Calibration Mode is enabled. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.4 Clock (0x030 to 0x03F) Table 55. Clock Registers Address Reset Acronym Register Name 0x030 0xC0 CLKGEN_0 Clock Generator Control 0 Register Section Go 0x031 0x07 CLKGEN_1 Clock Generator Status Register Go 0x032 0x80 CLKGEN_2 Clock Generator Control 2 Register Go 0x033 0xC3 ANA_MISC Analog Miscellaneous Register Go 0x034 0x2F IN_CL_EN Clamp Enable Register Go 0x035 0xDF RESERVED RESERVED 0x036 0x00 RESERVED RESERVED 0x037 0x45 RESERVED RESERVED 0x038-0x03F Undefined RESERVED RESERVED 7.6.1.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0] Figure 66. Clock Generator Control 0 Register (CLKGEN_0) 7 SysRef_Rcvr_E n R/W-1 6 SysRef_Pr_En 5 SysRefDetClr R/W-1 R/W-0 4 Clear Dirty Capture R/W-0 3 RESERVED R/W-0 2 1 0 DC_LVPECL_C DC_LVPECL_S DC_LVPECL_T LK_en YSREF_en S_en R/W-0 R/W-0 R/W-0 Table 56. CLKGEN_0 Field Descriptions Bit Field Type Reset Description 7 SysRef_Rcvr_En R/W 1 Default: 1 0 : SYSREF receiver is disabled. 1 : SYSREF receiver is enabled (default) 6 SysRef_Pr_En R/W 1 To power down the SYSREF receiver, clear this bit first, then clear SysRef_Rcvr_En. To power up the SYSREF receiver, set SysRef_Rcvr_En first, then set this bit. Default: 1 0 : SYSREF Processor is disabled. 1 : SYSREF Processor is enabled (default) 5 SysRefDetClr R/W 0 Default: 0 Write a 1 and then a 0 to clear the SysRefDet status bit. 4 Clear Dirty Capture R/W 0 Default: 0 Write a 1 and then a 0 to clear the DC status bit. 3 RESERVED R/W 0 Default: 0 2 DC_LVPECL_CLK_en R/W 0 Default: 0 Set this bit if DEVCLK is a DC-coupled LVPECL signal through a 50-Ω resistor. 1 DC_LVPECL_SYSREF_en R/W 0 Default: 0 Set this bit if SYSREF is a DC-coupled LVPECL signal through a 50-Ω resistor. 0 DC_LVPECL_TS_en R/W 0 Default: 0 Set this bit if TimeStamp is a DC-coupled LVPECL signal through a 50-Ω resistor. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 61 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07] Figure 67. Clock Generator Status Register (CLKGEN_1) 7 SysRefDet R-0 6 Dirty Capture R-0 5 4 3 2 1 0 RESERVED R-00 0111 Table 57. CLKGEN_1 Field Descriptions Bit Field Type Reset Description 7 SysRefDet R 0 When high, indicates that a SYSREF rising edge was detected. To clear this bit, write SysRefDetClr to 1 and then back to 0. 6 Dirty Capture R 0 When high, indicates that a SYSREF rising edge occurred very close to the device clock edge, and setup or hold is not ensured (dirty capture). To clear this bit, write CDC to1 and then back to 0. NOTE: When sweeping the timing on SYSREF, it may jump across the clock edge without triggering this bit. The REALIGNED status bit must be used to detect this (see the JESD_STATUS register description in Digital Down Converter and JESD204B (0x200-0x27F)) 5-0 RESERVED R 00 0111 Reserved register. Always returns 000111b 7.6.1.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80] Figure 68. Clock Generator Control 2 Register (CLKGEN_2) 7 6 5 4 3 2 RESERVED R/W-1000 1 0 RDEL R/W-0000 Table 58. CLKGEN_2 Field Descriptions 62 Bit Field Type Reset Description 7-4 RESERVED R/W 1000 Default: 1000b 3-0 RDEL R/W 0000 Adjusts the delay of the SYSREF input signal with respect to DEVCLK. Each step delays SYSREF by 20 ps (nominal) Default: 0 Range: 0 to 15 decimal Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3] Figure 69. Analog Miscellaneous Register (ANA_MISC) 7 6 5 RESERVED R/W-1100 0 4 3 2 SYNC_DIFF_PD R/W-0 1 0 RESERVED R/W-11 Table 59. ANA_MISC Field Descriptions Bit Field Type Reset 7-3 RESERVED R/W 1100 0 SYNC_DIFF_PD R/W 0 Set this bit to power down the differential SYNC~± inputs for the JESD204B interface. The SYNC~± inputs can also serve as the TimeStamp input receiver for the TimeStamp function. The receiver must be powered up to support the time stamp or differential SYNC~. Default: 0b RESERVED R/W 11 Default: 11b 2 1-0 Description 7.6.1.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F] Figure 70. Input Clamp Enable Register (IN_CL_EN) 7 6 RESERVED R/W-00 5 INPUT_CLAMP_EN R/W-1 4 3 2 RESERVED R/W-0 1111 1 0 Table 60. IN_CL_EN Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00 Default: 00b INPUT_CLAMP_EN R/W 1 Set this bit to enable the analog input active clamping circuit. Enabled by default. Default: 1b RESERVED R/W 0 1111 Default: 01111b 5 4-0 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 63 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.5 Serializer (0x040 to 0x04F) Table 61. Serializer Registers Address Reset Acronym Register Name 0x040 0x04 SER_CFG Serializer Configuration Register Section 0x041-0x04F Undefined RESERVED RESERVED Go 7.6.1.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04] Figure 71. Serializer configuration Register (SER_CFG) 7 6 5 4 3 RESERVED R/W-0000 2 1 SERIALIZER PRE-EMPHASIS R/W-0100 0 Table 62. SER_CFG Field Descriptions 64 Bit Field Type Reset 7-4 RESERVED R/W 0000 3-0 SERIALIZER PRE-EMPHASIS R/W 0100 Description Control bits for the pre-emphasis strength of the serializer output driver. Pre-emphasis is required to compensate the low pass behavior of the PCB trace. Default: 4d Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.6 ADC Calibration (0x050 to 0x1FF) Table 63. ADC Calibration Registers Address Reset Acronym Register Name 0x050 0x06 CAL_CFG0 Calibration Configuration 0 Register Section Go 0x051 0xF4 CAL_CFG1 Calibration Configuration 1 Register Go 0x052 0x00 RESERVED RESERVED 0x053 0x5C RESERVED RESERVED 0x054 0x1C RESERVED RESERVED 0x055 0x92 RESERVED RESERVED 0x056 0x20 RESERVED RESERVED 0x057 0x10 CAL_BACK Calibration Background Control Register Go 0x058 0x00 ADC_PAT_OVR_EN ADC Pattern and Over-Range Enable Register Go 0x059 0x00 RESERVED RESERVED 0x05A 0x00 CAL_VECTOR Calibration Vectors Register Go 0x05B Undefined CAL_STAT Calibration Status Register Go 0x05C 0x00 RESERVED RESERVED 0x05D-0x05E Undefined RESERVED RESERVED 0x05F 0x00 RESERVED RESERVED 0x060 Undefined RESERVED RESERVED 0x061 Undefined RESERVED RESERVED 0x062 Undefined RESERVED RESERVED 0x063 Undefined RESERVED RESERVED 0x064 Undefined RESERVED RESERVED 0x065 Undefined RESERVED RESERVED 0x066 0x02 T_CAL Timing Calibration Register 0x067 0x01 RESERVED RESERVED 0x068 Undefined RESERVED RESERVED 0x069 Undefined RESERVED RESERVED 0x06A 0x00 RESERVED RESERVED 0x06B 0x20 RESERVED RESERVED 0x06C-0x1FF Undefined RESERVED RESERVED Go Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 65 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06] Figure 72. Calibration Configuration 0 Register (CAL_CFG0) 7 6 RESERVED R/W-00 5 TIME_STAMP_EN R/W-0 4 CALIBRATION_READ_WRITE_EN R/W-0 3 CAL_SFT R/W-0 2 1 RESERVED R/W-110 0 Table 64. CAL_CFG0 Field Descriptions (1) Bit Field Type Reset 7-6 RESERVED R/W 00 Description 5 TIME_STAMP_EN R/W 0 Enables the capture of the external time stamp signal to allow tracking of input signal. Default: 0 4 CALIBRATION_READ_WRITE_EN R/W 0 Enables the scan register to read or write calibration vectors at register 0x05A. Default: 0 3 CAL_SFT (1) R/W 0 Software calibration bit. Set bit to initiate foreground calibration. This bit is self-clearing. This bit resets the calibration state machine. Most calibration SPI registers are not synchronized to the calibration clock. Changing them may corrupt the calibration state machine. Always set CAL_SFT AFTER making any changes to the calibration registers. 2-0 RESERVED R/W 110 Default: 110 IMPORTANT NOTE: Setting CAL_SFT can glitch internal state machines. The JESD_EN bit must be cleared and then set after setting CAL_SFT. 7.6.1.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4] Figure 73. Calibration Configuration 1 Register (CAL_CFG1) 7 RESERVED R/W-1 6 5 LOW_SIG_EN R/W-111 4 3 2 1 0 RESERVED R/W-0100 Table 65. CAL_CFG1 Field Descriptions Bit Field Type Reset RESERVED R/W 1 6-4 LOW_SIG_EN R/W 111 3-0 RESERVED R/W 0100 7 66 Description Controls signal range optimization for calibration processes. 111: Calibration is optimized for lower amplitude input signals (< –10dBFS). 000: Calibration is optimized for large (-1dBFS) input signals. Default: 111 but recommend 000 for large input signals. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10] Figure 74. Calibration Background Control Register (CAL_BACK) 7 6 5 4 3 2 1 CAL_CONT R/W-0 RESERVED R/W-0001 00 0 CAL_BCK R/W-0 Table 66. CAL_BACK Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0001 00 Set to 0001 00b 1 CAL_CONT R/W 0 CAL_CONT is the only calibration register bit that can be modified while background calibration is ongoing. This bit must be set to 0 before modifying any of the other bits. 0 : Pause or stop background calibration sequence. 1 : Start background calibration sequence. 0 CAL_BCK R/W 0 Background calibration mode enabled. When pausing background calibration leave this bit set, only change CAL_CONT to 0. If CAL_BCK is set to 0 after background calibration has been operation the calibration processes may stop in an incomplete condition. Set CAL_SFT to perform a foreground calibration 7.6.1.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00] Figure 75. ADC Pattern and Over-Range Enable Register (ADC_PAT_OVR_EN) 7 6 5 RESERVED R/W-0000 0 4 3 2 ADC_PAT_EN R/W-0 1 OR_EN R/W-0 0 RESERVED R/W-0 1 0 Table 67. ADC_PAT_OVR_EN Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0000 0 Set to 00000b 2 ADC_PAT_EN R/W 0 Enable ADC test pattern 1 OR_EN R/W 0 Enable over-range output 0 RESERVED R/W 0 Set to 0 7.6.1.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00] Figure 76. Calibration Vectors Register (CAL_VECTOR) 7 6 5 4 3 2 CAL_DATA R/W-0000 0000 Table 68. CAL_VECTOR Field Descriptions Bit Field Type Reset 7-0 CAL_DATA R/W 0000 0000 Repeated reads of this register outputs all the calibration register values for analysis if the CALIBRATION_READ_WRITE_EN bit is set. Repeated writes of this register inputs all the calibration register values for configuration if the CAL_RD_EN bit is set. Description Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 67 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.6.6 Calibration Status Register (address = 0x05B) [reset = undefined] Figure 77. Calibration Status Register (CAL_STAT) 7 6 5 4 RESERVED R-0000 10 3 2 1 CAL_CONT_OFF R-X 0 FIRST_CAL_DONE R-X Table 69. CAL_STAT Field Descriptions Bit Field Type Reset 7-2 RESERVED R 0000 10XX Description 1 CAL_CONT_OFF R X After clearing CAL_CONT, calibration does not stop immediately. Use this register to confirm it has stopped before changing calibration settings. 0: Indicates calibration is running (foreground or background) 1: Indicates that calibration is finished or stopped because CAL_CONT = 0 0 FIRST_CAL_DONE R X Indicates first calibration sequence has been done and ADC is operational. 7.6.1.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02] Figure 78. Timing Calibration Register (T_CAL) 7 6 5 4 RESERVED R/W-0000 001 3 2 1 0 T_AUTO R/W-0 Table 70. CAL_STAT Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0000 001 Set to 0000001b T_AUTO R/W 0 Set to enable automatic timing optimization. Timing calibration will occur once CAL_SFT is set. 0 68 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.7 Digital Down Converter and JESD204B (0x200-0x27F) Table 71. Digital Down Converter and JESD204B Registers Address Reset Acronym Register Name 0x200 0x10 DDC_CTRL1 Digital Down-Converter (DDC) Control Section Go 0x201 0x0F JESD_CTRL1 JESD204B Control 1 Go 0x202 0x00 JESD_CTRL2 JESD204B Control 2 Go 0x203 0x00 JESD_DID JESD204B Device ID (DID) Go 0x204 0x00 JESD_CTRL3 JESD204B Control 3 Go 0x205 Undefined JESD_STATUS JESD204B and System Status Register Go 0x206 0xF2 OVR_T0 Overrange Threshold 0 Go 0x207 0xAB OVR_T1 Overrange Threshold 1 Go 0x208 0x00 OVR_N Overrange Period Go 0x209-0x20B 0x00 RESERVED RESERVED 0x20C 0x00 NCO_MODE DDC Configuration Preset Mode Go 0x20D 0x00 NCO_SEL DDC Configuration Preset Select Go 0x20E-0x20F 0x0000 NCO_RDIV Rational NCO Reference Divisor Go 0x210-0x213 0xC0000000 NCO_FREQ0 NCO Frequency (Preset 0) Go 0x214-0x215 0x0000 NCO_PHASE0 NCO Phase (Preset 0) Go 0x216 0xFF DDC_DLY0 DDC Delay (Preset 0) Go 0x217 0x00 RESERVED RESERVED NCO_FREQ1 NCO Frequency (Preset 1) Go NCO_PHASE1 NCO Phase (Preset 1) Go Go 0x218-0x21B 0xC0000000 0x21C-0x21D 0x0000 0x21E 0xFF DDC_DLY1 DDC Delay (Preset 1) 0x21F 0x00 RESERVED RESERVED 0x220-0x223 0xC0000000 NCO_FREQ2 NCO Frequency (Preset 2) Go 0x224-0x225 0x0000 NCO_PHASE2 NCO Phase (Preset 2) Go 0x226 0xFF DDC_DLY2 DDC Delay (Preset 2) Go 0x227 0x00 RESERVED RESERVED NCO_FREQ3 NCO Frequency (Preset 3) Go NCO_PHASE3 NCO Phase (Preset 3) Go Go 0x228-0x22B 0xC0000000 0x22C-0x22D 0x0000 0x22E 0xFF DDC_DLY3 DDC Delay (Preset 3) 0x22F 0x00 RESERVED RESERVED 0x230-0x233 0xC0000000 NCO_FREQ4 NCO Frequency (Preset 4) Go 0x234-0x235 0x0000 NCO_PHASE4 NCO Phase (Preset 4) Go 0x236 0xFF DDC_DLY4 DDC Delay (Preset 4) Go 0x237 0x00 RESERVED RESERVED NCO_FREQ5 NCO Frequency (Preset 5) Go NCO_PHASE5 NCO Phase (Preset 5) Go Go 0x238-0x23B 0xC0000000 0x23C-0x23D 0x0000 0x23E 0xFF DDC_DLY5 DDC Delay (Preset 5) 0x23F 0x00 RESERVED RESERVED 0x240-0x243 0xC0000000 NCO_FREQ6 NCO Frequency (Preset 6) Go 0x244-0x245 0x0000 NCO_PHASE6 NCO Phase (Preset 6) Go 0x246 0xFF DDC_DLY6 DDC Delay (Preset 6) Go 0x247 0x00 RESERVED RESERVED NCO_FREQ7 NCO Frequency (Preset 7) Go NCO_PHASE7 NCO Phase (Preset 7) Go Go 0x248-0x24B 0xC0000000 0x24C-0x24D 0x0000 0x24E 0xFF DDC_DLY7 DDC Delay (Preset 7) 0x24F-0x251 0x00 RESERVED RESERVED 0x252-0x27F Undefined RESERVED RESERVED Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 69 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.7.1 Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10] Figure 79. Digital Down-Converter (DDC) Control Register (DDC_CTRL1) 7 RESERVED 6 5 SFORMAT R/W-00 R/W-0 4 DDC GAIN BOOST R/W-1 3 2 1 0 DMODE R/W-0000 Table 72. DDC_CTRL1 Field Descriptions Bit Field Type Reset 7-6 RESERVED R/W 00 5 SFORMAT R/W 0 Output sample format for bypass mode: 0 : Offset binary (default) 1 : Signed 2s complement (1) 4 DDC GAIN BOOST R/W 1 0 : Final filter has 0-dB gain (recommended when NCO is set near DC). 1 : Final filter has 6.02-dB gain (default) DMODE (2) R/W 0000 0 : Bypass mode (12-bit output, decimate-by-1, DDC off) (default) 1 : Reserved 2 : decimate-by-4 3 : decimate-by-8 4 : decimate-by-10 5 : decimate-by-16 6 : decimate-by-20 7 : decimate-by-32 8..15 : RESERVED 3-0 (1) (2) Description Decimated modes always output in signed 2s complement. The DMODE setting must only be changed when JESD_EN is 0. 7.6.1.7.2 JESD204B Control 1 Register (address = 0x201) [reset = 0x0F] Figure 80. JESD204B Control 1 Register (JESD_CTRL1) 7 SCR R/W-0 6 5 4 K_Minus_1 R/W-000 11 3 2 1 DDR R/W-1 0 JESD_EN R/W-1 Table 73. JESD_CTRL1 Field Descriptions Bit Field Type Reset Description 7 SCR R/W 0 0 : Scrambler disabled (default) 1 : Scrambler enabled K_Minus_1 R/W 000 11 K is the number of frames per multiframe, and K – 1 is programmed here. Default: K = 4, K_Minus_1 = 3. Depending on the decimation (D) and serial rate (DDR), there are constraints on the legal values of K. 1 DDR R/W 1 0 : SDR serial rate (ƒ(BIT) = ƒS) 1 : DDR serial rate (ƒ(BIT) = 2ƒS) (default) 0 JESD_EN (1) R/W 1 0 : Block disabled 1 : Normal operation (default) 6-2 (1) 70 Before altering any parameters in the JESD_CTRL1 register, you must set JESD_EN to 0. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00] Figure 81. JESD204B Control 2 Register (JESD_CTRL2) 7 P54 R/W-0 6 SYNC_DIFFSEL R/W-0 5 4 RESERVED R/W-00 3 2 1 JESD204B_TEST R/W-0000 0 Table 74. JESD_CTRL2 Field Descriptions Bit Field Type Reset Description 7 P54 R/W 0 0 : Disable 5/4 PLL. Serial bit rate is 1x or 2x based on DDR parameter. 1 : Enable 5/4 PLL. Serial bit rate is 1.25x or 2.5x based on DDR parameter. 6 SYNC_DIFFSEL R/W 0 0 : Use SYNC_SE_N input for SYNC_N function 1 : Use SYNC_DIFF_N input for SYNC_N function R/W 00 Set to 00b R/W 0000 See 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS15 test mode 3 : PRBS23 test mode 4 : Ramp test mode 5 : Short and long transport layer test mode 6 : D21.5 test mode 7 : K28.5 test mode 8 : Repeated ILA test mode 9 : Modified RPAT test mode 10: Serial outputs held low 11: Serial outputs held high 12 through 15 : RESERVED 5-4 RESERVED 3-0 (1) JESD204B_TEST (1) The JESD_CTRL2 register must only be changed when JESD_EN is 0. 7.6.1.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00] Figure 82. JESD204B Device ID (DID) Register (JESD_DID) 7 6 5 4 3 2 1 0 JESD_DID R/W-0000 0000 Table 75. JESD_DID Field Descriptions Bit 7-0 (1) Field JESD_DID (1) Type Reset Description R/W 0000 0000 Specifies the DID value that is transmitted during the second multiframe of the JESD204B ILA. The DID setting must only be changed when JESD_EN is 0. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 71 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00] Figure 83. JESD204B Control 3 Register (JESD_CTRL3) 7 6 5 4 3 2 1 0 RESERVED R/W-0000 00 FCHAR R/W-00 Table 76. JESD_CTRL3 Field Descriptions (1) Bit Field Type Reset 7-2 RESERVED R/W 0000 00 1-0 FCHAR (1) R/W 00 Description Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically according to JESD204B Section 5.3.3.4. When using a JESD204B receiver, always use FCHAR=0. When using a general purpose 8-b or 10-b receiver, the K28.7 character can cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers realign to the false comma. To avoid this, program FCHAR to 1 or 2. 0 : Use K28.7 (default) (JESD204B compliant) 1 : Use K28.1 (not JESD204B compliant) 2 : Use K28.5 (not JESD204B compliant) 3 : Reserved The JESD_CTRL3 register must only be changed when JESD_EN is 0. 7.6.1.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined] See the JESD204B Synchronization Features section for more details. Figure 84. JESD204B and System Status Register (JESD_STATUS) 7 RESERVED R/W-0 6 LINK_UP R/W-0 5 SYNC_STATUS R/W-X 4 REALIGNED R/W-X 3 ALIGNED R/W-0 2 PLL_LOCKED R/W-0 1 0 RESERVED R/W-00 Table 77. JESD_STATUS Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0 Always returns 0 6 LINK_UP R/W 0 When set, indicates that the JESD204B link is in the DATA_ENC state. 5 SYNC_STATUS R/W X Returns the state of the JESD204B SYNC~ signal (SYNC_SE_N or SYNC_DIFF_N). 0 : SYNC~ asserted 1 : SYNC~ deasserted 4 REALIGNED R/W X When high, indicates that the div8 clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit clears it. 3 ALIGNED R/W 0 When high, indicates that the multiframe clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit clears it. 2 PLL_LOCKED R/W 0 When high, indicates that the PLL is locked. RESERVED R/W 0 Always returns 0 1-0 72 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.7.7 Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2] Figure 85. Overrange Threshold 0 Register (OVR_T0) 7 6 5 4 3 2 1 0 OVR_T0 R/W-1111 0010 Table 78. OVR_T0 Field Descriptions Bit Field Type Reset 7-0 OVR_T0 R/W 1111 0010 Over-range threshold 0. This parameter defines the absolute sample level that causes control bit 0 to be set. Control bit 0 is attached to the DDC I output samples. The detection level in dBFS (peak) is 20log10(OVR_T0 / 256) Default: 0xF2 = 242 → –0.5 dBFS Description 7.6.1.7.8 Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB] Figure 86. Overrange Threshold 1 Register (OVR_T1) 7 6 5 4 3 2 1 0 OVR_T1 R/W-1010 1011 Table 79. OVR_T1 Field Descriptions Bit Field Type Reset Description 7-0 OVR_T1 R/W 1010 1011 Overrange threshold 1. This parameter defines the absolute sample level that causes control bit 1 to be set. Control bit 1 is attached to the DDC Q output samples. The detection level in dBFS (peak) is 20log10(OVR_T1 / 256) Default: 0xAB = 171 → –3.5 dBFS 7.6.1.7.9 Overrange Period Register (address = 0x208) [reset = 0x00] Figure 87. Overrange Period Register (OVR_N) 7 6 5 RESERVED R/W-0000 0 4 3 2 1 OVR_N R/W-000 0 Table 80. OVR_N Field Descriptions (1) Bit Field Type Reset 7-3 RESERVED R/W 0000 0 2-0 OVR_N (1) R/W 000 Description This bit adjusts the monitoring period for the OVR[1:0] output bits. The period is scaled by 2OVR_N. Incrementing this field doubles the monitoring period. Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 73 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00] Figure 88. DDC Configuration Preset Mode Register (NCO_MODE) 7 6 5 4 RESERVED R/W-0000 000 3 2 1 0 CFG_MODE R/W-0 Table 81. NCO_MODE Field Descriptions Bit Field Type Reset 7-1 RESERVED R/W 0000 000 0 CFG_MODE R/W 0 Description The NCO frequency and phase are set by the NCO_FREQx and NCO_PHASEx registers, where x is the configuration preset (0 through 7). The DDC delay setting is defined by the DDC_DLYx register. 0 : Use NCO_[2:0] input pins to select the active DDC and NCO configuration preset. 1 : Use the NCO_SEL register to select the active DDC and NCO configuration preset. 7.6.1.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00] Figure 89. DDC Configuration Preset Select Register (NCO_SEL) 7 6 5 RESERVED R/W-0000 0 4 3 2 1 NCO_SEL R/W-000 0 Table 82. NCO_SEL Field Descriptions 74 Bit Field Type Reset 7-3 RESERVED R/W 0000 0 2-0 NCO_SEL R/W 000 Description When NCO_MODE = 1, this register is used to select the active configuration preset. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000] Figure 90. Rational NCO Reference Divisor Register (NCO_RDIV) 15 14 13 12 11 10 9 8 3 2 1 0 NCO_RDIV R/W-0x00h 7 6 5 4 NCO_RDIV R/W-0x00h Table 83. NCO_RDIV Field Descriptions Bit 15-0 Field Type Reset Description NCO_RDIV R/W 0x0000h Sometimes the 32-bit NCO frequency word does not provide the desired frequency step size and can only approximate the desired frequency. This results in a frequency error. Use this register to eliminate the frequency error. Use this equation to compute the proper value to program: NCO_RDIV = ƒS / ƒ(STEP) / 128 where • • ƒS is the ADC sample rate ƒ(STEP) is the desired NCO frequency step size (10) For example, if ƒS= 3072 MHz, and ƒ(STEP) = 10 KHz then: NCO_RDIV = 3072 MHz / 10 KHz / 128 = 2400 (11) Any combination of ƒS and ƒ(STEP) that results in a fractional value for NCO_RDIV is not supported. Values of NCO_RDIV larger than 8192 can degrade the NCO’s SFDR performance and are not recommended. This register is used for all configuration presets. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 75 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 7.6.1.7.13 NCO Frequency (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 91. NCO Frequency (Preset x) Register (NCO_FREQ_x) 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NCO_FREQ_x R/W-0xC0h 23 22 21 20 NCO_FREQ_x R/W-0x00h 15 14 13 12 NCO_FREQ_x R/W-0x00h 7 6 5 4 NCO_FREQ_x R/W-0x00h Table 84. NCO_FREQ_x Field Descriptions Bit 31-0 Field Type Reset Description NCO_FREQ_x R/W 0xC00000 00h Changing this register after the JESD204B interface is running results in non-deterministic NCO phase. If deterministic phase is required, the JESD204B interface must be re-initialized after changing this register. The NCO frequency (ƒ(NCO)) is: ƒ(NCO) = NCO_FREQ_x × 2–32 × ƒS where • • ƒS is the sampling frequency of the ADC NCO_FREQ_x is the integer value of this register (12) This register can be interpreted as signed or unsigned. Use this equation to determine the value to program: NCO_FREQ_x = 232 × ƒ(NCO) / ƒS (13) If the equation does not result in an integer value, you must choose an alternate frequency step (ƒ(STEP) ) and program the NCO_RDIV register. Then use one of the following equations to compute NCO_FREQ_x: NCO_FREQ_x = round(232 × ƒ(NCO) / ƒS) NCO_FREQ_x = round(225 × ƒ(NCO) / ƒ(STEP) / NCO_RDIV) 76 Submit Documentation Feedback (14) (15) Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 7.6.1.7.14 NCO Phase (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 92. NCO Phase (Preset) Register (NCO_PHASE_x) 15 14 13 12 11 NCO_PHASE_x R/W-0x00h 10 9 8 7 6 5 4 2 1 0 3 NCO_PHASE_x R/W-0x00h Table 85. NCO_PHASE_x Field Descriptions Bit 15-0 Field Type Reset Description NCO_PHASE_x R/W 0x0000h This value is MSB-justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is NCO_PHASE_x × 2–16 × 2π (16) This register can be interpreted as signed or unsigned. 7.6.1.7.15 DDC Delay (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 93. DDC Delay (Preset) Register (DDC_DLY_x) 7 6 5 4 3 2 1 0 DDC_DLY_x R/W-0xFFh Table 86. DDC_DLY_x Field Descriptions Bit Field Type Reset Description 7-0 DDC_DLY_x R/W 0xFFh DDC delay for configuration preset 0 This register provides fine adjustments to the DDC group delay. The step size is one half of an ADC sample period (t(DEVCLK) / 2). This is equivalent to Equation 17. tO / (2 × D) where • • tO is the DDC output sample period D is the decimation factor (17) The legal range for this register is 0 to 2D-1. Illegal values result in undefined behavior. Example: When D = 8, the legal register range is 0 to 15. The step size is tO / 16 and the maximum delay is 15 × tO / 16. Programming this register to 0xFF (the default value) powers down and bypasses the fractional delay filter which reduces the DDC latency by 34 ADC sample periods (as compared to the 0 setting). Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 77 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ADC12J4000 device is a wideband sampling and digital tuning device. The ADC input captures input signals from DC to greater than 3 GHz. The DDC performs digital-down conversion and programmable decimation filtering, and outputs complex (15 bit I and 15 bit Q) data. In DDC Bypass Mode (Decimation = 1) the raw 12 bit ADC data is also available. The resulting output data is output on the JESD204B data interface for capture by the downstream capture or processing device. Most frequency-domain applications benefit from DDC capability to select the desired frequency band and provide only the necessary bandwidth of output data, minimizing the required number of data signals. Time domain applications generally require the raw 12-bit ADC output data provided by the DDC bypass feature. 8.2 Typical Application 8.2.1 RF Sampling Receiver An RF Sampling Receiver is used to directly sample a signal in the RF frequency range and provide the data for the captured signal to downstream processing. The wide input bandwidth, high sampling rate, and DDC features of the ADC12J4000 make it ideally suited for this application. SPI Master Over-Range Logic FPGA 1:2 Balun 4.7 nF BPF L Lanes ADC Limiter Diode JESD204B Receiver SYNC~ SYSREF DEVCLK 4.7 nF JESD204B Clock Generator Data Processing and Storage SYSREF and FPGA CLKs Figure 94. Simplified Schematic 78 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 Typical Application (continued) 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 87. Table 87. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Signal center frequency 2500 MHz Signal bandwidth 100 MHz Signal nominal amplitude –7 dBm Signal maximum amplitude 6 dBm Minimum SINAD (in bandwidth of interest) 48 dBc Minimum SFDR (in bandwidth of interest) 60 dBc 8.2.1.2 Detailed Design Procedure Use the following steps to design the RF receiver: • Use the signal-center frequency and signal bandwidth to select an appropriate sampling rate (DEVCLK frequency) and decimate factor (x / 4 to x / 32). • Select the sampling rate so that the band of interest is completely within a Nyquist zone. • Select the sampling rate so that the band of interest is away from any harmonics or interleaving tones. • Use a frequency planning tool, such as the ADC harmonic calculator (see the Development Support section). • Select the decimation factor that provides the highest factor possible with an adequate alias-protected output bandwidth to capture the frequency bandwidth of interest. • Select other system components to provide the needed signal frequency range and DEVCLK rate. • See Table 1 for recommended balun components. • Select bandpass filters and limiter components based on the requirement to attenuate unwanted signals outside the band of interest (blockers) and to prevent large signals from damaging the ADC inputs. See the Absolute Maximum Ratings table. The LMK048xx JESD204B clocking devices can provide the DEVCLK clock and other system clocks for ƒ(DEVCLK) < 3101 MHz. For DEVCLK frequencies up to 4 GHz the consider using the LMX2581 and TRF3765 devices as the DEVCLK source. Use the LMK048xx device to provide the JESD204B clocks. For additional device information, see the Related Documentation section. 8.2.1.3 Application Curves The following curves show an RF signal at 2497.97 MHz captured at a sample rate of 4000 MSPS. Figure 95 shows the spectrum for the full Nyquist band. Figure 96 shows the spectrum for the output data in decimate-by32 mode with ƒ(NCO) equal to 2500 MHz. Figure 96 shows the ability to provide only the spectrum of interest in the decimated output data. Figure 96 also shows how proper selection of the sampling rate can ensure interleaving tones are outside the band of interest and outside the decimated frequency range. Lastly, Figure 96 shows the reduction in the noise floor provided by the processing gain of decimation. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 79 ADC12J4000 www.ti.com 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 -40 -60 -80 -100 -40 -60 -80 -100 -120 0 200 400 600 -120 -62.5 -50 -37.5 -25 -12.5 0 12.5 Frequency (MHz) 800 1000 1200 1400 1600 1800 2000 Frequency (MHz) D001 DDC Bypass Mode FIN = 2497.97 MHz at –7 dBFS ƒS = 4000 MSPS ƒS = 4000 MSPS FIN = 2497.97 MHz at –7 dBFS Figure 95. Spectrum — DDC Bypass Mode 25 37.5 50 62.5 D001 ƒ(NCO) = 2500 MHz Figure 96. Spectrum — Decimate-by-32 8.2.2 Oscilloscope The ADC12J4000 device is equally well-suited for high-speed time-domain applications such as oscilloscopes. The following typical application is for a generic high-speed oscilloscope. Adjustable gain is provided by the frontend resistor ladder and selection mux, and the gain adjustments of the LMH6518 device. Additional gain finetuning can be achieved using the full-scale range adjustment features of the ADC. MEMORY MEMORY MEMORY DISPLAY Display Interface Memory Interface SPI Master 1 nF 900 kŸ 8 Lanes 90 kŸ ADC MUX SYNC~ JFET LNA 10 kŸ DEVCLK 50 Ÿ JESD204 Receiver Data Processing / Storage VCMO SYSREF Hi-Z 50-Ÿ Switch Over-Range Logic LMH6518 Output Amp JESD204 Clock Generator LMH6518 Aux Amp SYSREF and FPGA CLKs Trigger Logic Gain Control + LMH7220 DAC101C085 DAC Figure 97. Simplified Schematic for an Oscilloscope 80 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 8.2.2.1 Design Requirements For this design example, use the parameters listed in Table 88. Table 88. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Maximum sample rate 4000 MSPS Maximum input frequency 1500 MHz 1-dB flat-frequency range 0 to 1000 MHz Signal maximum amplitude 6 dBm Signal minimum amplitude 48 dBc Maximum capture depth 1 million points 8.2.2.2 Detailed Design Procedure Use the following primary steps to design a 12-bit oscilloscope: • Select the desired sampling rate based on the maximum sampling-rate requirement. • Select the input path components (LNA, amplifier, and other components) based on the maximum input frequency and 1-dB flat-frequency range requirements. • Set the attenuation range steps based on the required minimum and maximum values for the signal amplitude. • Select the memory size based on the resolution of the ADC output (12 bits) and the required maximum number of sample points. 8.2.2.3 Application Curves 4000 0 3200 -20 Magnitude (dBFS) Magnitude (LSB) The following curves show the time-domain sample data for a 150-MHz input signal at –1 dBFS, sampled at 4000 MSPS using the ADC12J4000 device. Figure 98 shows the raw time-domain data. Figure 99 shows the spectrum of the captured signal which shows the additional capability of a 12-bit ADC oscilloscope to provide basic spectrum-analysis functions with reasonable performance. 2400 1600 800 -40 -60 -80 0 -100 0 20 40 60 Samples Number (n) FIN = 147.97 MHz at –1 dBFS 80 100 0 200 D001 ƒS = 4000 MSPS 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (MHz) D001 FIN = 149.97 MHz at –1 dBFS Figure 98. Raw Time-Domain Data ƒS = 4000 MSPS Figure 99. Captured Signal Spectrum Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 81 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 8.3 Initialization Set-Up 8.3.1 JESD204B Startup Sequence The JESD204B interface requires a specific startup and alignment sequence. The general order of that sequence is listed in the following steps. 1. Power up or reset the ADC12J4000 device. 2. Program JESD_EN = 0 to shut down the link and enable configuration changes. 3. Program DECIMATE, SCRAM_EN, KM1 and DDR to the desired settings. 4. Configure the device calibration settings as desired, and initiate a calibration (set CAL_SFT = 1). 5. Program JESD_EN = 1 to enable the link. 6. Apply at least one SYSREF rising edge to establish the LMFC phase. 7. Assert SYNC~ from the data receiver to initiate link communications. 8. After the JESD204B receiver has established code group synchronization, SYNC~ is de-asserted and the ILA process begins. 9. Immediately following the end of the ILA sequence normal data output begins. NOTE If deterministic latency is not required this step can be omitted. 8.4 Dos and Don'ts 8.4.1 Common Application Pitfalls Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, an input must not go more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits even on a transient basis can cause faulty, or erratic, operation and can impair device reliability. High-speed digital circuits exhibiting undershoot that goes more than a volt below ground is common. To control overshoot, the impedance of high-speed lines must be controlled and these lines must be terminated in the characteristic impedance. Care must be taken not to overdrive the inputs of the ADC12J4000 device. Such practice can lead to conversion inaccuracies and even to device damage. Incorrect analog input common-mode voltage in the DC-coupled mode. As described in the The Analog Inputs and DC Coupled Input Usage sections, the input common-mode voltage (VCMI) must remain the specified range as referenced to the VCMO pin, which has a variability with temperature that must also be tracked. Distortion performance is degraded if the input common mode voltage is outside the specified VCMI range. Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier to drive the ADC12J4000 device because many high-speed amplifiers have higher distortion than the ADC12J4000 device which results in overall system performance degradation. Driving the clock input with an excessively high level signal. The ADC input clock level must not exceed the level described in the Recommended Operating Conditions table because the input offset can change if these levels are exceeded. Inadequate input clock levels. As described in the Using the Serial Interface section, insufficient input clock levels can result in poor performance. Excessive input-clock levels can result in the introduction of an input offset. Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having other signals coupled to the input clock signal trace. These pitfalls cause the sampling interval to vary which causes excessive output noise and a reduction in SNR performance. Failure to provide adequate heat removal. As described in the Thermal Management section, providing adequate heat removal is important to ensure device reliability. Adequate heat removal is primarily provided by properly connecting the thermal pad to the circuit board ground planes. Multiple vias should be arranged in a grid pattern in the area of the thermal pad. These vias will connect the topside pad to the internal ground planes and to a copper pour area on the opposite side of the printed circuit board. 82 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 9 Power Supply Recommendations Data-converter-based systems draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10-µF capacitor must be placed within one inch (2.5 cm) of the device power pins for each supply voltage. A 0.1-µF capacitor must be placed as close as possible to each supply pin, preferably within 0.5 cm. Leadless chip capacitors are preferred due to their low-lead inductance. As is the case with all high-speed converters, the ADC12J4000 device must be assumed to have little powersupply noise-rejection. Any power supply used for digital circuitry in a system where a large amount of digital power is consumed must not be used to supply power to the ADC12J4000 device. If not a dedicated supply, the ADC supplies must be the same supply used for other analog circuitry. 9.1 Supply Voltage The ADC12J4000 device is specified to operate with nominal supply voltages of 1.9 V (VA19) and 1.2 V (VA12, VD12). For detailed information regarding the operating voltage minimums and maximums see the Recommended Operating Conditions table. During power-up the voltage on all 1.9-V supplies must always be equal to or greater than the voltage on the 1.2V supplies. Similarly, during power-down, the voltage on the 1.2-V supplies must always be lower than or equal to that of the 1.9-V supplies. In general, supplying all 1.9-V buses from a single regulator, and all 1.2-V buses from a single regulator is the easiest method to ensure that the 1.9-V supplies are greater than the 1.2-V supplies. If the 1.2-V buses are generated from separate regulators, they must rise and fall together (within 200 mV). The voltage on a pin, including a transient basis, must not have a voltage that is in excess of the supply voltage or below ground by more than 150 mV. A pin voltage that is higher than the supply or that is below ground can be a problem during startup and shutdown of power. Ensure that the supplies to circuits driving any of the input pins, analog or digital, do not rise faster than the voltage at the ADC12J4000 power pins. The values in the Absolute Maximum Ratings table must be strictly observed including during power up and power down. A power supply that produces a voltage spike at power turnon, turnoff, or both can destroy the ADC12J4000 device. Many linear regulators produce output spiking at power on unless there is a minimum load provided. Active devices draw very little current until the supply voltages reach a few hundred millivolts. The result can be a turn-on spike that destroys the ADC12J4000 device, unless a minimum load is provided for the supply. A 100-Ω resistor at the regulator output provides a minimum output current during power up to ensure that no turn-on spiking occurs. Whether a linear or switching regulator is used, TI recommends using a soft-start circuit to prevent overshoot of the supply. 10 Layout 10.1 Layout Guidelines Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Each ground layer should be a single unified ground plane, rather than splitting the ground planes into analog and digital areas. Because digital switching transients are composed largely of high frequency components, the skin effect dictates that the total ground-plane copper weight has little effect upon the logic-generated noise. Total surface area is more important than the total ground-plane volume. Coupling between the typically-noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that can be impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High-power digital components must not be located on or near any linear component or power-supply trace or plane that services analog or mixed-signal components because the resulting common return current path could cause fluctuation in the analog input ground return of the ADC which causes excessive noise in the conversion result. In general, assume that analog and digital lines must cross each other at 90° to avoid digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The input clock lines must be isolated from all other lines, both analog and digital. The generally-accepted 90° crossing must be avoided because even a same amount of coupling causes problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 83 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com Layout Guidelines (continued) Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques available including distance isolation, orientation planning to prevent field coupling of components like inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at 90° angles to minimize crosstalk. Isolation of the analog input is important because of the low-level drive required of the ADC12J4000 device. Quality analog input signal and clock signal path layout is required for full dynamic performance. Symmetry of the differential signal paths and discrete components in the path is mandatory and symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements of the input and clock signal paths necessitate using differential routing with controlled impedances and minimizing signal path stubs (including vias) when possible. Layout of the high-speed serial-data lines is of particular importance. These traces must be routed as tightly coupled 100-Ω differential pairs, with minimal vias. When vias must be used, care must be taken to implement control-impedance vias (that is, 50-Ω) with adjacent ground vias for image current control. 10.2 Layout Example The following examples show layout-example plots (top and bottom layers only). Figure 102 shows a typical stackup for a 10 layer board. VBG DNC RSV VA12 TDIODE+ TDIODE± VA19 RSV2 VA19 SCS SCLK SDI SDO VD12 DS7+/NCO_2 DS7-/NCO_2 VD12 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 RBIAS+ 1 51 RBIAS± 2 50 DS6±/NCO_1 VCMO 3 49 VD12 VA19 4 48 DS5+/NCO_0 VNEG 5 VA12 6 VA19 7 VIN+ Power supply decoupling capacitors near VIN and DEVCLK are located on opposite side of board to minimize noise coupling. 8 VIN± 9 VA19 10 VA12 11 VNEG 12 47 DS5±/NCO_0 46 VD12 45 DS4+ 44 DS4± 43 VD12 42 DS3+ 41 DS3± 40 VD12 39 DS2+ DS1± 34 VD12 33 DS0+ 32 DS0± 31 VD12 SYNC~ VNEG_OUT VD12 VA19 OR_T1 OR_T0 VA19 SYNC~±/TMST± SYNC~+/TMST+ VA12 30 35 29 DS1+ VA12 17 28 36 27 16 26 VD12 DEVCLK± 25 37 24 15 23 DS2± DEVCLK+ 22 38 21 14 20 VA12 18 13 VA12 DEVCLK path B selected if capacitors installed here. DS6+/NCO_1 VA19 19 Straight analog input path with minimal adjacent circuitry. Power supply decoupling capacitors very close to power pins. SYSREF± Balun transformer for SE to differential conversion. Large bulk decoupling capacitor near device. SYSREF+ Single ended VIN path via balun selected if capacitors installed here. AC coupling capacitors on serial output pairs. Straight DEVCLK path with minimal adjacent circuitry. GND reference vias near where high speed signals transition to inner layer. Figure 100. ADC12J4000 Layout Example 1 — Top Side 84 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 Layout Example (continued) Additional decoupling capacitors near device. Optional differential VIN path selected if capacitors or resistors installed here. VBG DNC RSV VA12 TDIODE+ TDIODE± VA19 RSV2 VA19 SCS SCLK SDI SDO VD12 DS7+/NCO_2 DS7-/NCO_2 VD12 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 RBIAS resistor near to RBIAS+ and RBIAS- pins. RBIAS+ 1 51 RBIAS± 2 50 DS6±/NCO_1 VCMO 3 49 VD12 VA19 4 48 DS5+/NCO_0 VNEG 5 VA12 6 VA19 Decoupling capacitors power pins near VIN and DEVCLK on this side of board. 7 VIN+ 8 VIN± 9 VA19 10 VA12 11 VNEG 12 DS6+/NCO_1 47 DS5±/NCO_0 46 VD12 45 DS4+ 44 DS4± 43 VD12 42 DS3+ 41 DS3± 28 29 30 31 32 33 34 VD12 VNEG_OUT SYNC~ VD12 DS0± DS0+ VD12 27 26 OR_T1 VA19 25 DEVCLK path A selected if capacitors installed here. OR_T0 DS1± 24 35 VA19 DS1+ VA12 17 23 36 SYNC~±/TMST± 16 22 VD12 DEVCLK± 21 37 VA12 15 SYNC~+/TMST+ DS2± DEVCLK+ 20 38 19 14 18 DS2+ VA12 VA12 39 SYSREF± VD12 13 SYSREF+ 40 VA19 Larger bulk decoupling capacitors on this side of board, near device. Figure 101. ADC12J4000 Layout Example 2 — Bottom Side L1 ± SIG 0.0040'' L2 ± GND 0.0067'' L3 ± SIG 0.0060'' L4 ± GND 0.0041'' L5 ± PWR 0.0060'' 0.0578'' L6 ± SIG 0.0067'' L7 ± GND 0.0040'' L8 ± SIG 0.0073'' L9 ± GND 0.0040'' L10 ± SIG 1/2 oz. Copper on L1, L3, L6, L8, L10 1 oz. Copper on L2, L4, L5, L7, L9 100 Differential Signaling on SIG Layers Low loss dielectric adjacent very high speed trace layers Finished thickness 0.0620" including plating and solder mask Figure 102. ADC12J4000 Typical Stackup — 10 Layer Board Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 85 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 10.3 Thermal Management The ADC12J4000 device is capable of impressive speeds and performance at low power levels for speed. However, the power consumption is still high enough to require attention to thermal management. The VQFN package has a primary-heat transfer path through the center pad on the bottom of the package. The thermal resistance of this path is provided as RθJCbot. For reliability reasons, the die temperature must be kept to a maximum of 135°C which is the ambient temperature (TA) plus the ADC power consumption multiplied by the net junction-to-ambient thermal resistance (RθJA). Maintaining this temperature is not a problem if the ambient temperature is kept to a maximum of 85°C as specified in the Recommended Operating Conditions table and the center ground pad on the bottom of the package is thermally connected to a large-enough copper area of the PC board. The package of the ADC12J4000 device has a center pad that provides the primary heat-removal path as well as excellent electrical grounding to the PCB. Recommended land pattern and solder paste examples are provided in the Mechanical, Packaging, and Orderable Information section. The center-pad vias shown must be connected to internal ground planes to remove the maximum amount of heat from the package, as well as to ensure best product parametric performance. If needed to further reduce junction temperature, TI recommends to build a simple heat sink into the PCB which occurs by including a copper area of about 1 to 2 cm2 on the opposite side of the PCB. This copper area can be plated or solder-coated to prevent corrosion, but should not have a conformal coating which would provide thermal insulation. Thermal vias will be used to connect these top and bottom copper areas and internal ground planes. These thermal vias act as heat pipes to carry the thermal energy from the device side of the board to the opposite side of the board where the heat can be more effectively dissipated. 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support For the ADC Harmonic Calculator, got to http://www.ti.com/tool/adc-harmonic-calc. 11.1.3 Device Nomenclature Aperture (sampling) Delay is the amount of delay, measured from the sampling edge of the clock input, after which the signal present at the input pin is sampled inside the device. Aperture Jitter (t(AJ)) is the variation in aperture delay from sample to sample. Aperture jitter appears as input noise. Clock Duty Cycle is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period. Full Power Bandwidth (FPBW) is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below the low frequency value for a full scale input. Interleaving Spurs are frequency domain (FFT) artifacts resulting from non-idealities in the multi-bank interleaved architecture of the ADC. Offset errors between banks result in fixed spurs at ƒS / 4 and ƒS / 2. Gain and timing errors result in input-signal-dependent spurs at ƒS / 4 ± FIN and ƒS / 2 ± FIN. Intermodulation Distortion (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. IMD is defined as the ratio of the power in the second-order and third-order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. 86 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 ADC12J4000 www.ti.com SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 Device Support (continued) Least Significant Bit (LSB ) is the bit that has the smallest value or weight of all bits. This value is calculated with Equation 18. VFS(dif) / 2n where • • VFS(dif) is the differential full-scale amplitude of VI as set by the FSR input (pin 14) n is the ADC resolution in bits, which is 12 for the ADC12J4000 device (18) CML Differential Output Voltage (VOD) is the absolute value of the difference between the positive and negative outputs. Each output is measured with respect to Ground. VD+ VD VOD VD+ VOS VD GND VOD = | VD+ - VD- | Figure 103. CML Output Signal Levels CML Output Offset Voltage (VO(ofs)) is the midpoint between the D+ and D– pins output voltage. Equation 19 is an example of VOS. [(VD+) + ( VD–)] / 2 (19) Most Significant Bit (MSB) is the bit that has the largest value or weight. The value of the MSB is one half of full scale. Overrange Recovery Time is the time required after the differential input voltages goes from ±1.2 V to 0 V for the converter to recover and make a conversion with its rated accuracy. Other Spurs is the sum of all higher harmonics (fourth and above), interleaving spurs, and any other fixed or input-dependent spurs. Data Delay (Latency) is the number of input clock cycles between initiation of conversion and when related data is present at the serializer output. Spurious-free Dynamic Range (SFDR) is the difference, expressed in dB, between the RMS values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC. Total Harmonic Distortion (THD) is the ratio expressed in dB, of the RMS total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated with Equation 20. THD = 20 x log A 2 +... +A 2 f2 f10 A f12 where • • A(f1) is the RMS power of the fundamental (output) frequency A(f2) through A(f10) are the RMS power of the first nine harmonic frequencies in the output spectrum (20) Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency detected at the output and the power in the second harmonic level at the output. Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in the third harmonic level at the output. Word Error Rate is the probability of error and is defined as the probable number of errors per unit of time divided by the number of words seen in that amount of time. A Word Error Rate of 10–18 corresponds to a statistical error in one conversion about every four years. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 87 ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 www.ti.com 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • LMH3401 7-GHz, Ultra-Wideband, Fixed-Gain, Fully-Differential Amplifier, SBOS695 • LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs, SNAS605 • LMX2581 Wideband Frequency Synthesizer with Integrated VCO, SNAS601 • TRF3765 Integer-N/Fractional-N PLL with Integrated VCO, SLWS230 11.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 88 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: ADC12J4000 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) ADC12J4000NKE ACTIVE VQFN NKE 68 168 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC12J4000 ADC12J4000NKER ACTIVE VQFN NKE 68 2000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC12J4000 ADC12J4000NKET ACTIVE VQFN NKE 68 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC12J4000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of