September 2006
ADC12L030/ADC12L032/ADC12L034/ADC12L038
3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
General Description
Features
NOTE: These products are now obsolete.
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The ADC12L030 family is 12-bit plus sign successive approximation A/D converters with serial I/O and configurable
input multiplexers. These devices are fully tested with a
single 3.3V power supply. The ADC12L032, ADC12L034 and
ADC12L038 have 2, 4 and 8 channel multiplexers, respectively. Differential multiplexer outputs and A/D inputs are
available at the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2
pins. The ADC12L030 has a two channel multiplexer with the
multiplexer outputs and A/D inputs internally connected. On
request, these A/Ds go through a self calibration process
that adjusts linearity, zero and full-scale errors to less than
± 1⁄2 LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudodifferential modes. A fully differential unipolar analog input
range (0V to +3.3V) can be accommodated with a single
+3.3V supply. In the differential modes, valid outputs are
obtained even when the negative inputs are greater than the
positive because of the 12-bit plus sign two’s compliment
output data format.
The serial I/O is configured to comply with NSC’s
MICROWIRE™ and Motorola’s SPI standards. For voltage
references, see the LM4040, LM4050 or LM4041 data
sheets.
The ADC12L032 and the ADC12L034 are not recommended
for new designs and are presented for reference only.
0V to 3.3V analog input range with single 3.3V supply
Serial I/O ( MICROWIRE and SPI Compatible)
2 or 8 channel differential or single-ended multiplexer
Power down mode
Programmable acquisition time
Variable digital output word length and format
No zero or full scale adjustment required
Key Specifications
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Resolution
12-bit plus sign conversion time
12-bit plus sign sampling rate
Integral linearity error
Single supply
Power consumption, active
Power consumption, pwr down
12-bit plus sign
8.8 µs (min)
73 kHz (max)
± 1 LSB (max)
3.3V ± 10%
15 mW (max)
40 µW (typ)
Applications
n Portable Medical instruments
n Portable computing
n Portable Test equipment
ADC12L038 Simplified Block Diagram
01183001
COPS™ microcontrollers, HPC™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
Microsoft™ is a trademark of Microsoft Corporation.
© 2006 National Semiconductor Corporation
DS011830
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ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O
A/D Converters with MUX and Sample/Hold
OBSOLETE
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Connection Diagrams
16-Pin Wide Body
SO Package
20-Pin Wide Body
SO Package
01183002
Top View
01183003
* This product is on lifetime buy or obsolete. Shown for reference only.
Top View
28-Pin Wide Body
SO Package
24-Pin Wide Body
SO Package
01183004
* This product is on lifetime buy or obsolete. Shown for reference only.
Top View
01183005
Top View
Ordering Information
Industrial Temperature Range
−40˚C ≤ TA ≤ +85˚C
NS Package
Number
ADC12L030CIWM
M16B
ADC12L032CIWM *
M20B
ADC12L034CIWM *
M24B
ADC12L038CIWM
M28B
* This product is on lifetime buy or obsolete. Shown for reference only.
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2
CCLK
SCLK
DI
DO
EOC
CS
The clock applied to this input controls the successive approximation conversion and the acquisition time. The rise and fall times of the
clock edges should not be longer than 1 µs.
This serial data clock input clocks out the serial
data. The rising edge at this pin loads the information at the DI pin into the multiplexer address
and mode select shift register. This address
controls which channel of the analog input multiplexer (MUX) is selected and the mode of
operation for the A/D. With CS low the falling
edge of SCLK shifts the data resulting from the
previous ADC conversion out at DO, with the
exception of the first bit of data. When CS is low
continuously, the first bit of the data is clocked
out on the rising edge of EOC (end of conversion). When CS is toggled, the falling edge of
CS always clocks out the first bit of data. CS
should be brought low while SCLK is low. The
rise and fall times of the clock edges should not
be longer than 1 µs.
DOR
CONV
This data output ready pin is an active push/pull
output. It is low when the conversion result is
being shifted out and goes high to signal that all
the data has been shifted out.
A logic low is required on this pin to program
any mode or change the ADC’s configuration.
(See the Table 5, Mode Programming). When
this pin is high, the ADC is placed into the read
data only mode. While in this mode, bringing
CS low and pulsing SCLK will only clock out
any data stored in the ADCs output shift register. The data at DI will be neglected, a new
conversion will not be started and the ADC will
remain in the mode and/or configuration previously programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero is in progress.
PD
When this power down pin is high, the A/D is
powered down; when PD is low the A/D is
powered up. The A/D takes a maximum of 700
µs to power up after the command is given.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin (see Tables 2, 3, 4).
The voltage applied to these inputs should not
exceed VA+ or go below GND. Exceeding this
range on an unselected channel will corrupt the
reading of a selected channel.
COM
This analog input pin is used as a pseudo
ground when the analog multiplexer is
single-ended.
MUXOUT1, MUXOUT2
These
are
the
multiplexer
output
pins.
A/DIN1,
A/DIN2
These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied to A/DIN2. If external circuitry is placed
between MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should not
exceed VA+ or go below AGND (see Figure 6 ).
This is the positive analog voltage reference
VREF+
input. In order to maintain accuracy the voltage
range of VREF = (VREF+) − (VREF−) is 1 VDC to
3.3 VDC and VREF+ cannot exceed VA+.
The negative voltage reference input. To mainVREF−
tain accuracy, this voltage must not go below
GND or exceed (VREF+) − 1V. (See Figure 5).
These analog and digital power supply pins are
VA+, VD+
not connected together on the chip and should
be tied to the same power supply but bypassed
separately (see Figure 5 ). The operating voltage range of VA+ and VD+ is 3.0 VDC to 5.5
VDC.
DGND
Digital ground pin (see Figure 5 ).
AGND
Analog ground pin (see Figure 5 ).
The data applied to this serial data input pin is
shifted into the multiplexer address and mode
select register on the rising edge of SCLK.
Tables 2, 3, 4, 5 show the assignment of the
multiplexer address and the mode select data.
This pin is the active push/pull output pin when
CS is Low. When CS is High this output is off
(high impedance). The A/D conversion result
(DB0–DB12) and converter status data are
clocked out on this pin at the falling edge of
SCLK. The word length and format of this result
can vary (see Table 1). The word length and
format are controlled by the data shifted into the
multiplexer address and mode select register
(see Table 5).
This active push/pull output indicates the status
of the ADC. When low the A/D is busy with a
conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC
signals the end of one of these cycles.
When a logic low is applied to this chip select
pin, the rising edge of SCLK shifts the data at
DI into the address register and brings DO out
of the high impedance state. With CS low, the
falling edge of SCLK shifts the data resulting
from the previous ADC conversion out at DO,
with the exception of the first bit of data. When
CS is low continuously, the first bit of the data is
clocked out on the rising edge of EOC (end of
conversion). When CS is toggled the falling
edge of CS always clocks out the first bit of
data. CS should be brought low while SCLK is
low. The falling edge of CS halts a conversion
in progress (the data in the output latches may
be corrupted) and starts the sequence for a
new conversion. Therefore, when CS is brought
low during a conversion in progress the data
output at that time should be ignored. CS may
also be left continuously low, in which case it is
imperative that the correct number of SCLK
cycles be applied to the ADC in order to remain
synchronous. After the ADC supply power is
applied, the ADC expects to see 13 clock
3
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
cycles for each I/O sequence. After that, the
number of clock cycles the ADC expects is the
same as the digital output word length, which
can be modified by the user. See Table 5.
Pin Descriptions
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Absolute Maximum Ratings
Operating Ratings
(Notes 1, 2)
Operating Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6.5V
Voltage at Inputs and Outputs
except CH0–CH7 and COM
GND −5V to V+
+5V
300 mV
± 30 mA
± 120 mA
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
(Note 4)
+3.0V to +5.5V
≤ 100 mV
VREF+
0V to VA+
VREF−
0V to (VREF+ −1V)
1V to VA+
VREF Common Mode Voltage Range
[(VREF+) − (VREF−)] / 2
Voltage at Analog Inputs
|VA+ − VD+|
(V+ = VA+ = VD+)
VREF (VREF+ − VREF−)
−0.3V to V+ +0.3V
CH0–CH7 and COM
TMIN ≤ TA ≤ TMAX
−40˚C ≤ TA ≤ +85˚C
|VA+ − VD+|
Positive Supply Voltage
(V+ = VA+ = VD+)
(Notes 1, 2)
0.1 VA+ to 0.6 VA+
A/DIN1, A/DIN2, MUXOUT1 and
MUXOUT2 Voltage Range
0V to VA+
A/D IN Common Mode Voltage
Range
[(VIN+) − (VIN−)] / 2
0V to VA+
TA = 25˚C
500 mW
Package Thermal Resistance
ESD Susceptibility (Note 5)
Human Body Model
1500V
Thermal
Resistance (θJA)
Part Number
Soldering Information
SO Package (Note 6):
Vapor Phase (60 seconds)
215˚C
Infrared (15 seconds)
220˚C
Storage Temperature
−65˚C to +150˚C
ADC12L030CIWM
70˚C/W
ADC12L032CIWM *
64˚C/W
ADC12L034CIWM *
57˚C/W
ADC12L038CIWM
50˚C/W
* This product is on lifetime buy or obsolete. Shown for
reference only.
Converter Electrical Characteristics
The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed
1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ =
TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12 + sign
Bits (min)
LSB (max)
± 1/2
± 1/2
±1
±1
±2
±2
± 1/2
±2
LSB (max)
±2
±1
± 3.5
LSB (max)
8 + sign
Bits (min)
± 1/2
± 3/4
± 1/2
± 1/2
LSB (max)
8-bit + sign mode after Auto-Zero
VIN(+) = VIN(−) = + 1.250V (Note 13)
± 1/2
LSB (max)
8-bit + sign mode after Auto-Zero
(Notes 12, 13, 14)
± 3/4
LSB (max)
ILE
Integral Linearity Error
After Auto-Cal (Notes 12, 18)
DNL
Differential Non-Linearity
After Auto-Cal
Positive Full-Scale Error
After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error
After Auto-Cal (Notes 12, 18)
Offset Error
After Auto-Cal (Notes 5, 18)
VIN(+) = VIN (−) = 1.250V
DC Common Mode Error
After Auto-Cal (Note 15)
Total Unadjusted Error
After Auto-Cal (Notes 12, 13, 14)
Resolution with No Missing Codes
8-bit + sign mode
INL
Integral Linearity Error
8-bit + sign mode (Note 12)
DNL
Differential Non-Linearity
8-bit + sign mode
Positive Full-Scale Error
8-bit + sign mode (Note 12)
Negative Full-Scale Error
8-bit + sign mode (Note 12)
Offset Error
Total Unadjusted Error
TUE
TUE
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4
± 1/2
LSB (max)
LSB (max)
LSB (max)
LSB
LSB (max)
LSB (max)
LSB (max)
(Continued)
The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed
1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ =
TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
± 0.05
Multiplexer Chan-to-Chan Matching
LSB
V+ = +3.3V ± 10%
Power Supply Sensitivity
± 0.5
± 0.5
± 0.5
± 0.5
Offset Error
+ Full-Scale Error
− Full-Scale Error
Integral Linearity Error
±1
± 1.5
± 1.5
LSB (max)
LSB (max)
LSB (max)
LSB
Output Data from
“12-Bit Conversion of Offset”
(see Table 5)
(Note 20)
+10
−10
LSB (max)
LSB (min)
Output Data from
“12-Bit Conversion of Full-Scale”
(see Table 5)
(Note 20)
4095
4093
LSB (max)
LSB (min)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
fIN = 1 kHz, VIN = 2.5 VP-P
69.4
dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = 2.5 VP-P
68.3
dB
fIN = 40 kHz, VIN = 2.5 VPP
65.7
dB
31
kHz
−3 dB Full Power Bandwidth
VIN = 2.5 VP-P, where S/(N+D) drops 3 dB
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
fIN = 1 kHz, VIN = ± 2.5V
77.0
dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = ± 2.5V
73.9
dB
fIN = 40 kHz, VIN = ± 2.5V
67.0
dB
40
kHz
−3 dB Full Power Bandwidth
VIN = ± 2.5V, where S/(N+D) drops 3 dB
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
CREF
Reference Input Capacitance
85
pF
CA/D
A/DIN1 and A/DIN2 Analog Input
Capacitance
75
pF
A/DIN1 and A/DIN2 Analog Input
Leakage Current
VIN = +3.3V or VIN = 0V
± 0.1
CH0–CH7 and COM Input Voltage
CCH
CH0–CH7 and COM Input
Capacitance
On Channel Leakage (Note 16)
CH0–CH7 and COM Pins
MUXOUT1 and MUXOUT2 Leakage
Current
RON
µA (max)
GND − 0.05
VA+ + 0.05
V (min)
V (max)
10
CMUXOUT MUX Output Capacitance
Off Channel Leakage (Note 16)
CH0–CH7 and COM Pins
± 1.0
pF
20
pF
On Channel = 3.3V and Off Channel = 0V
−0.01
−0.3
µA (min)
On Channel = 0V and Off Channel = 3.3V
0.01
0.3
µA (max)
On Channel = 3.3V and Off Channel = 0V
0.01
0.3
µA (max)
On Channel = 0V and Off Channel = 3.3V
−0.01
−0.3
µA (min)
VMUXOUT = 3.3V or VMUXOUT = 0V
0.01
0.3
µA (max)
1900
Ω (max)
MUX On Resistance
VIN = 1.65V and VMUXOUT = 1.55V
1300
RON Matching Channel to Channel
VIN = 1.65V and VMUXOUT = 1.55V
5
%
Channel-to-Channel Crosstalk
VIN = 3.3 VP-P, fIN = 40 kHz
−72
dB
90
kHz
MUX Bandwidth
5
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Converter Electrical Characteristics
ADC12L030/ADC12L032/ADC12L034/ADC12L038
DC and Logic Electrical Characteristics
The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed
1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ =
TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9)
Symbol
Parameter
Typical
(Note 10)
Conditions
Limits
(Note 11)
Units
(Limits)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
V+ = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
V+ = 3.0V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
0.005
1.0
µA (max)
IIN(0)
Logical “0” Input Current
VIN = 0V
−0.005
−1.0
µA (min)
V+ = 3.0V, IOUT = −360 µA
2.4
V (min)
V+ = 3.0V, IOUT = − 10 µA
2.9
V (min)
V+ = 3.0V, IOUT = 1.6 mA
0.4
V (max)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
IOUT
TRI-STATE Output Current
VOUT = 0V
−0.1
−3.0
µA (max)
VOUT = 3.3V
0.1
3.0
µA (max)
+ISC
Output Short Circuit Source Current
VOUT = 0V
14
6.5
mA (min)
−ISC
Output Short Circuit Sink Current
VOUT = VD+
16
8.0
mA (min)
Awake
1.1
1.5
mA (max)
CS = HIGH, Powered Down, CCLK on
600
POWER SUPPLY CHARACTERISTICS
ID+
IA+
IREF
Digital Supply Current
Positive Analog Supply Current
Reference Input Current
CS = HIGH, Powered Down, CCLK off
12
Awake
2.2
µA
µA
3.0
mA (max)
CS = HIGH, Powered Down, CCLK on
10
µA
CS = HIGH, Powered Down, CCLK off
0.1
µA
Awake
70
µA
CS = HIGH, Powered Down
0.1
µA
AC Electrical Characteristics
The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input
with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 17)
Symbol
fCK
fSK
Parameter
Conditions
Conversion Clock (CCLK) Frequency
Typical
(Note 10)
Limits (Note 11)
Units (Limits)
10
5
MHz (max)
5
MHz (max)
1
10
Serial Data Clock SCLK Frequency
0
Conversion Clock Duty Cycle
Serial Data Clock Duty Cycle
12-Bit + Sign or 12-Bit
tC
Conversion Time
8-Bit + Sign or 8-Bit
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MHz (min)
6
44(tCK)
21(tCK)
Hz (min)
40
% (min)
60
% (max)
40
% (min)
60
% (max)
44(tCK)
(max)
8.8
µs (max)
21(tCK)
(max)
4.2
µs (max)
(Continued)
The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input
with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
6(tCK)
6 Cycles Programmed
10(tCK)
10 Cycles Programmed
tA
Acquisition Time (Note 19)
18(tCK)
18 Cycles Programmed
34(tCK)
34 Cycles Programmed
tCAL
Self-Calibration Time
tAZ
Auto-Zero Time
tSYNC
Self-Calibration or Auto-Zero
Synchronization Time from DOR
tDOR
DOR High Time when CS is Low
Continuously for Read Data and
Software Power Up/Down
4944(tCK)
76(tCK)
2(tCK)
9(tSK)
Units (Limits)
6(tCK)
(min)
7(tCK)
(max)
1.2
µs (min)
1.4
µs (max)
10(tCK)
(min)
11(tCK)
(max)
2.0
µs (min)
2.2
µs (max)
18(tCK)
(min)
19(tCK)
(max)
3.6
µs (min)
3.8
µs (max)
34(tCK)
(min)
35(tCK)
(max)
6.8
µs (min)
7.0
µs (max)
4944(tCK)
(max)
988.8
µs (max)
76(tCK)
(max)
15.2
µs (max)
2(tCK)
(min)
3(tCK)
(max)
0.40
µs (min)
0.60
µs (max)
9(tSK)
(max)
1.8
µs (max)
8(tSK)
(max)
1.6
µs (max)
250
700
µs (max)
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to EOC
Rising Edge
500
700
µs (max)
tACC
Access Time Delay from CS Falling
Edge to DO Data Valid
25
60
ns (max)
tSET-UP
Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge
50
ns (min)
tDELAY
Delay from SCLK Falling Edge to CS
Falling Edge
0
5
ns (min)
t1H, t0H
Delay from CS Rising Edge to DO
TRI-STATE ®
70
100
ns (max)
tHDI
DI Hold Time from Serial Data Clock
Rising Edge
5
15
ns (min)
tSDI
DI Set-Up Time from Serial Data Clock
Rising Edge
5
10
ns (min)
tCONV
CONV Valid Data Time
tHPU
Hardware Power-Up Time, Time from
PD Falling Edge to EOC Rising Edge
tSPU
8(tSK)
Limits (Note 11)
RL = 3k, CL = 100 pF
7
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
AC Electrical Characteristics
ADC12L030/ADC12L032/ADC12L034/ADC12L038
AC Electrical Characteristics
(Continued)
The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input
with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits (Note 11)
Units (Limits)
RL = 3k, CL = 100 pF
35
65
5
ns (max)
ns (min)
50
90
ns (max)
tHDO
DO Hold Time from Serial Data Clock
Falling Edge
tDDO
Delay from Serial Data Clock Falling
Edge to DO Data Valid
tRDO
DO Rise Time, TRI-STATE to High DO
Rise Time, Low to High
RL = 3k, CL = 100 pF
10
40
ns (max)
tFDO
DO Fall Time, TRI-STATE to Low DO
Fall Time, High to Low
RL = 3k, CL = 100 pF
15
15
40
40
ns (max)
ns (max)
tCD
Delay from CS Falling Edge to DOR
Falling Edge
50
80
ns (max)
tSD
Delay from Serial Data Clock Falling
Edge to DOR Rising Edge
45
80
ns (max)
CIN
Capacitance of Logic Inputs
10
pF
COUT
Capacitance of Logic Outputs
20
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+ or VD+), the current at that pin should be limited to 20 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJ max = 150˚C.
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be ≤3.05
VDC to ensure accurate conversions.
01183006
Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V+
pin.
Note 9: With the test condition for VREF (VREF+ − VREF−) given as +2.500V the 12-bit LSB is 610 µV and the 8-bit LSB is 9.8 mV.
Note 10: Typical figures are at TJ = TA = 25˚C and represent most likely parametric norm.
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see Figure 4).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
www.national.com
8
(Continued)
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 18: The ADC12L030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
01183007
FIGURE 1. Transfer Characteristic
01183008
FIGURE 2. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles
9
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
AC Electrical Characteristics
ADC12L030/ADC12L032/ADC12L034/ADC12L038
AC Electrical Characteristics
(Continued)
01183009
FIGURE 3. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle
01183010
FIGURE 4. Offset or Zero Error Voltage
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10
Linearity Error Change
vs. Temperature
Full-Scale Error Change
vs. Temperature
01183051
01183052
Full-Scale Error Change
vs. Supply Voltage
Zero Error Change
vs. Temperature
01183053
01183054
Zero Error Change
vs. Supply Voltage
Analog Supply Current
vs. Temperature
01183055
01183056
11
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after autocalibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9)
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note
9) (Continued)
Digital Supply Current
vs. Temperature
01183057
Test Circuits
DO “TRI-STATE” (t1H, t0H)
DO except “TRI-STATE”
01183015
01183016
Leakage Current
01183017
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12
DO “TRI-STATE” Falling and Rising Edge
DO Falling and Rising Edge
01183019
01183018
DI Data Input Timing
01183020
DO Data Output Timing Using CS
01183021
DO Data Output Timing with CS Continuously Low
01183022
13
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
ADC12L038 Auto-Cal or Auto-Zero
01183023
Note: DO output data is not valid during this cycle.
ADC12L038 Read Data without Starting a Conversion Using CS
01183024
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14
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
ADC12L038 Read Data without Starting a Conversion with CS Continuously Low
01183025
ADC12L038 Conversion Using CS with 8-Bit Digital Output Format
01183026
15
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
ADC12L038 Conversion Using CS with 16-Bit Digital Output Format
01183027
ADC12L038 Conversion with CS Continuously Low and 8-Bit Digital Output Format
01183028
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16
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
ADC12L038 Conversion with CS Continuously Low and 16-Bit Digital Output Format
01183029
ADC12L038 Software Power Up/Down Using CS with 16-Bit Digital Output Format
01183030
17
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
ADC12L038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format
01183031
ADC12L038 Hardware Power Up/Down
01183032
Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will
be stored in the output shift register.
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18
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
ADC12L038 Configuration Modification — Example of a Status Read
01183033
Note: In order for all 9 bits of status information to be accessible the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign,
12 bits, 12 bits plus sign, or greater.
01183035
*Tantalum
**Monolithic Ceramic or better
FIGURE 5. Recommended Power Supply Bypassing and Grounding
19
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Timing Diagrams
(Continued)
01183034
FIGURE 6. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins
Format and Set-Up Tables
TABLE 1. Data Out Formats
DO Formats
17 Bits
with
Sign
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16
X
X
10
9
8
7
6
5
4
MSB 13 Bits Sign MSB
First
MSB
9 Bits Sign
10
9
8
7
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
17 Bits LSB
1
2
3
4
5
6
7
8
9
10
MSB Sign
13 Bits LSB
1
2
3
4
5
6
7
8
9
10
MSB Sign
9 Bits LSB
1
2
3
4
5
6
16 Bits
0
0
0
MSB
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
1
2
3
4
5
6
7
8
9
10
MSB
1
2
3
4
5
6
7
8
9
10
MSB
1
2
3
4
5
6
MSB
LSB
First
X
0
MSB
12 Bits MSB
First
8 Bits MSB
without
Sign
16 Bits LSB
LSB
12 Bits LSB
First
8 Bits LSB
X
Sign MSB
X = High or Low state.
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20
3
2
1
LSB
X
X
X
X
3
2
1
LSB
0
0
0
0
MSB Sign
(Continued)
TABLE 2. ADC12L038 Multiplexer Addressing
Analog Channel Addressed and Assignment
with A/DIN1 tied to MUXOUT1 and A/DIN2
tied to MUXOUT2
MUX Address
A/D Input
Polarity
Assignment
Multiplexer Output
Channel
Assignment
Mode
DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
+
−
+
−
+
−
+
−
−
+
−
+
−
+
−
+
+
+
+
+
+
+
+
+
+
−
CH0
CH1
+
−
CH2
CH3
+
−
CH4
CH5
+
−
CH6
CH7
−
+
CH0
CH1
−
+
CH2
CH3
−
+
CH4
CH5
−
+
CH6
CH7
−
+
−
CH0
COM
−
+
−
CH2
COM
−
+
−
CH4
COM
−
+
−
CH6
COM
−
+
−
CH1
COM
−
+
−
CH3
COM
−
+
−
CH5
COM
−
+
−
CH7
COM
Differential
Single-Ended
TABLE 3. ADC12L034 Multiplexer Addressing
Analog Channel Addressed and
Assignment with A/DIN1 tied to
MUXOUT1 and A/DIN2 tied to
MUXOUT2
A/D Input Polarity
Assignment
DI2
CH0
CH1
A/DIN1
+
−
MUX Address
DI0
DI1
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
−
CH2
CH3
+
−
COM
+
−
+
+
+
+
+
A/DIN2
Multiplexer Output
Channel Assignment
MUXOUT1
MUXOUT2
+
−
CH0
CH1
+
−
CH2
CH3
−
+
CH0
CH1
−
+
CH2
CH3
−
+
−
CH0
COM
−
+
−
CH2
COM
−
+
−
CH1
COM
−
+
−
CH3
COM
21
Mode
Differential
Single-Ended
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Format and Set-Up Tables
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Format and Set-Up Tables
(Continued)
TABLE 4. ADC12L032 and ADC12L030 Multiplexer Addressing
MUX
Address
Analog Channel Addressed and
Assignment with A/DIN1 tied to
MUXOUT1 and A/DIN2 tied to MUXOUT2
A/D Input Polarity
Assignment
COM
Multiplexer Output
Channel Assignment
DI0
DI1
CH0
CH1
A/DIN1
A/DIN2
MUXOUT1
MUXOUT2
L
L
+
−
+
−
CH0
CH1
L
H
−
+
−
+
CH0
CH1
H
L
+
−
+
−
CH0
COM
H
H
−
+
−
CH1
COM
+
Mode
Differential
Single-Ended
The ADC12L030 does not have A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 pins.
TABLE 5. Mode Programming
ADC12L038
DI0
DI1
DI2
ADC12L034
DI0
DI1
DI2
ADC12L030
and
ADC12L032
DI0
DI1
DI3
DI4
DI5
DI6
DI7
DI3
DI4
DI5
DI6
DI2
DI3
DI4
DI5
Mode Selected
(Current)
See Tables 2, 3, 4
L
L
L
L
12 Bit Conversion
12 or 13 Bit MSB First
See Tables 2, 3, 4
L
L
L
H
12 Bit Conversion
16 or 17 Bit MSB First
See Tables 2, 3, 4
L
L
H
L
8 Bit Conversion
8 or 9 Bit MSB First
L
L
H
H
12 Bit Conversion of Full-Scale
12 or 13 Bit MSB First
See Tables 2, 3, 4
L
H
L
L
12 Bit Conversion
12 or 13 Bit LSB First
See Tables 2, 3, 4
L
H
L
H
12 Bit Conversion
16 or 17 Bit LSB First
See Tables 2, 3, 4
L
H
H
L
8 Bit Conversion
8 or 9 Bit LSB First
L
L
L
L
L
L
L
L
L
H
H
H
12 Bit Conversion of Offset
12 or 13 Bit LSB First
L
L
L
L
H
L
L
L
Auto-Cal
No Change
L
L
L
L
H
L
L
H
Auto-Zero
No Change
L
L
L
L
H
L
H
L
Power Up
No Change
L
L
L
L
H
L
H
H
Power Down
No Change
L
L
L
L
H
H
L
L
Read Status Register
No Change
L
L
L
L
H
H
L
H
Data Out without Sign
No Change
H
L
L
L
H
H
L
H
Data Out with Sign
No Change
L
L
L
L
H
H
H
L
Acquisition Time — 6 CCLK Cycles
No Change
No Change
L
H
L
L
H
H
H
L
Acquisition Time — 10 CCLK
Cycles
H
L
L
L
H
H
H
L
Acquisition Time — 18 CCLK
Cycles
No Change
H
H
L
L
H
H
H
L
Acquisition Time — 34 CCLK
Cycles
No Change
L
L
L
L
H
H
H
H
User Mode
No Change
H
Test Mode
(CH1–CH7 become Active
Outputs)
No Change
H
X
X
X
H
H
H
X = Don’t Care
The A/D powers up with no Auto-Cal, no Auto-Zero, 10 CCLK
acquisition time, 12-bit + sign conversion, power up, 12- or
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DO Format
(next Conversion
Cycle)
13-bit MSB first and user mode.
22
(Continued)
TABLE 6. Conversion/Read Data Only Mode Programming
CS
CONV
PD
Mode
L
L
L
See Table 5 for Mode
L
H
L
Read Only (Previous DO Format)
No Conversion
H
X
L
Idle
X
X
H
Power Down
X = Don’t Care
TABLE 7. Status Register
Status Bit
Location
Status Bit
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
PU
PD
Cal
8 or 9
12 or 13
16 or 17
Sign
Justification
Test
Mode
Device Status
“High”
indicates a
Power Up
Function Sequence
is in
progress
“High”
indicates a
Power
Down
Sequence
is in
progress
“High”
indicates
an
Auto-Cal
Sequence
is in
progress
DO Output Format Status
“High”
indicates
an 8 or 9
bit format
“High”
indicates a
12 or 13
bit format
23
“High”
indicates a
16 or 17
bit format
“High”
indicates
that the
sign bit is
included.
When
“Low” the
sign bit is
not
included.
When “High”
the conversion
result will be
output MSB
first. When
“Low” the result
will be output
LSB first.
When
“High” the
device is
in test
mode.
When
“Low” the
device is
in user
mode.
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Format and Set-Up Tables
ADC12L030/ADC12L032/ADC12L034/ADC12L038
another instruction can be transmitted to the A/D. The data
from this conversion can be accessed when the next instruction is issued to the A/D.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize the serial communication to the A/D (see Section 1.3).
Application Information
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The example in Figure 7 shows a typical sequence of events
after the power is applied to the ADC12L030/2/4/8:
1.2 Changing Configuration
The configuration of the ADC12L030/2/4/8 on power up
defaults to 12-bit plus sign resolution, 12- or 13-bit MSB
First, 10 CCLK acquisition time, user mode, no Auto-Cal, no
Auto-Zero, and power up mode. Changing the acquisition
time and turning the sign bit on and off requires an 8-bit
instruction to be issued to the ADC. This instruction will not
start a conversion. The instructions that select a multiplexer
address and format the output data do start a conversion.
Figure 8 describes an example of changing the configuration
of the ADC12L030/2/4/8.
During I/O sequence 1, the instruction at DI configures the
ADC12L030/2/4/8 to do a conversion with 12-bit +sign resolution. Notice that when the 6 CCLK Acquisition and Data
Out without Sign instructions are issued to the ADC, I/O
sequences 2 and 3, a new conversion is not started. The
data output during these instructions is from conversion N
which was started during I/O sequence 1. The Configuration
Modification timing diagram describes in detail the sequence
of events necessary for a Data Out without Sign, Data Out
with Sign, or 6/10/18/34 CCLK Acquisition time mode selection. Table 5 describes the actual data necessary to be input
to the ADC to accomplish this configuration modification. The
next instruction, shown in Figure 8, issued to the A/D starts
conversion N+1 with 8 bits of resolution formatted MSB first.
Again the data output during this I/O cycle is the data from
conversion N.
01183036
FIGURE 7. Typical Power Supply Power Up Sequence
The first instruction input to the A/D via DI initiates Auto-Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto-Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto-Cal procedure modifies the data in the output
shift register. To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word is low Auto-Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data
output at this time is again status information. To keep noise
from corrupting the A/D conversion, the status can not be
read during a conversion. If CS is brought low during a
conversion, that conversion is prematurely ended. EOC can
be used to determine the end of a conversion or the A/D
controller can keep track in software of when it would be
appropriate to communicate to the A/D again. Once it has
been determined that the A/D has completed a conversion
01183037
FIGURE 8. Changing the ADC’s Conversion Configuration
The number of SCLKs applied to the A/D during any conversion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O sequence. The various formats and resolutions available are
shown in Table 1. In Figure 8, since 8-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 8. In the following I/O sequence the format changes to 12-bit without sine
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.
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1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not
doing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below
details out the number of clock periods required for different
24
(PD pin high) the device will remain in the power-down state.
If a software power down instruction is issued to the ADC
while a hardware power up is in effect (PD pin low), the
device will power down. When the device is powered down
by software, it may be powered up by either issuing a
software power up instruction or by taking PD pin high and
then low. If the power down command is issued during an
A/D conversion, that conversion is disrupted. Therefore, the
data output after power up cannot be relied on.
(Continued)
DO formats:
Number of
SCLKs
Expected
DO Format
8-Bit MSB or LSB First
12-Bit MSB or LSB First
16-Bit MSB or LSB first
SIGN OFF
8
SIGN ON
9
SIGN OFF
12
1.6 User Mode and Test Mode
SIGN ON
13
SIGN OFF
16
SIGN ON
17
An instruction may be issued to the ADC to put it into test
mode, which is used by the manufacturer to verify complete
functionality of the device. During test mode CH0–CH7 become active outputs. If the device is inadvertently put into the
test mode with CS low continuously, the serial communications may be desynchronized. Synchronization may be regained by cycling the power supply voltage to the device.
Cycling the power supply voltage will also set the device into
user mode. If CS is used in the serial interface, the ADC may
be queried to see what mode it is in. This is done by issuing
a “read STATUS register” instruction to the ADC. When bit 9
of the status register is high the ADC is in test mode; when
bit 9 is low the ADC is in user mode. As an alternative to
cycling the power supply, an instruction sequence may be
used to return the device to user mode. This instruction
sequence must be issued to the ADC using CS. The following table lists the instructions required to return the device to
user mode. Note that this entire sequence, including both
Test Mode and User Mode values, should be sent to recover
from the test mode.
If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continuously vs. the case when CS is cycled. Take the I/O sequence
detailed in Figure 7 (Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
CS Low
Continuously
CS Strobed
Auto-Cal
13 SCLKs
8 SCLKs
Read Status
13 SCLKs
8 SCLKs
Read Status
13 SCLKs
8 SCLKs
12-Bit + Sign Conv 1
13 SCLKs
8 SCLKs
Instruction
12-Bit + Sign Conv 2
13 SCLKs
13 SCLKs
TEST MODE
H
X
X
X
H
H
H
H
Reset
Test Mode
Instructions
L
L
L
L
H
H
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
H
H
USER MODE
L
L
L
L
H
H
H
H
Power Up
L
L
L
L
H
L
H
L
Set DO with or
without Sign
H
or
L
L
L
L
H
H
L
H
Set Acquisition
Time
H
or
L
H
or
L
L
L
H
H
H
L
Start a
Conversion
H
or
L
H
or
L
H
or
L
H
or
L
L
H
or
L
H
or
L
H
or
L
Instruction
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular A/D conversion (See Tables 2, 3, 4, 5). In
Figure 8 the only times when the channel configuration could
be modified would be during I/O sequences 1, 4, 5 and 6.
Input channels are reselected before the start of each new
conversion. Shown below is the data bit stream required on
DI, during I/O sequence number 4 in Figure 8, to set CH1 as
the positive input and CH0 as the negative input for the
different versions of ADCs:
Part
Number
DI Data
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
ADC12L030
L
H
L
L
H
L
X
X
ADC12L032
L
H
L
L
H
L
X
X
ADC12L034
L
H
L
L
L
H
L
X
ADC12L038
L
H
L
L
L
L
H
L
DI Data
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
X = Don’t Care
1.7 Reading the Data Without Starting a Conversion
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONV line is taken high during the I/O sequence. See the
Read Data timing diagrams. Table 6 describes the operation
of the CONV pin.
Where X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down by taking the PD pin HIGH
or by the instruction input on DI (see Tables 5, 6, and the
Power Up/Down timing diagrams). When the ADC is powered down in this way, the A/D conversion circuitry is deactivated, but the digital I/O circuitry is kept active. Hardware
power up/down is controlled by the state of the PD pin.
Software power up/down is controlled by the instruction
issued to the ADC. If a software power up instruction is
issued to the ADC while a hardware power down is in effect
2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12L038, the analog input multiplexer can be
configured with 4 differential channels or 8 single ended
channels with the COM input as the zero reference or any
combination thereof (see Figure 9 ). The difference between
25
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
CH6 with CH7. The A/DIN1 and A/DIN2 pins can be assigned positive or negative polarity.
With the single-ended multiplexer configuration CH0 through
CH7 can be assigned to the MUXOUT1 pin. The COM pin is
always assigned to the MUXOUT2 pin. A/DIN1 is assigned
as the positive input; A/DIN2 is assigned as the negative
input. (See Figure 10 ).
(Continued)
the voltages on the VREF+ and VREF− pins determines the
input voltage span (VREF). The analog input voltage range is
0 to VA+. Negative digital output codes result when VIN− >
VIN+. The actual voltage at VIN− or VIN+ cannot go below
AGND.
CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as
follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and
The Multiplexer assignment tables for the ADC12L030,2,4,8
(Tables 2, 3, 4) summarize the aforementioned functions for
the different versions of A/Ds.
8 Single-Ended Channels with
COM as Zero Reference
4 Differential Channels
01183038
01183039
FIGURE 9.
Differential Configuration
Single-Ended Configuration
01183040
01183041
A/DIN1 and A/DIN2 can be assigned as the + or − input
A/DIN1 is + input
A/DIN2 is − input
FIGURE 10.
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26
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
(Continued)
01183046
FIGURE 11. Single-Ended Biasing
2.1 Biasing for Various Multiplexer Configurations
Figure 11 is an example of biasing the device for singleended operation. The sign bit is always low. The digital
output range is 0 0000 0000 0000 to 0 1111 1111 1111. One
LSB is equal to 610 µV (2.5V/4096 LSBs).
For pseudo-differential signed operation the biasing circuit
shown in Figure 13 shows a signal AC coupled to the ADC.
This gives a digital output range of −4096 to +4095. With a
1.25V reference, 1 LSB is equal to 305 µV. Although the
ADC is not production tested with a 1.25V reference, linearity error typically will not change more than 0.3 LSB. With the
ADC set to an acquisition time of 10 clock periods the input
biasing resistor needs to be 600Ω or less. Notice though that
the input coupling capacitor needs to be made fairly large to
bring down the high pass corner. Increasing the acquisition
time to 34 clock periods (with a 5 MHz CCLK frequency)
would allow the 600Ω to increase to 6k, which with a 1 µF
coupling capacitor would set the high pass corner at 26 Hz.
The value of R1 will depend on the value of R2.
An alternative method for biasing pseudo-differential operation is to use the +1.25V from the LM4040 to bias any
amplifier circuits driving the ADC as shown in Figure 12. The
value of the resistor pull-up biasing the LM4040-2.5 will
depend upon the current required by the op amp biasing
circuitry.
Fully differential operation is shown in Figure 14. One LSB
for this case is equal to (2.5V/4096) = 610 mV.
01183048
FIGURE 12. Alternative Pseudo-Differential Biasing
27
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
(Continued)
01183047
FIGURE 13. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC
01183050
FIGURE 14. Fully Differential Biasing
tions. For absolute accuracy, where the analog input voltage
varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the
reference inputs. Typically, the reference voltage’s magnitude will require an initial adjustment to null reference voltage induced full-scale errors.
Below are recommended references along with some key
specifications.
3.0 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and
VREF− defines the analog input span (the difference between
the voltage applied between two multiplexer inputs or the
voltage applied to one of the multiplexer inputs and analog
ground), over which 4095 positive and 4096 negative codes
exist. The voltage sources driving VREF+ or VREF− must have
very low output impedance and noise.
The ADC12L030/2/4/8 can be used in either ratiometric or
absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC’s reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA+ and
VREF− is connected to ground. This technique relaxes the
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together.
This maintains the same output code for given input condi-
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Part Number
LM4041CIM3-Adj
LM4040AIM3-2.5
LM4050AIM3-2.5
28
Output
Voltage
Tolerance
Temperature
Coefficient
(max)
± 0.5%
± 0.1%
± 0.1%
± 100ppm/˚C
± 100ppm/˚C
± 50ppm/˚C
Examples are shown in the table below:
(Continued)
The reference voltage inputs are not fully differential. The
ADC12L030/2/4/8 will not generate correct conversions or
comparisons if VREF+ is taken below VREF−. Correct conversions result when VREF+ and VREF− differ by 1V and remain,
at all times, between ground and VA+. The VREF common
mode range, (VREF+ + VREF−)/2, is restricted to (0.1 x VA+) to
(0.6 x VA+). Therefore, with VA+ = 3.3V the center of the
reference ladder should not go below 0.33V or above 1.98V.
Figure 15 is a graphic representation of the voltage restrictions on VREF+ and VREF−.
VREF+
VREF−
VIN+
VIN−
Digital Output
Code
+2.5V
+1V
+1.5V
0V
0,1111,1111,1111
+2.500V
0V
+2V
0V
0,1100,1100,1101
+2.500V
0V
+2.500V
0V
+2.499V +2.500V
0V
1,1111,1111,1111
+2.500V 1,0000,0000,0000
5.0 INPUT CURRENT
At the start of the acquisition window (tA) a charging current
flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux
on resistance is typically 750Ω.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources ( < 600Ω), the input
charging current will decay, before the end of the S/H’s
acquisition time of 2 µs (10 CCLK periods with fC = 5 MHz),
to a value that will not introduce any conversion errors. For
high source impedances, the S/H’s acquisition time can be
increased to 18 or 34 CCLK periods. For less ADC resolution
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (Nc) required for the acquisition time
with a specific source impedance for the various resolutions
the following equations can be used:
12 Bit + Sign NC = [RS + 2.3] x fC x 0.824
8 Bit + Sign NC = [RS + 2.3] x fC x 0.57
Where fC is the conversion clock (CCLK) frequency in MHz
and RS is the external source resistance in kΩ. As an example, operating with a resolution of 12 Bits+sign, a 5 MHz
clock frequency and maximum acquisition time of 34 conversion clock periods the ADC’s analog inputs can handle a
source impedance as high as 6 kΩ. The acquisition time may
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.
An acquisition is started by a falling edge of SCLK and ends
with a rising edge of CCLK (see Timing Diagrams). If SCLK
and CCLK are asynchronous one extra CCLK clock period
may be inserted into the programmed acquisition time for
synchronization. Therefore, with asynchronous SCLK and
CCLK, the acquisition time will change from conversion to
conversion.
01183043
FIGURE 15. VREF Operating Range
4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12L030/2/4/8’s fully differential ADC generate a
two’s complement output that is found by using the equations shown below:
for (12-bit) resolution the Output Code =
for (8-bit) resolution the Output Code =
Round off to the nearest integer value between −4096 to
4095 for 12-bit resolution and between −256 to 255 for 8-bit
resolution if the result of the above equation is not a whole
number.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected
between the analog input pins, CH0–CH7, and analog
ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not degrade the conversion accuracy.
29
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
power supply voltage change significantly. (See the curves
titled “Zero Error Change vs. Ambient Temperature” and
“Zero Error Change vs. Supply Voltage” in the Typical Performance Characteristics.)
(Continued)
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion
errors. Input filtering can be used to reduce the effects of the
noise sources.
14.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the A/D converter’s performance with AC input signals. The important
specifications for AC applications reflect the converter’s ability to digitize AC signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise (S/N), signal-to-noise
+ distortion ratio (S/(N + D)), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter’s capability.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/N
are shown in the table of Electrical Characteristics, and
spectral plots of S/(N + D) are included in the typical performance curves..
9.0 POWER SUPPLIES
Noise spikes on the VA+ and VD+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1 µF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the VA+ and VD+ supplies and placed as
close as possible to these pins.
10.0 GROUNDING
The ADC12L030/2/4/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital areas of the board with analog
and digital components and traces located only in their respective areas. Bypass capacitors of 0.01 µF and 0.1 µF
surface mount capacitors and a 10 µF are recommended at
each of the power supply pins for best performance. These
capacitors should be located as close to the bypassed pin as
practical, especially the smaller value capacitors.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can be
seen in the S/(N + D) versus frequency curves. These curves
will also give an indication of the full power bandwidth (the
frequency at which the S/(N + D) or S/N drops 3 dB).
Effective number of bits can also be useful in describing the
A/D’s noise and distortion performance. An ideal A/D converter will have some amount of quantization noise, determined by its resolution, and no distortion, which will yield an
optimum S/(N + D) ratio given by the following equation:
11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12L030/2/4/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock
signals to the CCLK and SCLK pins. Maintaining a separation of at least 7 to 10 times the height of the clock trace
above its reference plane is recommended.
S/(N + D) = (6.02 x n + 1.76) dB
where "n" is the A/D’s resolution in bits.
Since the ideal A/D converter has no distortion, the effective
bits of a real A/D converter, therefore, can be found by::
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to
stabilize after initial turn on. During the calibration cycle,
correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits. Fullscale error typically changes ± 0.4 LSB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once after
power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).
n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02
As an example, this device with a ± 2.5V, 10 kHz sine wave
input signal will typically have a S/N of 78 dB, which is
equivalent to 12.6 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown below is a schematic for an RS232 interface to any
IBM and compatible PCs. The DTR, RTS, and CTS RS232
signal lines are buffered via level translators and connected
to the ADC12L038’s DI, SCLK, and DO pins, respectively.
The D flip flop drive the CS control line.
13.0 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the A/D,
the auto-zero cycle can be used. It may be necessary to do
an auto-zero cycle whenever the ambient temperature or the
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30
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
(Continued)
01183045
Note: VA+, VD+, and VREF+ on the ADC12L038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF
caps. The DS14C335 has an internal DC-DC converter that generates the necessary TIA/EIA-232-E output levels from a 3.3V supply. There are four 0.47 µF
capacitors required for the DC-DC converter that are not shown in the above schematic.
The assignment of the RS232 port is shown below
COM1
B7
B6
B5
B4
B3
B2
B1
B0
Input Address
3FE
X
X
X
CTS
X
X
X
X
Output Address
3FC
X
X
X
0
X
X
RTS
DTR
A sample program, written in Microsoft™ QuickBasic, is
shown on the next page. The program prompts for data
mode select instruction to be sent to the A/D. This can be
found from the Mode Programming table shown earlier. The
data should be entered in “1”s and “0”s as shown in the table
with DI0 first. Next the program prompts for the number of
SCLKs required for the programmed mode select instruction.
For instance, to send all “0”s to the A/D, selects CH0 as the
+input, CH1 as the −input, 12-bit conversion, and 13-bit MSB
first data output format (if the sign bit was not turned off by a
previous instruction). This would require 13 SCLK periods
since the output data format is 13 bits. The device powers up
with No Auto-Cal, No Auto-Zero, 10 CCLK Acquisition Time,
12-bit conversion, data out with sign, 12- or 13-bit MSB First,
power up, and user mode. Auto-Cal, Auto-Zero, Power UP
and Power Down instructions do not change these default
settings. The following power up sequence should be followed:
1. Run the program
2. Prior to responding to the prompt apply the power to the
ADC12L038
3. Respond to the program prompts
It is recommended that the first instruction issued to the
ADC12L038 be Auto-Cal (see Section 1.1).
31
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Application Information
(Continued)
01183063
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32
ADC12L030/ADC12L032/ADC12L034/ADC12L038
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number ADC12L030CIWM
NS Package Number M16B
Order Number ADC12L032CIWM
NS Package Number M20B
33
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ADC12L030/ADC12L032/ADC12L034/ADC12L038
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Order Number ADC12L034CIWM
NS Package Number M24B
Order Number ADC12L038CIWM
NS Package Number M28B
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34
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ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O
A/D Converters with MUX and Sample/Hold
Notes
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