ADC12L063CIVY/NOPB

ADC12L063 www.ti.com SNAS144E – JULY 2001 – REVISED MARCH 2013 ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold Check for Samples: ADC12L063 FEATURES DESCRIPTION • • • • The ADC12L063 is a monolithic CMOS analog-todigital converter capable of converting analog input signals into 12-bit digital words at 62 Megasamples per second (MSPS), minimum. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. Operating on a single 3.3V power supply, this device consumes just 354 mW at 62 MSPS, including the reference current. The Power Down feature reduces power consumption to just 50 mW. 1 2 Single Supply Operation Low Power Consumption Power Down Mode On-Chip Reference Buffer APPLICATIONS • • • • • • • • Ultrasound and Imaging Instrumentation Cellular Base Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends KEY SPECIFICATIONS • • • • • • • • • • Resolution: 12 Bits Conversion Rate: 62 MSPS (min) Bandwidth: 170 MHz DNL: ±0.5 LSB(typ) INL: ±1.0 LSB(typ) SNR: 66 dB(typ) SFDR: 78 dB(typ) Data Latency: 6 Clock Cycles Supply Voltage: +3.3V ± 300 mV Power Consumption, 62 MHz: 354 mW(typ) The differential inputs provide a full scale input swing equal to ±VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary. This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of −40°C to +85°C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated ADC12L063 SNAS144E – JULY 2001 – REVISED MARCH 2013 www.ti.com Connection Diagram Figure 1. 32-Lead LQFP See NEY0032A Package 2 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L063 ADC12L063 www.ti.com SNAS144E – JULY 2001 – REVISED MARCH 2013 Block Diagram PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit Description ANALOG I/O 2 VIN+ Non-Inverting analog signal Input. With a 1.0V reference voltage the input signal level is 1.0 VP-P. 3 VIN− Inverting analog signal Input. With a 1.0V reference voltage the input signal level is 1.0 VP-P. This pin may be connected to VCM for singleended operation, but a differential input signal is required for best performance. 1 VREF Reference input. This pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. VREF is 1.0V nominal and should be between 0.8V and 1.2V. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L063 3 ADC12L063 SNAS144E – JULY 2001 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol 31 VRP 32 VRM 30 VRN Equivalent Circuit Description These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to AGND. DO NOT connect anything else to these pins. DIGITAL I/O 10 CLK Digital clock input. The range of frequencies for this input is 1 MHz to 70 MHz (typical) with specified performance at 62 MHz. The input is sampled on the rising edge of this input. 11 OE OE is the output enable pin that, when low, enables the TRI-STATE data output pins. When this pin is high, the outputs are in a high impedance state. 8 PD 14–19, 22–27 D0–D11 PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the offset binary output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.1 µF monolithic capacitors located within 1 cm of these power pins, and with a 10 µF capacitor. The ground return for the analog supply. DIGITAL POWER 4 13 VD 9, 12 DGND Positive digital supply pin. This pin should be connected to the same quiet +3.3V source as is VA and bypassed to DGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF capacitor, both located within 1 cm of the power pin. Decouple this pin from the VA pins. The ground return for the digital supply. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L063 ADC12L063 www.ti.com SNAS144E – JULY 2001 – REVISED MARCH 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol 21 Equivalent Circuit VDR 20 Description Positive digital supply pin for the ADC12L063's output drivers. This pin should be connected to a voltage source of +2.5V to VD and bypassed to DR GND with a 0.1 µF monolithic capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF tantalum capacitor. The voltage at this pin should never exceed the voltage on VD. All bypass capacitors should be located within 1 cm of the supply pin. The ground return for the digital supply for the ADC12L063's output drivers. This pin should be connected to the system digital ground, but not be connected in close proximity to the ADC12L063's DGND or AGND pins. See LAYOUT AND GROUNDING for more details. DR GND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) VA, VD, VDR 4.2V ≤ 100 mV |VA–VD| −0.3V to VA or VD +0.3V Voltage on Any Input or Output Pin Input Current at Any Pin Package Input Current (4) ±25 mA (4) ±50 mA Package Dissipation at TA = 25°C See ESD Susceptibility Human Body Model Machine Model Soldering Temperature, Infrared, 10 sec. (6) (3) (4) (5) (6) (7) 2500V (6) 250V (7) 235°C −65°C to +150°C Storage Temperature (1) (2) (5) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA, VD or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 32-pin LQFP, θJA is 79°C/W, so PDMAX = 1,582 mW at 25°C and 823 mW at the maximum operating ambient temperature of 85°C. Note that the power consumption of this device under normal operation will typically be about 374 mW (354 typical power consumption + 20 mW TTL output loading). The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle. Operating Ratings (1) (2) Operating Temperature −40°C ≤ TA ≤ +85°C Supply Voltage (VA, VD) +3.0V to +3.60V Output Driver Supply (VDR) +2.5V to VD VREF Input 0.8V to 1.2V (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L063 5 ADC12L063 SNAS144E – JULY 2001 – REVISED MARCH 2013 www.ti.com Operating Ratings (1)(2) (continued) −0.05V to VD + 0.05V CLK, PD, OE −0V to (VA − 0.5V) VIN Input ≤100mV |AGND–DGND| 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L063 ADC12L063 www.ti.com SNAS144E – JULY 2001 – REVISED MARCH 2013 Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = VDR = +3.3V, PD = 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25°C (1) (2) (3) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes (5) INL Integral Non Linearity DNL Differential Non Linearity GE Gain Error ±1.0 12 Bits ±2.4 LSB(max) ±0.5 LSB(max) Positive Error −0.8 %FS(max) Negative Error +0.1 ±3 %FS(max) +0.1 ±0.9 %FS(max) Under Range Output Code 0 0 Over Range Output Code 4095 4095 Offset Error (VIN+ = VIN−) REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM Common Mode Input Voltage CIN VIN Input Capacitance (each pin to GND) VREF Reference Voltage VIN = 1.0 Vdc + 1 VP-P 1.0 V (CLK LOW) 8 pF (CLK HIGH) 7 (6) 1.00 Reference Input Resistance (1) (2) (3) (4) (5) (6) pF 0.8 V(min) 1.2 V(max) 100 MΩ(min) The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per Note 4 under the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions. See Figure 2 To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2 bandgap voltage reference is recommended for this application. DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD= VDR = +3.3V, PD = 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25°C (1) (2) (3) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) CLK, PD, OE DIGITAL INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage VD = 3.3V 2.0 V(min) VIN(0) Logical “0” Input Voltage VD = 3.0V 0.8 V(max) IIN(1) Logical “1” Input Current VIN+, VIN− = 3.3V IIN(0) Logical “0” Input Current CIN Digital Input Capacitance + − VIN , VIN = 0V 10 µA −10 µA 5 pF D0–D11 DIGITAL OUTPUT CHARACTERISTICS (1) (2) (3) (4) The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per Note 4 under the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions. See Figure 2 To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L063 7 ADC12L063 SNAS144E – JULY 2001 – REVISED MARCH 2013 www.ti.com DC and Logic Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD= VDR = +3.3V, PD = 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25°C (1)(2)(3) Symbol Parameter Conditions VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA Typical (4) Limits (4) Units (Limits) 2.7 V(min) 0.4 V(max) VOUT = 3.3V 100 VOUT = 0V −100 nA nA IOZ TRI-STATE Output Current +ISC Output Short Circuit Source Current VOUT = 0V −20 mA(min) −ISC Output Short Circuit Sink Current VOUT = VDR 20 mA(min) POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND, VREF = 1.0V PD Pin = VDR 102 4 140 mA(max) mA ID Digital Supply Current PD Pin = DGND PD Pin = VDR, fCLK = 0 5.3 2 7 mA(max) mA IDR Digital Output Supply Current PD Pin = DGND, (5) PD Pin = VDR, fCLK = 0