ADC12L066CIVY/NOPB

ADC12L066 www.ti.com SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-andHold Check for Samples: ADC12L066 FEATURES DESCRIPTION • • • • The ADC12L066 is a monolithic CMOS analog-todigital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (Msps), minimum, with typical operation possible up to 80 Msps. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 450 MHz. Operating on a single 3.3V power supply, this device consumes just 357 mW at 66 Msps, including the reference current. The Power Down feature reduces power consumption to just 50 mW. 1 23 Single Supply Operation Low Power Consumption Power Down Mode On-Chip Reference Buffer APPLICATIONS • • • • • • • • Ultrasound and Imaging Instrumentation Cellular Base Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends KEY SPECIFICATIONS • • • • • • • • • Resolution: 12 Bits Conversion Rate: 66 Msps Full Power Bandwidth: 450 MHz DNL: ±0.4 LSB (typ) SNR (fIN = 10 MHz): 66 dB (typ) SFDR (fIN = 10 MHz): 80 dB (typ) Data Latency: 6 Clock Cycles Supply Voltage: +3.3V ± 300 mV Power Consumption, 66 MHz: 357 mW (typ) The differential inputs provide a full scale input swing equal to ±VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary. This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to facilitate the evaluation process. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TRI-STATE is a registered trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated ADC12L066 SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com Connection Diagram Block Diagram 2 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 ADC12L066 www.ti.com SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit Description ANALOG I/O 2 VIN+ 3 VIN− 1 VREF 31 VRP 32 VRM 30 VRN Analog signal Input pins. With a 1.0V reference voltage the differential input signal level is 2.0 VP-P. The VIN- pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. Reference input. This pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. VREF is 1.0V nominal and should be between 0.8V and 1.5V. These pins are high impedance reference bypass pins. Connect a 0.1 µF capacitor from each of these pins to AGND. DO NOT LOAD these pins. DIGITAL I/O 10 11 8 CLK Digital clock input. The range of frequencies for this input is 1 MHz to 80 MHz (typical) with specified performance at 66 MHz. The input is sampled on the rising edge of this input. OE OE is the output enable pin that, when low, enables the TRI-STATE® data output pins. When this pin is high, the outputs are in a high impedance state. PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 3 ADC12L066 SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS and EQUIVALENT CIRCUITS (continued) Pin No. Symbol 14–19, 22–27 D0–D11 Equivalent Circuit Description Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the offset binary output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.1 µF monolithic capacitors located within 1 cm of these power pins, and with a 10 µF capacitor. The ground return for the analog supply. DIGITAL POWER 13 VD 9, 12 DGND 21 20 4 Positive digital supply pin. This pin should be connected to the same quiet +3.3V source as is VA and bypassed to DGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF capacitor, both located within 1 cm of the power pin. The ground return for the digital supply. VDR Positive digital supply pin for the ADC12L066's output drivers. This pin should be connected to a voltage source of +1.8V to VD and bypassed to DR GND with a 0.1 µF monolithic capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF tantalum capacitor. The voltage at this pin should never exceed the voltage on VD by more than 300 mV. All bypass capacitors should be located within 1 cm of the supply pin. DR GND The ground return for the digital supply for the ADC12L066's output drivers. This pin should be connected to the system digital ground, but not be connected in close proximity to the ADC12L066's DGND or AGND pins. See Layout and Grounding for more details. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 ADC12L066 www.ti.com SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) VA, VD, VDR 4.2V ≤ 100 mV |VA–VD| −0.3V to (VA or VD +0.3V) Voltage on Any Pin Input Current at Any Pin (4) Package Input Current ±25 mA (4) ±50 mA Package Dissipation at TA = 25°C See Human Body Model (6) ESD Susceptibility Machine Model 2500V (6) 250V Soldering Temperature, Infrared, 10 sec. (7) 235°C −65°C to +150°C Storage Temperature (1) (2) (3) (4) (5) (6) (7) (5) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA, VD or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX - (TJmax - TA )/θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle. Operating Ratings (1) (2) Operating Temperature −40°C ≤ TA ≤ +85°C Supply Voltage (VA, VD) +3.0V to +3.60V Output Driver Supply (VDR) +1.8V to VD VREF Input 0.8V to 1.5V −0.05V to (VD + 0.05V) CLK, PD, OE −0V to (VA − 0.5V) VIN Input VCM 0.5V to (VA -1.5V) ≤100 mV |AGND–DGND| (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Package Thermal Resistances Package θJA 32-Lead LQFP 79°C / W Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 5 ADC12L066 SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) (4) Symbol Parameter Typical Conditions (4) Limits (4) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes Integral Non Linearity (5) INL DNL GE ±1.2 Differential Non Linearity Gain Error ±0.4 Positive Error −0.15 Negative Error +0.4 12 Bits +2.7 LSB (max) −3 LSB (min) +1 LSB (max) −0.95 LSB (min) ±3 %FS (max) +4 %FS (max) −5 %FS (min) +0.2 ±1.3 %FS (max) Under Range Output Code 0 0 Over Range Output Code 4095 4095 Offset Error (VIN+ = VIN−) REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM Common Mode Input Voltage CIN VIN Input Capacitance (each pin to GND) VREF 1.0 VIN + 1.0 Vdc + 1 VP-P (CLK LOW) 8 (CLK HIGH) 7 Reference Voltage (6) 1.0 Reference Input Resistance 100 0.5 V (min) 1.5 V (max) pF pF 0.8 1.5 V (min) V (max) MΩ (min) (1) The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions. (2) (3) (4) To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for VREF = +1.0V (2 VP-P differential input), the 12-bit LSB is 488 µV. Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Integral Non Linearity is defined as the deviation of the analog value, expressed in LSB, from the straight line that passes through positive and negative full-scale. Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2 bandgap voltage reference is recommended for this application. (5) (6) 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 ADC12L066 www.ti.com SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 Converter Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2)(3)(4) Symbol Parameter Typical Conditions (4) Limits (4) Units (Limits) 64.6 dB (min) 65 dB (min) 64.6 dB (min) DYNAMIC CONVERTER CHARACTERISTICS BW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 450 85°C fIN = 10 MHz, VIN = −0.5 dBFS 25°C 66 −40°C SNR Signal-to-Noise Ratio fIN = 25 MHz, VIN = −0.5 dBFS 65 85°C fIN = 150 MHz, VIN = −6 dBFS 25°C 55 −40°C fIN = 240 MHz, VIN = −6 dBFS 25°C 66 −40°C SINAD Signal-to-Noise & Distortion fIN = 25 MHz, VIN = −0.5 dBFS 25°C 55 −40°C fIN = 240 MHz, VIN = −6 dBFS 25°C Effective Number of Bits fIN = 25 MHz, VIN = −0.5 dBFS 25°C 25°C fIN = 25 MHz, VIN = −0.5 dBFS −80 dB (min) 63 dB (min) dB 51.8 dB (min) 53.9 dB (min) 50 dB (min) dB 10.5 25°C Bits (min) Bits 8.6 Bits (min) Bits −73 dB (max) −73 dB (max) −68 dB (max) −80 85°C −81 −40°C fIN = 240 MHz, VIN = −6 dBFS dB (min) 64.8 8.2 −40°C fIN = 150 MHz, VIN = −6 dBFS 64.3 8.0 85°C Second Harmonic Distortion dB 8.3 8.8 −40°C 2nd Harm dB (min) 10.3 fIN = 240 MHz, VIN = −6 dBFS fIN = 10 MHz, VIN = −0.5 dBFS dB (min) 51 10.2 85°C fIN = 150 MHz, VIN = −6 dBFS 54 10.3 10.7 −40°C ENOB dB (min) 51 85°C fIN = 10 MHz, VIN = −0.5 dBFS 52 64 85°C fIN = 150 MHz, VIN = −6 dBFS dB 52 85°C fIN = 10 MHz, VIN = −0.5 dBFS MHz −61 dB −66 dB (max) −66 dB (max) −56 dB (max) dB Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 7 ADC12L066 SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2)(3)(4) Symbol Parameter Typical Conditions (4) 85°C fIN = 10 MHz, VIN = −0.5 dBFS 25°C −84 −40°C 3rd Harm Third Harmonic Distortion fIN = 25 MHz, VIN = −0.5 dBFS 25°C −78 −40°C fIN = 240 MHz, VIN = −6 dBFS 25°C −77 −40°C THD Total Harmonic Distortion fIN = 25 MHz, VIN = −0.5 dBFS 25°C −69 −40°C fIN = 240 MHz, VIN = −6 dBFS 25°C Spurious Free Dynamic Range fIN = 25 MHz, VIN = −0.5 dBFS 8 Submit Documentation Feedback dB (max) dB −68 dB (max) −68 dB (max) −64 dB (max) dB −72 dB (max) −72 dB (max) −66 dB (max) dB −63 dB (max) −63 dB (max) −53 dB (max) dB 73 73 25°C dB (min) dB 66 74 −40°C fIN = 240 MHz, VIN = −6 dBFS dB (max) −71 68 85°C fIN = 150 MHz, VIN = −6 dBFS −74 73 80 −40°C SFDR dB (max) −57 85°C fIN = 10 MHz, VIN = −0.5 dBFS −74 −71 85°C fIN = 150 MHz, VIN = −6 dBFS Units (Limits) −78 85°C fIN = 10 MHz, VIN = −0.5 dBFS (4) −79 85°C fIN = 150 MHz, VIN = −6 dBFS Limits 66 dB (min) 56 61 dB Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC12L066 ADC12L066 www.ti.com SNAS153I – NOVEMBER 2001 – REVISED MARCH 2013 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) (4) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) CLK, PD, OE DIGITAL INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage VD = 3.3V 2.0 V (min) VIN(0) Logical “0” Input Voltage VD = 3.3V 0.8 V (max) IIN(1) Logical “1” Input Current VIN+, VIN− = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN+, VIN− = 0V −10 µA CIN Digital Input Capacitance 5 pF D0–D11 DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA VOUT = 3.3V 100 VDR − 0.18 V (min) 0.4 V (max) nA IOZ TRI-STATE Output Current VOUT = 0V −100 nA +ISC Output Short Circuit Source Current VOUT = 0V −20 mA −ISC Output Short Circuit Sink Current VOUT = 2.5V 20 mA POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND, VREF = 1.0V PD Pin = VDR 103 4 139 mA (max) mA ID Digital Supply Current PD Pin = DGND PD Pin = VDR 5.3 2 6.2 mA (max) mA IDR Digital Output Supply Current PD Pin = DGND, (5) PD Pin = VDR