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ADC141S628Q
SNOI146B – SEPTEMBER 2011 – REVISED NOVEMBER 2017
ADC141S628Q 14-Bit, 200-kSPS, Pseudo-Differential, Micro-Power ADC
1 Features
3 Description
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The ADC141S628Q device is a 14-bit, 200-kSPS,
pseudo-differential, analog-to-digital converter (ADC)
that is AEC-Q100 grade 2 qualified. The converter is
based on a successive-approximation register (SAR)
architecture and has pseudo-differential analog
inputs. The signal path is maintained from the internal
sample-and-hold circuits throughout the ADC to
provide excellent common-mode noise rejection. The
ADC141S628Q features a zero-power track mode
where the ADC is consuming the minimum amount of
supply current while the internal sampling capacitor
tracks the applied analog input voltage.
1
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AEC-Q100 Grade 2 Qualified
14-Bit Resolution With no Missing Codes
Specified Performance Up to 200 kSPS
Pseudo Differential Inputs
Zero-Power Track Mode
±150-mV Swing Around GND on Negative Input
Separate Digital I/O and Analog Supplies
Operating Temperature Range of –40°C to
+105°C
SPI™, QSPI™, Microwire, DSP-Compatible Serial
Interface
Conversion Rate: 50 kSPS to 200 kSPS
INL (–15°C to +65°C): ±0.95 LSB (max)
DNL: ±0.95 LSB (max)
Post Calibration TUE (–15°C to +65°C): ±0.5 mV
(max)
SNR: 80 dBc (min)
THD: –97 dBc (typ)
ENOB: 13.0 Bits (min)
Power Consumption:
– 200 kSPS, 5 V: 4.8 mW (typ)
– Power-Down, 5 V: 13 µW (typ)
2 Applications
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Automotive Battery Management
Automotive Navigation
Portable Systems
Medical Instruments
Instrumentation and Control Systems
Motor Control
Direct Sensor Interface
The serial data output of the ADC141S628Q is
straight binary and is compatible with several
standards, such as SPI, QSPI, Microwire, and many
common DSP serial interfaces. The ADC141S628Q
has no latency which means the conversion result is
clocked out by the serial clock input and is the result
of the conversion currently in progress.
The ADC141S628Q can be operated with
independent analog (VA) and digital input/output
(VIO) supplies. VA and VIO can range from 4.5 V to
5.5 V and can be set independent of each other. This
functionality allows a user to maximize performance
and minimize power consumption. Similarly, the
ADC141S628Q uses an external reference that can
be varied from 1.0 V to VA allowing users to optimize
the full dynamic range of the input. The pseudodifferential input, low power consumption, and small
size make the ADC141S628Q ideal for remote data
acquisition applications.
Operation is specified over the temperature range of
–40°C to +105°C and clock rates of 0.36 MHz to
3.6 MHz. The ADC141S628Q is available in a 10lead package.
Device Information(1)
PART NUMBER
ADC141S628Q
PACKAGE
VSSOP (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pin Out Diagram
V REF
1
10
+IN
2
9
VIO
- IN
3
8
SCLK
GND
4
7
D OUT
GND
5
6
CS
ADC141S628
VA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC141S628Q
SNOI146B – SEPTEMBER 2011 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
7
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
ADC141S628Q Converter Electrical Characteristics 6
ADC141S628Q Timing Requirements ...................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Feature Description................................................. 14
7.3 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 18
9
Power Supply Recommendations...................... 19
8.1 Application Information............................................ 18
9.1 Analog and Digital Power Supplies......................... 19
9.2 Voltage Reference .................................................. 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
22
22
22
22
22
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2011) to Revision B
Page
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information
table, Functional Block Diagram section, Feature Description section, Device Functional Modes section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Changed MSOP to VSSOP throughout document ................................................................................................................ 1
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Changed Pin Out Diagram title from Connection Diagram ................................................................................................... 1
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Deleted Ordering Information table ........................................................................................................................................ 4
•
Added I/O column to Pin Functions table .............................................................................................................................. 4
•
Added maximum specification to Power consumption row of Absolute Maximum Ratings table .......................................... 5
•
Changed footnote 1 of Absolute Maximum Ratings table ...................................................................................................... 5
•
Changed Operating Ratings table title to Recommended Operating Conditions ................................................................... 5
•
Changed Operating temperature range parameter specifications to min and max specifications from –40 ≤ TA ≤ 105
max specification ................................................................................................................................................................... 5
•
Added fSCLK parameter to Recommended Operating Conditions from Operating Conditions section; deleted
Operating Conditions section ................................................................................................................................................. 5
•
Deleted Package Thermal Resistance table ......................................................................................................................... 5
•
Added unit to Analog input pin, +IN, Analog input voltage, and Digital input pins voltage range parameters ....................... 5
•
Deleted footnote 1 from Recommended Operating Conditions table and changed last footnote to include updated
link ......................................................................................................................................................................................... 5
•
Changed condition statement of ADC141S628Q Converter Electrical Characteristics table to remove boldface condition . 6
•
Changed INL and PCTUE parameter specification test conditions ....................................................................................... 6
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Added TA = –40°C to +105°C to IDCL parameter test conditions ........................................................................................... 6
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Changed VA to max specification from typ specification in VREF parameter .......................................................................... 7
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Changed fSCLK = 0 to fSCLK = low in IVA (PD), IVIO (PD), and IVREF (PD) parameter test conditions......................................... 7
•
Deleted last footnote from ADC141S628Q Converter Electrical Characteristics table .......................................................... 7
•
Changed condition statement of ADC141S628Q Timing Requirements table to remove boldface condition ....................... 8
•
Added temperature conditions to certain parameters in the ADC141S628Q Timing Requirements table ............................ 8
2
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Revision History (continued)
•
Changed title of Typical Characteristics from Typical Performance Characteristics ........................................................... 10
•
Changed Overview title from Functional Description ........................................................................................................... 14
•
Deleted last sentence of second paragraph in Reference Input (VREF) section ................................................................... 14
•
Changed last paragraph of Reference Input (VREF) section ................................................................................................. 14
•
Changed Layout Guidelines title from PCB Layout and Circuit Considerations................................................................... 20
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ADC141S628Q
SNOI146B – SEPTEMBER 2011 – REVISED NOVEMBER 2017
www.ti.com
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
V REF
1
10
+IN
2
9
VIO
- IN
3
8
SCLK
GND
4
7
D OUT
GND
5
6
CS
ADC141S628
VA
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
VREF
Reference
input
Voltage reference input. A voltage reference between 1 V and VA must be applied to this input.
VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk
capacitor value of 1.0 µF to 10 µF in parallel with the 0.1-µF capacitor is recommended for
enhanced performance.
2
+IN
Analog signal
input, positive
Noninverting input. +IN is the positive analog input for the signal applied to the ADC141S628Q.
3
–IN
Analog signal
Inverting input. Must be GND ± 150 mV.
input, negative
4
GND
Supply
Ground. GND is the ground reference point for all signals applied to the ADC141S628Q.
5
GND
Supply
Ground. GND is the ground reference point for all signals applied to the ADC141S628Q.
6
CS
Digital input
Chip-select bar. CS must be active LOW during an SPI conversion, which begins on the falling
edge of CS. The ADC141S628Q is in acquisition mode when CS is HIGH.
7
DOUT
Digital output
Serial data output. The conversion result is provided on DOUT. The serial data output word is
comprised of two null bits followed by 14 data bits (MSB first). During a conversion, the data are
output on the falling edges of SCLK and are valid on the subsequent rising edges.
8
SCLK
Digital input
Serial clock. SCLK is used to control data transfer and serves as the conversion clock.
9
VIO
Supply
Digital input/output power-supply input. A voltage source between 4.5 V and 5.5 V must be
applied to this input. VIO must be decoupled to GND with a minimum ceramic capacitor value of
0.1 µF.
10
VA
Supply
Analog power-supply input. A voltage source between 4.5 V and 5.5 V must be applied to this
input. VA must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
4
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6 Specifications
6.1 Absolute Maximum Ratings
If military/aerospace specified devices are required, please contact the Texas Instruments sales office, distributors for
availability and specifications. (1) (2)
MIN
MAX
UNIT
VA relative to GND
–0.3
6
V
VIO relative to GND
–0.3
6
V
Voltage between any two pins (3)
6
V
Current in or out of any pin (3)
±10
mA
Package input current (3)
±50
mA
Power consumption at TA = 25°C
See
Junction temperature
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
(4)
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA), the current at that pin must be limited to
10 mA and VIN must be within the absolute maximum rating for that pin. The 50-mA maximum package input current rating limits the
number of pins that can safely exceed the power supplies with an input current of 10 mA to five.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax – TA) / θJA. The values for maximum power dissipation listed above are reached only when the ADC141S628Q is
operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the powersupply polarity is reversed). These conditions must be avoided.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per AEC Q100-011
±1250
Machine model (MM)
±300
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1) (2)
MIN
NOM
MAX
UNIT
Operating temperature range
–40
105
°C
Supply voltage, VA
4.5
5.5
V
Supply voltage, VIO
4.5
5.5
V
Reference voltage, VREF
1.0
VA
V
SCLK frequency, fSCLK
0.9
3.6
MHz
Analog input pin, +IN
GND
VA
Analog input pin, –IN
GND ±150 mV
V
mV
Analog input voltage
GND
VREF
Digital input pins voltage range
GND
VIO
V
50k
3.6M
Hz
Clock frequency
(1)
(2)
V
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
For soldering specifications, see the Absolute Maximum Ratings for Soldering application report.
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ADC141S628Q
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6.4 ADC141S628Q Converter Electrical Characteristics
The following specifications apply for VA = VIO = 5 V, VREF = 4.096 V, and fSCLK = 0.9 MHz to 3.6 MHz; fIN = 20 kHz and CL =
25 pF, unless otherwise noted. All specifications are at TA = 25°C, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with no missing codes
TA = –40°C to +105°C
14
Bits
±0.95
LSB
±0.5
INL
Integral nonlinearity
TA = –15°C to +65°C
TA = –40°C to +105°C
DNL
Differential nonlinearity
PCTUE
Post calibration total unadjusted
error
OE
Offset error
FSE
Full-scale error
GE
Gain error
±1
±0.5
TA = –40°C to +105°C
±0.95
–15°C ≤ TA ≤ 65°C
–40°C ≤ TA ≤ 105°C
±0.5
–0.85
1
–1
TA = –40°C to +105°C
±5
–3
TA = –40°C to +105°C
±7
–1.5
TA = –40°C to +105°C
±6
LSB
mV
LSB
LSB
LSB
DYNAMIC CONVERTER CHARACTERISTICS
VIN = –0.1 dBFS
82
SINAD
Signal-to-noise and distortion ratio
SNR
Signal-to-noise ratio
VIN = –0.1 dBFS,
TA = –40°C to +105°C
THD
Total harmonic distortion
VIN = –0.1 dBFS
–97
dBc
SFDR
Spurious-free dynamic range
VIN = –0.1 dBFS
98
dBc
VIN = –0.1 dBFS
13.4
VIN = –0.1 dBFS,
TA = –40°C to +105°C
VIN = –0.1 dBFS
ENOB
Effective number of bits
FPBW
–3-dB full-power bandwidth
VIN = –0.1 dBFS,
TA = –40°C to +105°C
dBc
80
82
dBc
80
Bits
13.0
Output at 70.7%FS with FS input,
single-ended input
22
MHz
ANALOG INPUT CHARACTERISTICS
VIN
(+IN) – (–IN)
TA = –40°C to +105°C
GND
VREF
V
+IN
Noninverting input
TA = –40°C to +105°C
–0.15
VREF + 0.15
V
–IN
Inverting input
TA = –40°C to +105°C
–0.15
0.15
V
IDCL
DC leakage current
VIN = VREF or VIN = 0,
TA = –40°C to +105°C
±1
µA
CINA
Input capacitance
CMRR
Common-mode rejection ratio
(1)
6
In acquisition mode
14
In conversion mode
3.4
See the Specification Definitions
section for the test condition
76
pF
dB
Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are specified to TI's average outgoing quality
level (AOQL).
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ADC141S628Q Converter Electrical Characteristics (continued)
The following specifications apply for VA = VIO = 5 V, VREF = 4.096 V, and fSCLK = 0.9 MHz to 3.6 MHz; fIN = 20 kHz and CL =
25 pF, unless otherwise noted. All specifications are at TA = 25°C, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT CHARACTERISTICS
VIH
Input high voltage
VIL
Input low voltage
IIN
Input current
CIND
Input capacitance
1.9
TA = –40°C to +105°C
V
2.3
1.0
TA = –40°C to +105°C
0.7
VIN = 0 V or VA,
TA = –40°C to +105°C
±1
2
TA = –40°C to +105°C
4
V
µA
pF
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA
VOH
Output high voltage
ISOURCE = 200 µA,
TA = –40°C to +105°C
VA – 0.05
VA – 0.2
ISOURCE = 1 mA
VA – 0.16
ISINK = 200 µA
VOL
Output low voltage
0.01
ISINK = 200 µA,
TA = –40°C to +105°C
ISINK = 1 mA
IOZH, IOZL
Tri-state leakage current
COUT
Tri-state output capacitance
V
V
±1
µA
0.05
Force 0 V or VA,
TA = –40°C to +105°C
Force 0 V or VA
2
Force 0 V or VA,
TA = –40°C to +105°C
Output coding
0.4
4
pF
Straight binary
POWER-SUPPLY CHARACTERISTICS
VA
Analog supply voltage range
TA = –40°C to +105°C
4.5
5.5
V
VIO
Digital input/output supply voltage
range (2)
TA = –40°C to +105°C
4.5
5.5
V
VREF
Reference voltage range
TA = –40°C to +105°C
1.0
VA
V
IVA (Conv)
Analog supply current, conversion
mode
fSCLK = 3.6 MHz, fS = 200 kSPS
Digital I/O supply current, conversion
fSCLK = 3.6 MHz, fS = 200 kSPS,
mode
TA = –40°C to +105°C
170
IVIO (Conv)
IVREF
(Conv)
fSCLK = 3.6 MHz, fS = 200 kSPS
Reference current, conversion mode fSCLK = 3.6 MHz, fS = 200 kSPS,
TA = –40°C to +105°C
45
IVA (PD)
Analog supply current, power-down
mode (CS high)
fSCLK = 3.6 MHz, fS = 200 kSPS
740
fSCLK = 3.6 MHz, fS = 200 kSPS,
TA = –40°C to +105°C
970
260
80
fSCLK = 3.6 MHz
8
fSCLK = low
2
fSCLK = low, TA = –40°C to +105°C
fSCLK = 3.6 MHz
IVIO (PD)
Digital I/O supply current, powerdown mode (CS high)
fSCLK = low
fSCLK = low, TA = –40°C to +105°C
(2)
µA
µA
µA
µA
3
3
0.1
µA
0.7
The value of VIO is independent of the value of VA. For example, VIO can be operating at 5 V while VA is operating at 4.5 V or VIO can
be operating at 4.5 V while VA is operating at 5 V.
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ADC141S628Q Converter Electrical Characteristics (continued)
The following specifications apply for VA = VIO = 5 V, VREF = 4.096 V, and fSCLK = 0.9 MHz to 3.6 MHz; fIN = 20 kHz and CL =
25 pF, unless otherwise noted. All specifications are at TA = 25°C, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-SUPPLY CHARACTERISTICS (continued)
IVREF (PD)
Reference current, power-down
mode (CS high)
fSCLK = 3.6 MHz
0.1
fSCLK = low
0.1
fSCLK = low, TA = –40°C to +105°C
PWR
(Conv)
Power consumption, conversion
mode
PWR (PD)
Power consumption, power-down
mode (CS high)
PSRR
Power-supply rejection ratio
µA
0.2
fSCLK = 3.6 MHz, fS = 200 kSPS
4.8
fSCLK = 3.6 MHz, fS = 200 kSPS,
TA = –40°C to +105°C
6.5
fSCLK = 0, VA = VIO = VREF = 5.0 V
mW
11
fSCLK = 0, VA = VIO = VREF = 5.0 V,
TA = –40°C to +105°C
19.5
See the Specification Definitions
section for the test condition
–85
µW
dB
AC ELECTRICAL CHARACTERISTICS
fSCLK
Minimum clock frequency
TA = –40°C to +105°C
3.6
fS
Maximum sample rate
TA = –40°C to +105°C
200
tACQ
Acquisition, track time
TA = –40°C to +105°C
833
ns
15
SCLK
cycles
tCONV
Conversion, hold time
TA = –40°C to +105°C
tAD
Aperture delay
See the Specification Definitions
section
0.9
MHz
kSPS
6
ns
6.5 ADC141S628Q Timing Requirements
The following specifications apply for VA = VIO = 5 V, VREF = 4.096 V, fSCLK = 0.9 MHz to 3.6 MHz, and CL = 25 pF, unless
otherwise noted. All specifications are at TA = 25°C, unless otherwise noted. (1)
MIN
tCSS
CS setup time prior to an SCLK rising edge
–40°C to +105°C
NOM
tDA
tDIS
tCS
DOUT hold time after an SCLK falling edge
DOUT access time after an SCLK falling edge
–40°C to +105°C
1 / fSCLK – 3
ns (max)
6
ns
1 / fSCLK – 6
Minimum CS pulse duration
ns (min)
28
ns (max)
ns
–40°C to +105°C
40
10
ns
ns (max)
20
–40°C to +105°C
ns
10
6
DOUT disable time after the rising edge of CS (2)
UNIT
ns (min)
–40°C to +105°C
tDH
MAX
3
ns
5
ns (min)
32
ns (max)
20
ns
tEN
DOUT enable time after the falling edge of CS
tCH
SCLK high time
–40°C to +105°C
111
tCL
SCLK low time
–40°C to +105°C
111
tr
DOUT rise time
7
ns
tf
DOUT fall time
7
ns
(1)
(2)
8
51
ns
ns
ns
Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are specified to TI's average outgoing quality
level (AOQL).
tDIS is the time for DOUT to change 10% while being loaded by the timing test circuit (see Figure 2).
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tACQ (Power-Down)
tCONV (Power-Up)
CS
1
2
4
3
tCH
5
tCS
11
12
13
14
15
16
17
18
1
2
SCLK
tEN
D`
0
tDIS
tCL
0
DB13 DB12
DB5
DB4 DB3
DB2
DB1
DB0
0
0
Figure 1. ADC141S628Q Single Conversion Timing Diagram
2 mA
TO OUTPUT
PIN
I OL
1.6V
CL
25 pF
IOH
2 mA
Figure 2. Timing Test Circuit
0.9 x VIO
D OUT
0.1 x VIO
tr
tf
Figure 3. DOUT Rise and Fall Times
SCLK
VIL
tDA
2.3V
DOUT
0.7V
tDH
Figure 4. DOUT Hold and Access Times
SCLK
1
2
tCSS
CS
Figure 5. Valid CS Assertion Times
CS
V IH
90%
90
%
DOUT
10%
t DIS
90
%
DOUT
10%
10
%
Figure 6. Voltage Waveform for tDIS
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6.6 Typical Characteristics
VA = VIO = VREF = 5 V, fSCLK = 3.6 MHz, fSAMPLE = 200 kSPS, TA = +25°C, and fIN = 20 kHz (unless otherwise noted)
0.6
0.6
MAX
0.4
0.2
INL (LSBs)
0.2
DNL (LSBs)
MAX
0.4
0
VREF = VA
0
VREF = VA
-0.2
-0.2
MIN
-0.4
-0.4
-0.6
2.0
3.0
4.0
5.0
MIN
-0.6
3.0
6.0
3.5
4.0
4.5
5.0
VA (V)
VA (V)
Figure 7. DNL vs VA
Figure 8. INL vs VA
0.7
0.5
MAX
DNL (LSBs)
0.3
0.1
-0.1
V A=3V for V REF under 3V;
V A=VREF otherwise
-0.3
MIN
-0.5
-0.7
1
2
3
4
5
6
V REF (V)
Figure 10. INL vs VREF
1.0
0.6
0.6
0.2
VA=2.7V
VA=3.6V
VA=5.5V
INL (LSBs)
DNL (LSBs)
Figure 9. DNL vs VREF
1.0
MAX
MIN
-0.2
0.2
VA=2.7V
VA=3.6V
VA=5.5V
MAX
-0.2
MIN
-0.6
-0.6
-1.0
-45 -25
-5 15 35 55 75
TEMPERATURE (°C)
95 115
-1.0
-45 -25
Figure 11. DNL vs Temperature
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-5 15 35 55 75
TEMPERATURE (°C)
95 115
Figure 12. INL vs Temperature
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 3.6 MHz, fSAMPLE = 200 kSPS, TA = +25°C, and fIN = 20 kHz (unless otherwise noted)
-80
90
VA = VREF
VREF = VA
85
SINAD (dB)
THD (dB)
-90
-100
80
-110
-120
2.5
75
3.0
3.5
4.0
4.5
5.0
70
2.5
5.5
3.0
Figure 13. THD vs VA
90
VA = VREF = 2.7V
VA = VREF = 5.5V
VA = VREF = 3.6V
4.5
5.0
5.5
VA=VREF=2.7V
VA=VREF=3.6V
VA=VREF=5.5V
85
SINAD (dB)
THD (dB)
-90
-100
80
-110
75
-120
70
-45 -25
-5 15 35 55 75
TEMPERATURE (°C)
95 115
-45 -25
Figure 15. THD vs Temperature
-5 15 35 55 75
TEMPERATURE (°C)
95 115
Figure 16. SINAD vs Temperature
90
-80
VREF = V A = VIO = 5.5
VA = V REF = VIO = 5.5
85
SINAD (dB)
-90
THD (dB)
4.0
Figure 14. SINAD vs VA
-80
-100
80
75
-110
-120
0
3.5
VA (V)
VA (V)
70
0
10 20 30 40 50 60 70 80 90 100
10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 17. THD vs Input Frequency
Figure 18. SINAD vs Input Frequency
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 3.6 MHz, fSAMPLE = 200 kSPS, TA = +25°C, and fIN = 20 kHz (unless otherwise noted)
1.0
1.0
OFFSET ERROR
0.5
0.5
0.0
ERROR (LSBs)
ERROR (LSBs)
0.0
-0.5
-1.0
-0.5
-2.5
-45
VREF = VA = VIO = 5.5
-1.0
-1.5
-1.5
-2.0
OFFSET ERROR
GAIN ERROR
-25
-5
15
GAIN ERROR
-2.0
35
55
75
95
-2.5
2.5
115
3.0
1.5
POST CALIBRATION TUE (LSBs)
POST CALIBRATION TUE (LSBs)
2.0
1.5
1.0
0.5
VA=2.7V
VA=3.0V
VA=3.6V
VA=4.0V
VA=4.5V
VA=5.0V
VA=5.5V
-0.5
-1.0
-1.5
4.5
5.0
5.5
VA=2.7V
VA=3.0V
VA=3.6V
VA=4.0V
VA=4.5V
VA=5.0V
VA=5.5V
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-45 -25
-5 15 35 55 75
TEMPERATURE (°C)
95 115
-45 -25
Figure 21. Max TUE vs Temperature
1.0
-5 15 35 55 75
TEMPERATURE (°C)
95 115
Figure 22. Min TUE vs Temperature
0
-20°C
25°C
70°C
-20
MAGNITUDE (dB)
0.6
TUE (LSBs)
4.0
Figure 20. Gain and Offset Error vs VA
Figure 19. Gain and Offset Error vs Temperature
0.0
3.5
VA (V)
TEMPERATURE (°C)
0.2
-0.2
-40
-60
-80
-100
-120
-0.6
-140
-160
-1.0
0
4096
8192
12288
OUTPUT CODE
16384
Figure 23. TUE vs Code Over Temperature
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0
20
40
60
80
FREQUENCY (KHz)
100
Figure 24. Typical Spectrum
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 3.6 MHz, fSAMPLE = 200 kSPS, TA = +25°C, and fIN = 20 kHz (unless otherwise noted)
675
840
790
665
740
IV A (#A)
IV A (#A)
690
655
645
640
590
540
490
635
440
390
625
-45 -25
-5
15
35
55
75
95
340
2.5
115
3.0
3.5
TEMPERATURE (°C)
4.0
4.5
5.0
5.5
VA (V)
Figure 25. VA Current vs Temperature
Figure 26. VA Current vs VA
160
252
150
IV IO (#A)
IV IO (#A)
194
140
130
120
-45 -25
136
78
-5
15
35
55
75
95
20
2.5
115
3.0
3.5
4.0
4.5
5.0
5.5
VIO (V)
TEMPERATURE (°C)
Figure 28. VIO Current vs VIO
Figure 27. VIO Current vs Temperature
23
17.0
20
17
I VREF (#A)
I VREF (#A)
16.5
16.0
14
11
8
15.5
5
15.0
-45 -25
-5
15
35
55
75
95
115
2
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V REF (V)
TEMPERATURE (°C)
Figure 29. VREF Current vs Temperature
Figure 30. VREF Current vs VREF
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7 Detailed Description
7.1 Overview
The ADC141S628Q is a 14-bit, 200-kSPS, sampling analog-to-digital converter (ADC). The converter uses a
successive-approximation register (SAR) architecture based upon capacitive redistribution containing an inherent
sample-and-hold function. The pseudo-differential nature of the analog inputs is maintained from the internal
sample-and-hold circuits throughout the ADC to provide excellent common-mode signal rejection.
The ADC141S628Q operates from independent analog and digital supplies. The analog supply (VA) can range
from 4.5 V to 5.5 V and the digital input/output supply (VIO) can range from 4.5 V to 5.5 V. The ADC141S628Q
uses an external reference (VREF), which can be any voltage between 1 V and VA. The value of VREF determines
the range of the analog input, while the reference input current (IREF) depends upon the conversion rate.
The analog input is presented across the two input pins: +IN and –IN. The –IN pin is connected to the sensor
ground in order to reject any small ground noise that is common to the +IN and –IN. Upon initiation of a
conversion, the differential input is sampled on the internal capacitor array. The inputs are disconnected from the
internal circuitry while a conversion is in progress. The ADC141S628Q features a zero-power track mode where
the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the
applied analog input voltage. Zero-power track mode starts after the 16th falling edge of the serial clock.
The ADC141S628Q communicates with other devices via a serial peripheral interface (SPI) that operates using
three pins: chip-select bar (CS), serial clock (SCLK), and serial data out (DOUT). The external SCLK controls data
transfer and serves as the conversion clock. The duty cycle of SCLK is essentially unimportant, provided the
minimum clock high and low times are met. The minimum SCLK frequency is set by internal capacitor leakage.
Each conversion requires 18 SCLK cycles to complete. If less than 14 bits of conversion data are required, CS
can be brought high at any point during the conversion. This procedure of terminating a conversion prior to
completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB)
first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in
progress and thus there is no pipe line delay.
7.2 Feature Description
7.2.1 Reference Input (VREF)
The externally supplied reference voltage (VREF) sets the analog input range. The ADC141S628Q will operate
with VREF in the range of 1 V to VA.
Operation with VREF below 1 V is also possible with slightly diminished performance. As VREF is reduced, the
range of acceptable analog input voltages is reduced. The peak-to-peak input range is limited to (VREF).
Reducing VREF also reduces the size of the least significant bit (LSB). The size of one LSB is equal to [(VREF) /
2n], where n is 14. When the LSB size goes below the noise floor of the ADC141S628Q, the noise spans an
increasing number of codes and overall performance suffers. For example, the SNR from dynamic signals
degrades, while code uncertainty increases in DC measurements. Because the noise is Gaussian in nature, the
effects of this noise can be reduced by averaging the results of a number of consecutive conversions.
Additionally, because offset and gain errors are specified in LSB, any offset or gain errors inherent in the ADC
increase in terms of LSB size as VREF is reduced.
VREF and analog inputs (+IN and –IN) are connected to the capacitor array through a switch matrix when the
input is sampled. Hence, IREF, I+IN, and I–IN are a series of transient spikes that occur at a frequency dependent
on the operating sample rate of the ADC141S628Q.
IREF changes only slightly with temperature. See Figure 29 for additional details.
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Feature Description (continued)
7.2.2 Analog Signal Inputs
The ADC141S628Q has a pseudo-differential input where the effective input voltage that is digitized is (+IN) –
(–IN) and –IN is restricted to be close to ground. By using this differential input, small signals common to both
inputs are rejected. As shown in Figure 31, noise is rejected well at low frequencies where the common-mode
rejection ratio (CMRR) is 90 dB. As the frequency increases to 1 MHz, the CMRR rolls off to 40 dB.
Figure 31. Analog Input CMRR vs Frequency
The current required to recharge the input sampling capacitor causes voltage spikes at +IN and –IN. Do not try to
filter out these noise spikes. Rather, ensure that the transients settle out during the acquisition period.
7.2.3 Pseudo-Differential Operation
For pseudo-differential operation, the noninverting input (+IN) of the ADC141S628Q can be driven with a signal
that goes from GND to a voltage equal to or less than VREF. Connect the inverting input (–IN) to either the local
GND or the remote sensor ground. This connection allows +IN a maximum swing range of ground to VREF.
Figure 32 shows the ADC141S628Q being driven by a full-scale single-ended source.
V REF
0V
RS
VREF
SRC
+
CS
A DC141S628
-
Figure 32. Single-Ended Input
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Feature Description (continued)
7.2.4 Serial Digital Interface
The ADC141S628Q communicates via a synchronous 3-wire serial interface as described in Figure 1 or reshown in Figure 33 for convenience. CS, chip-select bar, initiates conversions and frames the serial data
transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the
serial data output pin, where a conversion result is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC141S628Q DOUT
pin is in a high-impedance state when CS is high and is active when CS is low; thus, CS acts as an output
enable.
The ADC141S628Q samples the input upon the assertion of CS. Assertion is defined as bringing the CS pin to a
logic low state. For the first 15 periods of the SCLK following the assertion of CS, the ADC141S628Q is
converting the analog input voltage. On the 16th falling edge of SCLK, the ADC141S628Q enters acquisition
(tACQ) mode. For the next three periods of SCLK, the ADC141S628Q is operating in acquisition mode where the
ADC input is tracking the analog input signal applied across +IN and –IN. During acquisition mode, the
ADC141S628Q is consuming a minimal amount of power.
The ADC141S628Q can enter conversion mode (tCONV) under three different conditions. The first condition
involves CS going low (asserted) with SCLK high. In this case, the ADC141S628Q enters conversion mode on
the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under
this condition, the ADC141S628Q automatically enters conversion mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC141S628Q
enters conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK,
there is a minimum and maximum setup time requirements for the falling edge of CS with respect to the rising
edge of SCLK. See Figure 5 for more information.
tACQ (Power-Down)
tCONV (Power-Up)
CS
1
2
3
4
tCH
5
tCS
11
12
13
14
15
17
16
18
1
2
SCLK
tEN
D`
0
tDIS
tCL
0
DB13 DB12
DB5
DB4 DB3
DB2
DB1
DB0
0
0
Figure 33. ADC141S628Q Single Conversion Timing Diagram
7.2.5 CS Input
The CS (chip-select bar) input is active low and is TTL- and CMOS-compatible. The ADC141S628Q enters
conversion mode when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the
ADC141S628Q is always in acquisition mode and thus consuming the minimum amount of power. Because CS
must be asserted to begin a conversion, the sample rate of the ADC141S628Q is equal to the assertion rate of
CS.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data may be clocked out one bit early. Whether or not the data are
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time
(the third falling edge of SCLK), the fall of CS must always meet the timing requirement specified in the
ADC141S628Q Timing Requirements table.
7.2.6 SCLK Input
The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is TTL- and
CMOS-compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The ADC141S628Q offers specified performance with the clock
rates indicated in the ADC141S628Q Converter Electrical Characteristics table.
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Feature Description (continued)
The ADC141S628Q enters acquisition mode on the 16th falling edge of SCLK during a conversion frame.
Assuming that the LSB is clocked into a controller on the 16th rising edge of SCLK, there is a minimum
acquisition time period that must be met before a new conversion frame can begin. Other than the 16th rising
edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition
during acquisition mode. Therefore, SCLK can be idle after the LSB is latched into the controller.
7.2.7 Data Output
The data output format of the ADC141S628Q is straight binary, as shown in Figure 34. This figure indicates the
ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or
noise. Each data output bit is output on the falling edges of SCLK. The first and second SCLK falling edges clock
out leading zeros while the third to 16th SCLK falling edges clock out the conversion result, MSB first.
|
|
00 0000 0000 0000 b
|
ADC Output Code
11 1111 1111 1111 b
+1 LSB
+VREF - 1 LSB
Analog Input
Figure 34. ADC Output vs Input
While most receiving systems capture the digital output bits on the rising edges of SCLK, the falling edges of
SCLK may be used to capture the conversion result if the minimum hold time for DOUT is acceptable. See
Figure 4 for DOUT hold (tDH) and access (tDA) times.
DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th
falling edge of SCLK, the current conversion is aborted and DOUT goes into its high impedance state. A new
conversion begins when CS is driven LOW.
7.3 Device Functional Modes
7.3.1 Power Consumption
The architecture, design, and fabrication process allow the ADC141S628Q to operate at conversion rates up to
200 kSPS while consuming very little power. The ADC141S628Q consumes the least amount of power while
operating in acquisition (power-down) mode. For applications where power consumption is critical, operate the
ADC141S628Q in acquisition mode as often as the application tolerates. To further reduce power consumption,
stop the SCLK while CS is high.
7.3.1.1 Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 14-bit resolution, or where
an analog signal is being monitored until some condition occurs. In some circumstances, the conversion can be
terminated after the first few bits. This termination lowers power consumption in the converter because the
ADC141S628Q spends more time in acquisition mode and less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC141S628Q
output. This cycling is possible because the ADC141S628Q places the latest converted data bit on DOUT as the
bit is generated. If only 10-bits of the conversion result are needed, for example, the conversion can be
terminated by pulling CS high after the 10th bit has been clocked out.
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Device Functional Modes (continued)
7.3.1.2 Burst Mode Operation
Normal operation of the ADC141S628Q requires the SCLK frequency to be 18 times the sample rate and the CS
rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 200 kSPS, run the ADC141S628Q with an SCLK frequency of 3.6 MHz and a CS
rate as slow as the system requires. When this set up is accomplished, the ADC141S628Q operates in burst
mode. The ADC141S628Q enters into acquisition mode at the end of each conversion, minimizing power
consumption, which causes the converter to spend the longest possible time in acquisition mode. Because power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Application Circuits
The following figure is an example of the ADC141S628Q in a typical application circuit. This circuit is basic and
generally requires modification for specific circumstances.
8.1.1.1 Data Acquisition
Figure 35 shows a typical connection diagram for the ADC141S628Q operating at VA of 5 V. VREF is connected
to a 4.1-V shunt reference, the LM4040-4.1, to define the analog input range of the ADC141S628Q independent
of supply variation on the 5-V supply line. Decouple the VREF pin to the ground plane by a 0.1-µF ceramic
capacitor and a tantalum capacitor of 10 µF. The 0.1-µF capacitor must be placed as close as possible to the
VREF pin while the placement of the tantalum capacitor is less critical. The VA and VIO pins of the ADC141S628Q
are also recommended to be decoupled to ground by a 0.1-µF ceramic capacitor in parallel with a 10-µF
tantalum capacitor.
+5V
+
10 PF
100:
ADC141S628
+
LM4040 -4.1
VREF
10 PF
VA
0.1 PF
0.1 PF
VIO
+IN
SCLK
-IN
DOUT
GND
CSB
Controller
Figure 35. Low-Cost, Low-Power Data Acquisition System
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9 Power Supply Recommendations
9.1 Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
ADC141S628Q must be clean and well bypassed. Use a 0.1-µF ceramic bypass capacitor and a 1-µF to 10-µF
capacitor to bypass the ADC141S628Q supply, with the 0.1-µF capacitor placed as close to the ADC141S628Q
package as possible.
Because the ADC141S628Q has both the VA and VIO pins, the user has three options on how to connect these
pins. The first option is to tie VA and VIO together and power them with the same power supply. This connection
is the most cost effective way of powering the ADC141S628Q but is also the least ideal. As stated previously,
noise from VIO can couple into VA and adversely affect performance. The other two options involve the user
powering VA and VIO with separate supply voltages. These supply voltages can have the same amplitude or they
can be different. These voltages may be set independent of each other and can be any value between 4.5 V and
5.5 V.
Best performance is typically achieved with VA operating at 5 V. Operating VA at 5 V offers the best linearity and
dynamic performance when VREF is also set to 5 V.
9.2 Voltage Reference
The reference source must have a low output impedance and must be bypassed with a minimum capacitor value
of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1-µF capacitor is preferred. While
the ADC141S628Q draws very little current from the reference on average, there are higher instantaneous
current spikes at the reference.
The VREF of the ADC141S628Q, like all ADCs, does not reject noise or voltage variations. Keep this fact in mind
if VREF is derived from the power supply. Any noise or ripple from the supply that is not rejected by the external
reference circuitry appears in the digital results. The use of an active reference source is recommended. The
LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are
excellent choices for a reference source.
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10 Layout
10.1 Layout Guidelines
For best performance, care must be taken with the physical layout of the printed circuit board, which is especially
true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so any
noise must settle out before the conversion begins.
10.1.1 PCB Layout
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible. Digital circuits create substantial supply and ground current transients. The logic noise
generated can have significant impact upon system noise performance. To avoid performance degradation of the
ADC141S628Q because of supply noise, avoid using the same supply for the VA and VREF of the ADC141S628Q
that is used for digital circuitry on the board.
Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. Clock lines must be kept
as short as possible and isolated from all other lines, including other digital lines. In addition, the clock line must
also be treated as a transmission line and be properly terminated. Isolate the analog input from noisy signal
traces to avoid coupling of spurious signals into the input. Any external component (for example, a filter
capacitor) connected between the converter input pins and ground or to the reference input pin and ground must
be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. Place the power planes
within the same board layer. All analog circuitry (input amplifiers, filters, reference components, and so forth)
must be placed over the analog power plane. Place all digital circuitry over the digital power plane. Furthermore,
the GND pins on the ADC141S628Q and all the components in the reference circuitry and input signal chain that
are connected to ground must be connected to the ground plane at a quiet point. Avoid connecting these points
too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power
digital device.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Specification Definitions
APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is
sampled for conversion.
COMMON-MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed
from 2 V to 3 V.
CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)
(1)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NONLINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying signal-to-noise
and distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full-scale input.
FULL-SCALE ERROR is the difference between the input voltage at which the output code transitions to positive
full-scale and VREF minus 1 LSB.
GAIN ERROR is the deviation from the ideal slope of the transfer function. Gain error is the difference between
positive full-scale error and negative full-scale error and can be calculated as:
Gain Error = Positive Full-Scale Error − Negative Full-Scale Error
(2)
INTEGRAL NONLINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given
code from this straight line is measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC141S628Q is
specified not to have any missing codes.
OFFSET ERROR is the difference between the input voltage at which the output code transitions from code
0000h to 0001h and 1 LSB.
POST CALIBRATION TOTAL UNADJUSTED ERROR is the total unadjusted error over the temperature range
after system calibration to remove gain and offset errors at 25°C.
POWER-SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage
is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage,
expressed in dB. For the ADC141S628Q, VA is changed from 4.5 V to 5.5 V.
PSRR = 20 LOG (Δ Output Offset / Δ VA)
(3)
SIGNAL-TO-NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or DC.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below one-half the sampling frequency,
including harmonics but excluding DC.
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ADC141S628Q
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Device Support (continued)
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency,
where a spurious spectral component is any signal present in the output spectrum that is not present at the input
and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the
output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated
as:
THD = 20 ‡ log10
A f 22 + " + A f 6 2
A f 12
where
•
•
Af1 is the RMS power of the input frequency at the output
Af2 through Af6 are the RMS power in the first five harmonic frequencies
(4)
TOTAL UNADJUSTED ERROR is the difference between the parts transfer function and the ideal transfer
function.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• LM4040xxx Precision Micropower Shunt Voltage Reference
• LM4050-N/-Q1 Precision Micropower Shunt Voltage Reference
• LM4132, LM4132-Q1 SOT-23 Precision Low Dropout Voltage Reference
• LM4140 High Precision Low Noise Low Dropout Voltage Reference
• Absolute Maximum Ratings for Soldering
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola Mobility LLC.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
22
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ADC141S628Q
www.ti.com
SNOI146B – SEPTEMBER 2011 – REVISED NOVEMBER 2017
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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