ADC14DS105KARB/NOPB

ADC14DS105KARB Near Zero-IF Receiver Reference Design Board LMH6552 + ADC14DS105 + LMK02000 User’s Guide N www.national.com Rev 0.2 Setpember 2007 ADC14DS105KARB Reference Design Board User’s Guide SPI_EN Jumper nd 2 Order Lowpass Filter Fc ≈ 35 MHz Channel A Signal Input ADC 14DS105 LMH6552 Channel B Signal Input LMK02000 Clock Conditioner JP1: PIC microcontroller board power Remove if using Codeloader HMZd Connector OF/DCS Jumper PIC microcontroller / Codeloader header 100 MHz VCXO 25 MHz Reference Crystal Oscillator +/- 5.0V Dual Power Supply Connector Figure 1. ADC14DS105KARB Component, Connector and Jumper Locations N -2- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 1.0 Introduction The ADC14DS105KARB is a near-zero IF receiver reference design board that utilizes the following components from National Semiconductor: • Two LMH6552 1.5 GHz bandwidth differential current feedback amplifiers; • ADC14DS105 14-bit, 1 GHz, Dual 105 MSPS (Megasample per Second) ADC with serial LVDS outputs; • LMK02000 low-jitter precision clock conditioner with an integrated phase-locked loop (PLL) that provides 128 femtosecond (fs) jitter over an integration bandwidth of 100 Hz to 20 MHz; • Several energy-efficient power management ICs. This subsystem reference design utilizes the LMH6552 current feedback amplifier as a differential driver for the ADC14DS105. The sampling clock is provided by a 100 MHz VCXO which is locked to a reference oscillator by the LMK02000. The 1 GHz input bandwidth of the ADC and the 1.5 GHz differential amplifier gain stage provide excellent performance in this application. The measured performance demonstrates large signal SNR of 73.3 dBFS and SFDR greater than 85 dBFS for input signals up to 25MHz. Figure 2 shows a functional block diagram of the board. The ADC14DS105KARB uses a dual ADC, demonstrating a quadrature direct conversion or nearzero IF receiver for signal frequencies from DC to 40 MHz. This receiver architecture is commonly used in WiMAX and WCDMA receiver systems. Figure 2. ADC14DS105KARB Block Diagram 2.0 Data Capture The digital data from the ADC14DS105KARB reference design board can be captured with a suitable instrument, such as a logic analyzer, or with National Semiconductor’s WaveVision signal path data acquisition hardware and software platform. The ADC14DS105KARB board can be connected to the data acquisition hardware through the 60-pin connector mounted on the board edge. N The ADC14DS105KARB is compatible with National Semiconductor’s WaveVision 5.1 Signal Path Digital Interface Board and associated WaveVision software. Please note that the ADC14DS105KARB board is not compatible with previous versions of the WaveVision hardware (WaveVision 4.x Digital Interface Boards). The WaveVision hardware and software package allows fast and easy data acquisition and analysis. The WaveVision hardware connects to a host PC via a USB cable and is fully configured and controlled by the latest -3- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide WaveVision software. The latest version of the WaveVision software (version 4.3.26) is included in this evaluation kit on a CD-ROM. The WaveVision 5.1 Signal Path Digital Interface hardware is available through the National Semiconductor website (part number: WAVEVSN 5.1). 3.0 Evaluation Kit Contents and Board Assembly The ADC14DS105KARB evaluation kit includes the following items: • ADC14DS105KARB reference design board • PIC microcontroller board (ADC14PIC REV. A) • CD-ROM with latest WaveVision software (4.3.26) The ADC14DS105KARB is factory configured for evaluation of input signals up to 35 MHz. Each board is populated with an analog input network which has a lowpass filter with a cutoff frequency of approximately 35 MHz. The LMK02000, which provides the sample clock for the ADC, must be programmed to correctly configure it for the proper operating frequency. The PICmicrocontroller board (ADC14PIC REV. A) is used to program the registers of the LMK02000 precision clock conditioner chip. 4.0 Quick Start 4.1 WaveVision Software and Hardware Installation The WaveVision software must be installed before connecting the WaveVision hardware. which can be found on the National Semiconductor website (http://www.national.com/appinfo/adc/evalboards_datac apture.html). Please note that the ADC14DS105KARB is only compatible with National Semiconductor’s WaveVision 5.1 Digital Interface board. 4.2 Serial Programming Interface (SPI) The channel and data format modes of the ADC14DS105 can be selected either through the SPI or by direct pin control through the jumpers on the evaluation board. The ADC14DS105KARB evaluation board is delivered with the ADC14DS105 configured for SPI operation. The serial programming interface enable (SPI_EN) pin jumper on the ADC14DS105KARB selects the state of the SPI_EN pin. When the jumper is in place, the pin state is asserted HIGH, the SPI is active and the direct control pins have no effect. When the jumper is removed, the SPI_EN state is LOW, the SPI is deactivated and the ADC modes are pin-controlled through the DLC, WAM, TEST jumpers. The SPI interface is routed through the 60-pin HMZd connector and is controlled through the WaveVision hardware and software when the WaveVision 5.1 data capture hardware is connected and active. When the ADC14DS105KARB board is connected to the WaveVision 5.1 board, the SPI software control panel shown in Figure 3 will automatically appear. This window should be used to set the modes of the ADC14DS105 when the SPI is enabled. Please ensure that the fields in the window correspond to Figure 3. Only the field labeled “Channel” needs to be changed to select between capture from Channel A or Channel B. The other fields in the software control panel should remain unchanged. It is not necessary to click on the “Relock DCMs” button. 1. Begin by installing the latest version of the WaveVision software (version 4.3.26) which is on the CD-ROM included in this evaluation kit. Do not start the WaveVision software application at this point. 2. Connect the WaveVision 5.1 Digital Interface Board to your PC through the supplied USB cable and apply power to the WaveVision 5.1 board through the +12V AC-DC power adapter included in the WaveVision 5.1 kit. The connection diagram is shown in Figure 3. 3. If this is the first time connecting a WaveVision 5.1 board to your PC, follow the on-screen instructions for installing the drivers for the hardware. 4. Once the WaveVision software and hardware have been installed, the WaveVision software application can be opened. For more information on installing the WaveVision data acquisition hardware or software, please refer to the Quick Start Guide in the WaveVision User’s Guide N -4- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide SPI_EN jumper is installed (SPI is active), as the DLC mode is controlled through the SPI interface. Only change this field Jumper position OPEN Description Both ADC LVDS channel outputs operate in dual-lane mode INSTALLED ADC LVDS channel outputs operate in single-lane mode Table 1. DLC Mode Jumper Description (Note: This jumper has no effect when the SPI_EN jumper is installed) 2. The word-alignment-mode (WAM) jumper on the front of the board controls the alignment of the sample data words at the ADC outputs. If the DLC mode is single-lane, this jumper must NOT be installed (WAM state is LOW). When the DLC mode is dual-lane (DLC jumper is removed), and the WAM jumper is not installed, the data samples at the SD1_X/SD0_X outputs are offset by one-half sample word. Likewise, when the WAM jumper is installed for dual-lane mode, the data words on SD1_X/SD0_X are time aligned with one another. This pin has no effect when SPI_EN jumper is installed (SPI is active), as the WAM mode is then controlled through the SPI interface. Jumper position OPEN Figure 3. SPI Software Control Panel 4.3 Evaluation Board Jumper Positions 1. JP1 should have a jumper installed to provide power to the PIC microcontroller board used for programming the LMK02000 registers. Remove JP1 if using Codeloader to program the LMK02000 (see Section 5.5 of this guide). If the SPI_EN jumper is not in place, then ADC14DS105 is under pin control, and ADC14DS105KARB board jumpers should configured as follows. Please refer to Figure 1 for exact jumper locations. the the be the When operating in single lane mode (DLC jumper is installed), this jumper must NOT be installed When operating in dual lane mode, the data samples are offset by one-half word. INSTALLED When operating in dual lane mode, the data samples are aligned. Table 2. WAM Jumper Description (Note: This jumper has no effect when the SPI_EN jumper is installed) 3. The PDA and PDB jumpers are used to place the ADC14DS105 converters into either power-down or normal operation mode. Table 1 below shows how to select between the power-down modes. PDx Jumper Settings Mode Open Normal Operation 1-2 Power-down Table 3. ADC Power-down Jumper Configuration (PDA and PDB) ADC Control Jumpers 1. The DLC pin jumper selects the Dual Lane configuration. When the jumper is in place, the pin is asserted HIGH and all data is sourced on a single lane (SD1_X) for each channel. When the jumper is removed, both channels operate in duallane mode and the SD1_X and SD0_X outputs both carry data. This control is disabled when the N Description If both Channel A and Channel B are powered down at the same time, the ADC14DS105KARB reference board must be power-cycled to recover. -5- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 4. The OF/DCS pin jumpers select the output data format (2’s complement or offset binary) and clock duty cycle correction (active or inactive). Table 2 below shows how to select between the duty cycle correction modes and output data formats. Please note that the ADC14DS105KARB evaluation board is delivered with the ADC14DS105 clock input configured for NO duty cycle correction and Offset Binary output data format (Jumper 7-8). OF/DCS Jumper Setting 1-2 3-4 5-6 7-8* Clock Mode No Duty Cycle Stabilization Duty Cycle Stabilization Duty Cycle Stabilization No Duty Cycle Stabilization Output Data Format 2’s Complement 2’s Complement Offset Binary Offset Binary * As assembled from factory. Not observed because ADC14DS105KARB is delivered with the SPI enabled Table 4. ADC Jumper Settings for ADC Clock Duty Cycle and Output Data Format (OF/DCS) 5. The TEST pin jumper selects the state of Test Mode. When the jumper is in place the TEST pin is asserted HIGH and Test Mode is active. A fixed test pattern (10100110001110, msb
lsb) is sourced on all data paths. When the jumper is removed, the ADCs operate in normal mode. This pin has no effect when the SPI_EN jumper is installed (SPI is active), as this the TEST mode is controlled through the SPI interface. Jumper position OPEN INSTALLED Description The ADC is in normal operation. A fixed test pattern is output (10100110001110 msb
lsb) Table 5. TEST Jumper Description Amplifier Power Jumpers 1. The VCCAA- and VCCAB- jumpers are used to select the power supply configuration for the amplifiers. The evaluation board is shipped from the factory in the dual power supply configuration (+/- 5V), so these jumpers are not installed. If single supply operation is desired (+5VDC only), these jumpers should be installed. N Jumper position Description OPEN Dual power supply operation INSTALLED Single power supply operation Table 6. VCCAA- and VCCAB- Jumper Description ADC Sample Clock Programming The LMK02000, which provides the sample clock for the ADC, must be programmed to correctly configure it for the proper clock frequency. The programming can be accomplished by either one of two methods. The first method is to attach a small PIC-based module that is included in this evaluation kit. This module is plugged onto the 10-pin header labeled “UWIRE” as described in Section 4.4 of this user’s guide. If this module is used, the JP1 jumper must be installed to provide power from the main board to the PIC module. The second method for programming the LMK02000 uses the 10-pin “UWIRE” header to connect the LMK02000’s serial programming interface (DATA, CLK, LE) to a PC. To use this programming interface, a special parallel port (LPT) cable supplied by National Semiconductor allows the device to be directly programmed with a PC using National Semiconductor’s Codeloader software. The serial programming interface can also be programmed over the USB port of the PC. To program the LMK02000 through the USB port, a separate interface board is available from National Semiconductor. See http://www.national.com/appinfo/interface/clk_condition ers.html to download Codeloader, obtain a user’s guide and to order any necessary hardware such as programming cables or USB interface boards. Remove JP1 if using Codeloader to program the LMK02000. 4.4 Connecting Power and Signal Sources 1. Connect the ADC14DS105KARB reference board to the WaveVision 5.1 board through the FutureBus connector as shown in Figure 4. The ADC14DS105KARB reference board should not be powered up, as the WaveVision hardware does not support hot-swapping of boards. 2. With the WaveVision software running, power-up the WaveVision 5.1 board, and the WaveVision software will automatically load the appropriate firmware to allow data capture from the ADC14DS105KARB. Allow the firmware file to finish downloading before continuing. -6- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide Figure 4. Connection Diagram for ADC14DS105KARB and WaveVision 5.1 Data Capture Hardware 3. Plug the PIC microcontroller board onto the dualrow header labeled “UWIRE” as shown in Figure 5. Align the arrows on the two boards to ensure proper orientation. JP1 should have a jumper installed on the main board to provide power to the PIC microcontroller board. Lastly, flip the switches on the PIC microcontroller board to the following positions: Switch 1 = OFF, Switch 2 = OFF. Switch 1 = OFF Switch 2 = OFF Place JP1 on main board to provide power to PIC board Align Arrows Figure 5. PIC microcontroller Board Connection and Configuration N 4. Connect a 5.0V dual power supply (+/- 5.0V) capable of supplying up to 1A to the green power connector which is located along the bottom edge of the ADC14DS105KARB board. This is shown in Figure 3. Ensure that the polarity of the wires going to the green power connector match the “+5V”, “-5V” and “GND” labels on the evaluation board. Turn on the +/- 5V supply. 5. The single-ended analog signal inputs are provided by board-edge SMA(f) connectors labeled “INA” and “INB”. The input impedances are 50 ohms. The maximum amplitude (Vp-p) for satisfactory performance is 1 Vp-p. The inputs are DC-coupled but the input signal may be either DC or AC coupled. If DC coupled, the DC level of the signal should not exceed 1.2 V. The DC level is set on the ADC14DS105KARB reference board. Connect the signal source through the SMA connector as shown in Figure 1 and Figure 4. Recommended signal generators are the HP8644B (HP/Agilent) or the SMA100A (Rohde & Schwarz). A bandpass filter between the signal generator output and the ADC14DS105KARB SMA connector is required to measure the true performance of the board. See Figure 4. 6. Set the signal source to the desired frequency (up to ~35 MHz) and the input amplitude to 0dBm. The signal generator amplitude will need to be adjusted during evaluation to obtain the desired signal amplitude at the ADC input. 7. Press the “RESET” button on the PIC microcontroller board to load the register settings -7- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide into the LMK02000. The three LED’s on the PIC microcontroller board will flash to indicate that the register bits have been sent to the LMK02000. At this point, the board should be ready to capture digital data. plot in WaveVision is to use the “alt-c” key stroke combination. 4.4 ADC14DS105KARB Performance 8. Capture the data and display the FFT of the captured data with the WaveVision software. A shortcut for capturing data and displaying the FFT Reference Board The following plots show the typical (not guarateed) performance of the ADC14DS105KARB reference board at a sample rate of 100 MSPS. 95 Magnitude (dBFS) 90 85 SNR ChanA SFDR ChanA SNR ChanB SFDR Chan B 80 75 70 0 5 10 15 20 25 30 Input Frequency (MHz) Figure 6. ADC14DS105KARB Typical SFDR and SNR Performance vs. Input Frequency (Amplitude at the ADC input is -1dBFS) Figure 7. ADC14DS105KARB Typical FFT for Input Frequency of 20 MHz and Amplitude of -1dBFS (at ADC input) N -8- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide SFDR), a low noise signal generator such as the HP8644B (HP/Agilent) or SMA100A (Rohde & Schwarz) is recommended to drive the signal inputs of the evaluation board. The output of the signal generator should be bandpass filtered to suppress any harmonic distortion produced by the signal generator and to allow accurate measurement of the noise and distortion performance. See Figure 4. The low pass filter (Fc ≈ 35 MHz) following the LMH6552 will further improve the noise performance of the ADC by filtering the broadband noise of the signal generator. 5.0 Functional Description 5.1 Dual Analog Inputs with LMH6552 High Speed Differential Amplifier This evaluation board is configured to accept dual analog inputs via SMA(f) connectors. Figure 8 illustrates the input configuration for the amplifiers. The inputs are 50 ohms, DC-coupled. Each input drives an LMH6552 differential amplifier that is configured for the single-ended-to-differential mode conversion. The VCOM output of the ADC (ADC14DS105) is used as the common mode input to the amplifier. Each amplifier is configured for 6 dB of gain, so the maximum input signal level is 1 Vp-p, producing 2Vp-p at the output of the amplifier. It is recommended that the amplifiers be powered by dual supply rails (+/- 5VDC), but the board can also be configured to operate in single supply mode by installing jumpers at VCCAA- and VCCAB-. Please refer to the LMH6552 datasheet for a description of operating the LMH6552 with a single supply. To obtain the best distortion results (best 5.2 Bandpass Anti-Aliasing Filter The output of the LMH6552 amplifier drives a passive nd 2 order lowpass filter with Fc ≈ 35 MHz as shown in Figure 8. The filter output is sampled by the analog to digital converter. The combined channel response of the differential amplifier, bandpass filter and ADC is shown in the Figure 9. Figure 8. Analog Input Circuit for ADC14DS105KARB 0 -2 Output Fundamental Amplitude (dBFS) ChanA ChanB -4 -6 -8 -10 -12 -14 -16 -18 0 10 20 30 40 50 60 Input Frequency (MHz) nd Figure 9. 2 Order Lowpass Filter Profile for ADC14DS105KARB N -9- www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 5.3 ADC Reference The internal 1.2V reference on the ADC14DS105 is used in this reference design. This is the recommended reference configuration for the ADC14DS105. 5.4 Clock Input The ADC clock used to sample the analog inputs is generated using a VCXO controlled by the LMK02000 Precision Clock Conditioner. The LMK02000 is gives the user an ultra-low noise phase-locked loop (PLL) paired with a clock distribution section that provides 5 LVPECL outputs and 3 LVDS outputs (all differential). Though not used in this design, each clock output channel on the LMK02000 contains a divider block and delay adjustment clock. The LMK02000 is typically paired with a low jitter VCXO, in this case the Crystek model CVHD-950X-100.0, which provides a singleended CMOS clock driving the ADC clock input. On the ADC14DS105KARB evaluation boad, the LMK02000 PLL locks this VCXO to a 25 MHz reference oscillator (Connor-Winfield model CWX823). Figure 10 shows a block diagram of the clocking circuit on the ADC14DS105KARB reference board. The PLL counters, phase detector and charge pump of the LMK02000 are programmed using the PIC microcontroller board as discussed in Section 4.4 of this guide. The LMK02000 achieves 128 fs RMS jitter (integrated from 100 Hz to 20 MHz). Figure 11 illustrates the phase noise performance of the clock, measured at CLKout4 of the LMK02000. The single-ended clock signal from the VCXO is applied to the CLK input on the ADC14DS105. ADC LMK02000 Reference Osc VCXO Figure 10. Clocking Circuit for ADC14DS105KARB Measured Phase Noise of the LMK02000, F_carrier = 100 MHz -100 Phase Noise -110 dBc -120 -130 -140 -150 -160 100 1000 10000 100000 1000000 10000000 Offset (Hz) Figure 11. LMK02000 Phase Noise Performance, 100 MHz, Measured at CLKout4 N - 10 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 5.5 LMK02000 Programming The LMK02000, which provides the sample clock for the ADC, must be programmed to correctly configure it for the proper clock frequency. The programming can be accomplished by either one of two methods. The first method is to attach a small PIC-based module that is included in this evaluation kit. This module is plugged onto the 10-pin header labeled “UWIRE” as described in Section 4.4 of this user’s guide. If this module is used, the JP1 jumper must be installed to provide power from the main boad to the PIC module. The PIC module will program the LMK02000 to lock the 100MHz VCXO to a reference of 25 MHz. The second method for programming the LMK02000 uses the 10-pin “UWIRE” header to connect the LMK02000’s serial programming interface (DATA, CLK, LE) to a PC. To use this programming interface, a special parallel port (LPT) cable supplied by National Semiconductor allows the device to be directly programmed with a PC using National Semiconductor’s Codeloader software. The serial programming interface can also be programmed over the USB port of the PC. To program the LMK02000 through the USB port, a separate interface board that is available from National Semiconductor is required. See http://www.national.com/appinfo/interface/clk_condition ers.html to download Codeloader, obtain a user’s guide and to order any necessary hardware such as programming cables or USB interface boards. Remove JP1 if using Codeloader to program the LMK02000. The procedure for programming the LMK02000 through National’s Codeloader software and special parallel port cable is described here if the user intends to program the ADC14DS105KARB reference board for sampling rates other than 100 MSPS. Please note that the VCXO and possibly the loop filter components must be changed to achieve sampling rates other than 100 MSPS. The following figures illustrate the Codeloader configuration screens and their contents required to properly program the LMK02000 Clock Conditioner using either a parallel port or USB PC interface with appropriate cable. These configuration screens are for programming the LMK02000 to lock a 100 MHz VCXO to a 25 MHz reference, which is the same configuration used on the ADC14DS105KARB reference board. The settings below are programmed using the PIC-module included in this evaluation kit. Figure 12. LMK02000 Codeloader software communication port setup for programming port requires a separate interface board, available from National Semiconductor. It should be noted that the user may be required to select a different LPT port that is compatible with the capabilities of the PC being used to program the device. Using the USB N - 11 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide Figure 13. LMK02000 Codeloader configuration, Bits/Pins tab. Figure 14. LMK02000 Codeloader configuration, PLL tab. Note: Using PLL parameter values different from the values shown in Figure 14 may result in degraded performance of the reference board. N - 12 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide Figure 15. LMK02000 Codeloader configuration, Clock Outputs tab. Note: The LMK02000 clock outputs are not accessible on the ADC14DS105KARB evaluation board. See http://www.national.com/appinfo/interface/clk_condition ers.html for information on acquiring the LMK02000 Evaluation board, which provides full access to all clock outputs on the LMK02000. 5.6 Board Outputs Each analog channel is sampled by the dual channel ADC14DS105 analog to digital converter (ADC) on the rising edge of the sample clock. The 14-bit digital samples from each ADC channel are serially clocked out of one (single-lane mode) or two (dual-lane mode) low-voltage-differential-signalling (LVDS) outputs. The samples from converter Channel A appear on SD1_A+/- (single-lane mode) or on both SD1_A+/- and SD0_A+/- (dual –lane mode). Likewise, the samples from Channel B appear on SD1_B+/- (single-lane mode) or on both SD1_B+/- and SD0_B+/- (dual –lane mode). On the evaluation board, these outputs are routed to the 60-pin connector. When the evaluation N board is mated with a WaveVision 5 board that is connected to a PC USB port, the samples are buffered on the WaveVision board and then processed by the WaveVision application software running on the PC. The sample format is configured by the control panel in the WaveVision software or by the jumper on the 8-pin header labeled “OF/DCS”. See Section 3.1 for further details. Please see the ADC14DS105KARB Reference Board schematic in Section 6.0 of this guide and the ADC14DS105 datasheet for further details. 5.7 Power requirements. Power to the ADC14DS105KARB evaluation board is supplied through the green power connector which is located along the bottom edge of the board. A dual 5V supply (+/- 5.0V) capable of delivering up to 1.0A is required. - 13 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 6.0 Evaluation Board Schematic Figure 16. Input Channels With LMH6552 N - 14 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 6.0 Schematic (cont.) Figure 17. ADC14DS105 Circuit N - 15 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 6.0 Schematic (cont.) Figure 18. LMK02000 Clock Circuit N - 16 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 6.0 Schematic (cont.) Figure 19. Power Distribution N - 17 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 7.0 Evaluation Board Layout Figure 20. Layer 1 - Signal N - 18 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 7.0 Evaluation Board Layout (cont.) Figure 21. Layer 2 - Ground N - 19 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 7.0 Evaluation Board Layout (cont.) Figure 22. Layer 3 - Power N - 20 - www.national.com Rev 0.2 ADC14DS105KARB Reference Design Board User’s Guide 7.0 Evaluation Board Layout (cont.) Figure 23. Layer 6 - Signal N - 21 - www.national.com Rev 0.2 4 5 6 7 8 2 2 2 5 37 9 23 Part Name EEPROM CONVERTER WAVEVISION CONNECTOR www.national.com Rev 0.2 10 2 2 1 4 4 6 2 2 2 1 0 1 17 24 25 26 27 28 29 30 31 32 33 3 2 1 1 1 2 4 4 2 3 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 1 1 2 1 2 2 1 1 1 1 7 5 6 1 2 3 1 10 2 2 3 2 1 1 1 1 6 4 4 2 2 1 1 4 2 0 4 4 OF/DCS UWIRE U1-2 PLL U6-7 U8-9 U4 POWER U3 Z1-4, Z6-8 R28, R61, R64, R94, R97 R30, R40, R65, R70, R47-48 R19 R62-63 R50, R52, R54 R44 R34, R67, R69, R71-75, R82, R85 R83, R90 R38, R46 R49, R51, R53 R43 R45 R77 R20 R35 R32 R36, R76, R78-81 R8-9, R24, R27 R6-7, R17-18, R87, R89 INA, INB Y2 Y3 MT1-4 R91-92 R11-R12, R23, R26 R2-3, R22, R25 Jumper 2X4 Jumper 2X5 DIFF AMP Phase Lock Loop Voltage Regulator Voltage Regulator Voltage Regulator Power Connector Terminal Block Power Connector Plug Inverter Noise Suppression Filter 0 ohms 0 ohms 102 ohms 121 ohms 15K ohms 18.2 ohms 1K ohms 2.32K ohms 24.9 ohms 26.7K ohms 274 ohms 3.57K ohms 301 ohms 332 ohms 4.75K ohms 40.2K ohms 274 ohms 100 ohms 49.9 ohms SMA Input OSC VCXO Bump-on Rubber Feet 0.1uF 127 ohms 68.1 ohms PCB Footprint 8 PIN SOIC LLP-60 - Manufacturer ATMEL NATIONAL SEMICONDUCTOR TYCO 0.1uF SMD CAP CERAMIC 6.3V X5R 10% 49.9 OHM SMD RESISTOR 1/16W 0.1% CAP CER 10UF 10V X7R 0.1uF SMD CAP CERAMIC 25V X5R 10% 0.1uF SMD CAP CERAMIC 10V X5R 10% sm/c_0201 sm/c_0603 sm/c_1210 sm/c_0603 sm/c_0402 Panasonic - ECG Susumu Taiyo Yuden AVX Corporation Panasonic - ECG 0.01uF SMD CAP CERAMIC 16V X7R 10% sm/c_0402 AVX Corporation 0.01uF SMD CAP CERAMIC 50V X7R 10% sm/c_0603 Panasonic - ECG 0.01uF SMD CAP CERAMIC 50V X7R 5% 0 OHM SMD RESISTOR 1/4W 5% 10uF SMD CAP CERAMIC 10V X5R 20% 1000PF SMD CAP CERAMIC 50V NPO 5% 1uF SMD CAP CERAMIC 6.3V X5R 10% 1uF SMD CAP CERAMIC 25V X7R 10% 2200pF SMD CAP CERAMIC 100V X7R 5% 22pF SMD CAP CERAMIC 50V NPO 5% 4.7uF SMD CAP CERAMIC 25V X5R 10% 470pF SMD CAP CERAMIC 50V COG 5% 68000pF SMD CAP CERAMIC 25V X7R 10% 10uF SMD CAP TANTALUM 6.3V 20% sm/c_1206 sm/c_1206 sm/c_1206 sm/c_0603 sm/c_0402 sm/c_1206 sm/c_0603 sm/c_0603 sm/c_1206 sm/c_0402 sm/c_0603 sm/c_3216 Kemet Vishay Dale Panasonic - ECG Panasonic - ECG Panasonic - ECG Panasonic - ECG AVX Corporation Panasonic - ECG Panasonic - ECG TDK Corporation Murata Electronics Kemet 22uF SMD CAP TANTALUM 10V 10% 68uF SMD CAP TANTALUM 10V 20% LIGHT TOUCH SWITCH 240GF SMD SMD FERRITE BEAD CORE 4.5X3.2X1.8 RED LIGHT EMITTING DIODE 100UH SMD INDUCTOR UNSHIELDED 620nH Series 1008CS (2520) Ceramic Chip Inductor 0 OHM SMD RESISTOR 1/8W 5% 1X2 JUMPER BLOCK HEADER PLACE SHUNT SO IT IS ON ONE OF JP1 CONNECTOR PINS BUT DOES NOT CONNECTOR TO THE OTHER PIN, PLACE SHUNT FROM PINS 1-2 ON SPI, PLACE SHUNT FROM PINS 7-8 ON OF/DCS 2X4 JUMPER BLOCK HEADER 2X5 JUMPER BLOCK HEADER 1 GHz Fully Differential Amplifier PRECISION CLOCK DISTRIBUTOR WITH INTERGRATED PLL ADJUSTABLE VOLTAGE REGULATOR LINEAR REGULATOR FOR RF/ANALOG CIRCUITS LOW-DROPOUT CMOS VOLTAGE REGULATOR TERMINAL BLOCK 3POS 5.08mm TERMINAL BLOCK PLUG 2POS 5.08mm INVERTER SGL TINYLOGIC FILTER LC HIGH FREQ .2UF 0 OHM SMD RESISTOR 1/10W 5% 0 OHM SMD RESISTOR 1/16W 1% 102 OHM SMD RESISTOR 1/10W 1% 121 OHM SMD RESISTOR 1/16W 1% 15K OHM SMD RESISTOR 1/16W 1% 18.2 OHM SMD RESISTOR 1/16W 1% 1K OHM SMD RESISTOR 1/16W 1% 2.32K OHM SMD RESISTOR 1/16W 1% 24.9 OHM SMD RESISTOR 1/16W 1% 26.7K OHM SMD RESISTOR 1/16W 1% 274 OHM SMD RESISTOR 1/16W 1% 3.57K OHM SMD RESISTOR 1/10W 1% 301 OHM SMD RESISTOR 1/10W 1% 332 OHM SMD RESISTOR 1/10W 1% 4.75K OHM SMD RESISTOR 1/16W 1% 40.2K OHM SMD RESISTOR 1/10W 1% 274 OHM SMD RESISTOR 1/10W 1% 100 OHM SMD RESISTOR 1/16W 0.1% 49.9 OHM SMD RESISTOR 1/16W 1% PCB MOUNTABLE SMA CONNECTOR 25 MHz Oscillator 100 MHz Voltage Controlled Oscillator PLACE BUMP ONS AT THE 4 CORNERS, ON BOTTOM OF BOARD 0.1uF SMD CAP CERAMIC 25V X5R 10% 127 OHM SMD RESISTOR 1/10W 1% 68.1 OHM SMD RESISTOR 1/10W 1% sm/c_3216 sm/c_6032 sm/i_1812 sm/l_1008 sm/l_1008 - AVX Corporation Kemet Panasonic - ECG Panasonic - ECG AVAGO API Delevan Coilcraft ROHM Samtec FCI Electronic LLP-8 LLP-48 PSOP-8 LLP-6 SOT23-5 SOT23-5 1806 sm/l_0603 sm/r_0402 sm/r_0603 sm/r_0402 sm/r_0402 sm/r_0402 sm/r_0402 sm/r_0402 sm/r_0402 sm/r_0402 sm/r_0402 sm/r_0603 sm/r_0603 sm/r_0603 sm/r_0402 sm/r_0603 sm/r_0603 sm/r_0603 sm/r_0402 sm/r_0603 sm/r_0603 sm/r_0603 Samtec Samtec NATIONAL SEMICONDUCTOR NATIONAL SEMICONDUCTOR NATIONAL SEMICONDUCTOR NATIONAL SEMICONDUCTOR NATIONAL SEMICONDUCTOR Phoenix Contact Phoenix Contact FAIRCHILD Murata Electronics Vishay Dale Vishay Dale Vishay Dale Panasonic - ECG Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale Vishay Dale ROHM Panasonic - ECG Yageo Corporation Molex/Waldom Electronics Corp Connor-Winfield Crystek Crystal Corpotation 3M AVX Corporation ROHM Vishay Dale ADC14DS105KARB Reference Design Board User’s Guide - 22 - 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C33, C37 0.1uF C153-154 49.9 ohms C98, C131 10uF C1, C119, C121, C127, C129 0.1uF C5, C7, C9, C11, C13, C15, 0.1uF C17-18, C20-21, C35-36, C39-40, C48, C53, C58-59, C61, C63-64, C66, C68, C70, C72, C74, C77, C79, C87, C94, C101-102, C110-112, C141, C147 C4, C6, C8, C10, C12, C14, C16, 0.01uF C47, C49, C52, C57, C60, C62, C65, C67, C71, C73, C76, C78, C86, C93, C95, C108 C23, C26, C29,C43, C45, C69, 0.01uF C132, C134-135, C149 C96, C130 0.01uF C30, C46 0 ohms C113 10uF C22, C25, C42, C44 1nF C19, C34, C38, C109 1uF C84, C82, C139-140, C145-146 1uF C152, C155 2.2nF C3, C32 22pF C91, C97 4.7uF C103 470pF C105 68nF C54-55, C81, C83, C85, C89, C92, 10uF C106-107, C120, C124, C126, C128, C136-137, C142-143 C56, C75, C122 22uF C138, C144 68uF RESET RESET SWITCH L4 Ferrite Bead Core LOCK LOCK LED L5, L9 Inductor L2-3, L6-7 620nH L10-13 0 ohms JP1, SPI Jumper 1X2 JP1, SPI, OF/DCS Shunt Description 2K SERIAL EEPROM DUAL 14-BIT 105 MSPS A/D CONVERTER WITH SERIAL LVDS OUTPUTS HMDz RECEPTACLE 8.0 Evaluation Board Bill of Materials N Item Quantity Schematic Reference 1 1 U5 2 1 ADC 3 1 WV ADC14DS105KARB Reference Design Board User’s Guide The ADC14DS105KARB Reference Design Board is intended for product evaluation purposes only and is not intended for resale to end consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC. WaveVision is a trademark of National Semiconductor Corporation. National does not assume any responsibility for use of any circuitry or software supplied or described. No circuit patent licenses are implied. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80 532 78 32 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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