ADC3561, ADC3562, ADC3563
SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
ADC356x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power ADC
1 Features
3 Description
•
•
•
The ADC3561, ADC3562, ADC3563 (ADC356x)
family of devices are a low-noise, ultra-low power,
16-bit, 10-MSPS to 65-MSPS, high-speed analog-todigital converters (ADCs). Designed for low power
consumption, these devices deliver a noise spectral
density of –158 dBFS/Hz combined with excellent
linearity and dynamic range. The ADC356x offers
good DC precision together with IF sampling support
making the device suitable for a wide range of
applications. High-speed control loops benefit from
the short latency of only one clock cycle. The ADC
consumes only 122 mW at 65 MSPS and power
consumption that scales well with lower sampling
rates.
•
•
•
•
•
•
•
•
•
•
16-Bit 10-MSPS to 65-MSPS ADC
Noise floor: –158 dBFS/Hz
Low power consumption:
77 mW (10 MSPS) to 122 mW (65 MSPS)
Latency: 1 clock cycle (1-wire SLVDS)
Specified 16-bit, no missing codes
INL: ± 3 LSB; DNL: ± 0.7 LSB
Reference: external or internal
Input bandwidth: 900 MHz (3 dB)
Industrial temperature range: –40°C to +105°C
On-chip dual band digital filter (optional)
– Decimation by 2, 4, 8, 16, 32
– 32-bit NCO
Serial LVDS digital interface (2-, 1- and 1/2-wire)
Small footprint: 40-WQFN (5 mm × 5 mm) package
Spectral performance (fIN = 10 MHz):
– SNR: 81.9 dBFS
– SFDR: 95-dBc HD2, HD3
– SFDR: 100-dBFS worst spur
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
High-Speed Data Acquisition
Industrial Monitoring
Software Defined Radio
Power Quality Analyzer
Source Measurement Unit (SMU)
Communications Infrastructure
Spectrum Analyzer
Control Loops
Instrumentation
Imaging
Spectroscopy
Radar
Sonar
The ADC356x uses a serial LVDS (SLVDS) interface
to output the data which minimizes the number of
digital interconnects. The device supports two-, oneand half-lane options. The ADC356x and ADC358x
are a pin-to-pin compatible family with 16 and 18-bit
resolution and different speed grades. The devices
come in a 40-pin QFN package (5 x 5 mm), and
supports the extended industrial temperature range
from -40 to +105⁰C.
Package Information
PART NUMBER
ADC356x
(1)
PACKAGE(1)
WQFN (40)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Table 3-1. Device Comparison
PART NUMBER
RESOLUTION
SAMPLING RATE
ADC3563
16 BIT
65 MSPS
ADC3562
16 BIT
25 MSPS
ADC3561
16 BIT
10 MSPS
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC3561, ADC3562, ADC3563
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics - Power Consumption......... 6
6.6 Electrical Characteristics - DC Specifications............. 7
6.7 Electrical Characteristics - AC Specifications............. 9
6.8 Timing Requirements................................................ 12
6.9 Typical Characteristics - ADC3561........................... 14
6.10 Typical Characteristics - ADC3562......................... 17
6.11 Typical Characteristics - ADC3563......................... 21
7 Parameter Measurement Information.......................... 26
8 Detailed Description......................................................28
8.1 Overview................................................................... 28
8.2 Functional Block Diagram......................................... 28
8.3 Feature Description...................................................29
8.4 Device Functional Modes..........................................50
8.5 Programming............................................................ 51
8.6 Register Maps...........................................................53
9 Application Information Disclaimer............................. 69
9.1 Typical Application.................................................... 69
9.2 Initialization Set Up................................................... 72
9.3 Power Supply Recommendations.............................73
9.4 Layout....................................................................... 74
10 Device and Documentation Support..........................76
10.1 Device Support ...................................................... 76
10.2 Documentation Support.......................................... 76
10.3 Receiving Notification of Documentation Updates..76
10.4 Support Resources................................................. 76
10.5 Trademarks............................................................. 76
10.6 Electrostatic Discharge Caution..............................76
10.7 Glossary..................................................................76
11 Mechanical, Packaging, and Orderable
Information.................................................................... 76
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2022) to Revision B (October 2022)
Page
• Added missing TYP value of 0.43 %FSR for Gain Error under ADC3561 (10 MSPS)....................................... 7
Changes from Revision * (February 2021) to Revision A (October 2022)
Page
• Removed the Product Preview note from part numbers ADC3561 and ADC3562 in the Device Comparison
table.................................................................................................................................................................... 1
• Corrected pin numbers for DB0P/M, DB1P/M, IOVDD and IOGND................................................................... 3
• Added the Typical Characteristics - ADC3561 graphs......................................................................................14
• Added the Typical Characteristics - ADC3562 graphs......................................................................................17
• Added GND symbol to REFGND pin for all voltage reference option diagrams...............................................34
• Added the section Output Bit Mapper ..............................................................................................................45
2
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
GND
NC
NC
GND
AVDD
SCLK
DB1M
DB1P
DB0M
DB0P
5 Pin Configuration and Functions
40
39
38
37
36
35
34
33
32
31
PDN/SYNC
1
30
IOVDD
VREF
2
29
FCLKM
REFGND
3
28
FCLKP
REFBUF
4
27
NC
AVDD
5
26
IOGND
CLKP
6
25
DCLKINP
CLKM
7
24
DCLKINM
VCM
8
23
DCLKP
RESET
9
22
DCLKM
21
IOVDD
GND PAD (backside)
14
15
16
17
18
AVDD
SEN
DA1M
DA1P
19
20
DA0P
13
DA0M
12
GND
GND
11
AINM
10
AINP
SDIO
Figure 5-1. RSB (WQFN) Package, 40-Pin
(Top View)
Table 5-1. Pin Descriptions
PIN
NAME
NO.
TYPE
DESCRIPTION
INPUT/REFERENCE
AINP
12
I
Positive analog input
AINM
13
I
Negative analog input
VCM
8
O
Common-mode voltage output for the analog inputs, 0.95 V
VREF
2
I
External voltage reference input, 1.6 V
REFBUF
4
I
1.2V external voltage reference input for use with internal reference buffer
REFGND
3
I
Reference ground input, 0 V
CLKM
7
I
Negative differential sampling clock input for the ADC
CLKP
6
I
Positive differential sampling clock input for the ADC
1
I
Power down/Synchronization input. This pin can be configured via the SPI interface. Active
high. This pin has an internal 21 kΩ pull-down resistor.
RESET
9
I
Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SEN
16
I
Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
SCLK
35
I
Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
CLOCK
CONFIGURATION
PDN/SYNC
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Table 5-1. Pin Descriptions (continued)
PIN
NAME
NO.
SDIO
NC
TYPE
DESCRIPTION
10
I
Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
27,38,39
-
Do not connect
DIGITAL INTERFACE
DA0P
20
O
Positive differential serial LVDS output for lane 0, channel A
DA0M
19
O
Negative differential serial LVDS output for lane 0, channel A
DA1P
18
O
Positive differential serial LVDS output for lane 1, channel A
DA1M
17
O
Negative differential serial LVDS output for lane 1, channel A
DB0P
31
O
Positive differential serial LVDS output for lane 0, channel B.
Used only in dual band complex decimation. Default is powered down.
DB0M
32
O
Negative differential serial LVDS output for lane 0, channel B.
Used only in dual band complex decimation. Default is powered down.
DB1P
33
O
Positive differential serial LVDS output for lane 1, channel B.
Used only in dual band complex decimation. Default is powered down.
DB1M
34
O
Negative differential serial LVDS output for lane 1, channel B.
Used only in dual band complex decimation. Default is powered down.
DCLKP
23
O
Positive differential serial LVDS bit clock output.
DCLKM
22
O
Negative differential serial LVDS bit clock output.
FCLKP
28
O
Positive differential serial LVDS frame clock output.
FCLKM
29
O
Negative differential serial LVDS frame clock output.
DCLKINP
25
I
Positive differential serial LVDS bit clock input.
DCLKINM
24
I
Negative differential serial LVDS bit clock input.
AVDD
5,15,36
I
Analog 1.8-V power supply
GND
11,14,37,40,
PowerPad
I
Ground, 0 V
IOGND
26
I
Ground, 0 V for digital interface
IOVDD
21,30
I
1.8-V power supply for digital interface
POWER SUPPLY
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
MAX
Supply voltage range, AVDD, IOVDD
–0.3
2.1
V
Supply voltage range, GND, IOGND, REFGND
–0.3
0.3
V
AINP/M, CLKP/M, VREF, REFBUF
–0.3
MIN(2.1, AVDD+0.3)
PDN/SYNC, RESET, SCLK, SEN, SDIO
–0.3
MIN(2.1, AVDD+0.3)
DCLKINP/M
–0.3
MIN(2.1, IOVDD+0.3)
Voltage applied to
input pins
TEST CONDITIONS
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
V
105
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
pins(1)
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
UNIT
2500
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply
voltage range IOVDD(1)
1.75
1.8
1.85
V
1.75
1.8
1.85
V
TA
Operating free-air temperature
–40
105
°C
TJ
Operating junction temperature
105(2)
°C
AVDD(1)
(1)
(2)
Measured to GND.
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADC356x
THERMAL
METRIC(1)
RSB (QFN)
UNIT
40 Pins
RΘJA
Junction-to-ambient thermal resistance
30.7
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
16.4
°C/W
RΘJB
Junction-to-board thermal resistance
10.5
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
10.5
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics - Power Consumption
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3561: 10 MSPS
IAVDD
Analog supply current
External reference
18
27
IIOVDD
I/O supply current
SLVDS 1-wire
25
43
PDIS
Power dissipation
External reference, SLVDS 1-wire
77
126
1-wire, 1/2-swing
19
IIOVDD
I/O supply current
2-wire
29
4x real decimation, 1-wire
26
mA
mW
mA
ADC3562: 25 MSPS
IAVDD
Analog supply current
External reference
20
27
IIOVDD
I/O supply current
1-wire
27
43
PDIS
Power dissipation
External reference, 1-wire
85
126
1-wire, 1/2-swing
21
2-wire
30
4x real decimation, 1-wire
29
IIOVDD
I/O supply current
mA
mW
mA
ADC3563: 65 MSPS
IAVDD
Analog supply current
External reference
40
51
IIOVDD
I/O supply current
2-wire
28
43
PDIS
Power dissipation
External reference, 2-wire
123
169
IIOVDD
I/O supply current
2-wire, 1/2-swing
21
4x real decimation, 1-wire
27
16x real decimation, 1-wire
25
4x complex decimation, 1-wire
33
16x complex decimation, 1-wire
28
mA
mW
mA
MISCELLANOUS
IAVDD
Internal reference, additional analog
supply current
1
External 1.2 V reference (REFBUF),
additional analog supply current
0.3
Single ended clock input, reduces
analog supply current by
PDIS
6
Power consumption in global power
down mode
Enabled via SPI
0.7
Default mask settings, internal
reference
5
Default mask settings, external
reference
9
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mW
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6.6 Electrical Characteristics - DC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
No missing codes
16
PSRR
FIN = 1 MHz
bits
50
dB
ADC3561 - 10 MSPS: DC ACCURACY
DNL
Differential nonlinearity
FIN = 4.9 MHz
± 0.4
± 0.85
LSB
INL
Integral nonlinearity
FIN = 4.9 MHz
±3
±5
LSB
VOS_ERR
Offset error
32
135
VOS_DRIFT
Offset drift over temperature
GAINERR
Gain error
External 1.6V Reference
0.43
%FSR
GAINDRIFT
Gain drift over temperature
External 1.6V Reference
0.85
ppm/ºC
GAINERR
Gain error
Internal Reference
-1.15
%FSR
GAINDRIFT
Gain drift over temperature
Internal Reference
90
ppm/ºC
Transition Noise
Transition Noise
1.3
LSB
-0.004
LSB
LSB/ºC
ADC3562 - 25 MSPS: DC ACCURACY
DNL
Differential nonlinearity
FIN = 5 MHz
± 0.4
± 0.85
LSB
INL
Integral nonlinearity
FIN = 5 MHz
±3
±5
LSB
VOS_ERR
Offset error
32
± 135
VOS_DRIFT
Offset drift over temperature
GAINERR
Gain error
External 1.6V Reference
-0.25
%FSR
GAINDRIFT
Gain drift over temperature
External 1.6V Reference
0.08
ppm/ºC
GAINERR
Gain error
Internal Reference
-1.9
%FSR
GAINDRIFT
Gain drift over temperature
Internal Reference
86
ppm/ºC
1.3
LSB
0.009
Transition Noise
LSB
LSB/ºC
ADC3563 - 65 MSPS: DC ACCURACY
DNL
Differential nonlinearity
FIN = 5 MHz
INL
Integral nonlinearity
FIN = 5 MHz
VOS_ERR
Offset error
VOS_DRIFT
Offset drift over temperature
GAINERR
Gain error
External 1.6V Reference
GAINDRIFT
Gain drift over temperature
External 1.6V Reference
GAINERR
Gain error
Internal Reference
GAINDRIFT
Gain drift over temperature
Internal Reference
242
ppm/ºC
1.3
LSB
Transition Noise
± 0.7
± 0.85
LSB
±3
±5
LSB
± 33
± 135
LSB
0.05
LSB/ºC
± 2.3
%FSR
68
ppm/ºC
± 3.5
%FSR
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6.6 Electrical Characteristics - DC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC ANALOG INPUT (AINP/M)
FS
Input full scale
Differential
3.2
VCM
Input common model voltage
RIN
Differential input resistance
FIN = 100 kHz
CIN
Differential input Capacitance
FIN = 100 kHz
VOCM
Output common mode voltage
BW
Analog Input Bandwidth (-3dB)
900
MHz
0.9
0.95
Vpp
1.0
V
8
kΩ
7
pF
0.95
V
Internal Voltage Reference
VREF
Internal reference voltage
VREF Output Impedance
External reference voltage
1.6
V
8
Ω
1.2
V
Reference Input Buffer (REFBUF)
VREF
1.6
V
Input Current
0.3
mA
Input impedance
5.3
kΩ
External voltage reference (VREF)
Input clock
frequency
Input clock frequency
0.5
VID
Differential input voltage
VCM
Input common mode voltage
1
65
MHz
3.6
Vpp
0.9
V
5
kΩ
1.5
pF
Clock Input (CLKP/M)
RIN
CIN
Single ended input capacitance
Clock duty cycle
Clock duty cycle
40
50
60
%
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input current
IIL
Low level input current
CI
Input capacitance
VOH
1.4
V
90
-150
IOVDD
– 0.1
High level output voltage
0.4
V
150
uA
-90
uA
1.5
pF
IOVDD
V
Digital Output (SDOUT)
VOL
Low level output voltage
ILOAD = 400 uA
Output data rate
Output data rate
per differential SLVDS output pair
VID
Differential input voltage
DCLKIN
VCM
Input common mode voltage
DCLKIN
VOD
Differential output voltage
VCM
Output common mode voltage
0.1
V
1000
Mbps
650
mVpp
SLVDS Interface
8
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200
350
1
1.2
1.3
V
500
700
850
mVpp
1.0
V
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6.7 Electrical Characteristics - AC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C
to TMAX = 105°C, ADC sampling rate = 10-65 MSPS, external reference, 50% clock duty cycle, AVDD = IOVDD = 1.8 V,
external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3561: 10 MSPS
NSD
Noise Spectral Density
SNR
Signal to noise ratio
No input signal
-150.0
fIN = 1.1 MHz
SINAD
fIN = 4.9 MHz
Signal to noise and distortion ratio
82.0
80.5
81.9
fIN = 1.1 MHz
81.9
80.0
fIN = 9.9 MHz
THD
Effective number of bits
fIN = 4.9 MHz
Total Harmonic Distortion (First five
harmonics)
Non HD2,3
Spur free dynamic range including
second and third harmonic distortion
Spur free dynamic range (excluding
HD2 and HD3)
13.3
fIN = 1.1 MHz
86
81
fIN = 4.9 MHz
Two tone inter-modulation distortion
86
dBc
86
81
86
fIN = 9.9 MHz
94
fIN = 1.1 MHz
100
fIN = 4.9 MHz
bit
95
fIN = 1.1 MHz
fIN = 9.9 MHz
IMD3
13.3
fIN = 9.9 MHz
fIN = 4.9 MHz
dBFS
13.3
13.0
fIN = 9.9 MHz
SFDR
81.9
dBFS
81.8
fIN = 1.1 MHz
ENOB
82.0
fIN = 9.9 MHz
fIN = 4.9 MHz
dBFS/Hz
92
100
dBc
dBFS
102
f1 = 3 MHz, f2 = 4 MHz, AIN = -7 dBFS/
tone
88
f1 = 10 MHz, f2 = 12 MHz, AIN = -7
dBFS/tone
90
dBc
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6.7 Electrical Characteristics - AC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C
to TMAX = 105°C, ADC sampling rate = 10-65 MSPS, external reference, 50% clock duty cycle, AVDD = IOVDD = 1.8 V,
external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3562: 25 MSPS
NSD
Noise Spectral Density
No input signal
-154.0
fIN = 1.1 MHz
fIN = 5 MHz
SNR
Signal to noise ratio
Signal to noise and distortion ratio
82.0
80.5
81.9
fIN = 20 MHz
81.6
fIN = 40 MHz
78.6
fIN = 1.1 MHz
81.9
80.0
81.9
fIN = 20 MHz
81.5
fIN = 40 MHz
78.5
fIN = 5 MHz
Effective number of bits
Total Harmonic Distortion (First five
harmonics)
THD
SFDR
Spur free dynamic range including
second and third harmonic distortion
13.3
13.2
fIN = 40 MHz
12.7
fIN = 1.1 MHz
85
81
88
fIN = 20 MHz
83
fIN = 40 MHz
85
fIN = 1.1 MHz
86
81
Non HD2,3
IMD3
10
Two tone inter-modulation distortion
89
fIN = 20 MHz
83
fIN = 40 MHz
86
dBc
101
92
101
fIN = 10 MHz
100
fIN = 20 MHz
99
fIN = 40 MHz
94
f1 = 3 MHz, f2 = 4 MHz, AIN = -7 dBFS/
tone
84
f1 = 10 MHz, f2 = 12 MHz, AIN = -7
dBFS/tone
86
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dBc
90
fIN = 10 MHz
fIN = 5 MHz
bit
89
fIN = 10 MHz
fIN = 1.1 MHz
Spur free dynamic range (excluding
HD2 and HD3)
13.3
fIN = 20 MHz
fIN = 5 MHz
dBFS
13.3
13.0
fIN = 10 MHz
fIN = 5 MHz
dBFS
81.9
fIN = 10 MHz
fIN = 1.1 MHz
ENOB
82.0
fIN = 10 MHz
fIN = 5 MHz
SINAD
dBFS/Hz
dBFS
dBc
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6.7 Electrical Characteristics - AC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C
to TMAX = 105°C, ADC sampling rate = 10-65 MSPS, external reference, 50% clock duty cycle, AVDD = IOVDD = 1.8 V,
external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3563: 65 MSPS
NSD
Noise Spectral Density
No input signal
-158.0
fIN = 1.1 MHz
fIN = 5 MHz
SNR
SINAD
ENOB
Signal to noise ratio
Signal to noise and distortion ratio
Effective number of bits
82.0
80.0
81.9
fIN = 20 MHz
81.6
fIN = 40 MHz
80.5
fIN = 70 MHz
77.0
fIN = 1.1 MHz
80.2
fIN = 5 MHz
80.2
fIN = 10 MHz
80.2
fIN = 20 MHz
80.0
fIN = 40 MHz
78.5
fIN = 70 MHz
75.5
fIN = 1.1 MHz
13.0
fIN = 5 MHz
13.0
fIN = 10 MHz
13.0
fIN = 20 MHz
13.0
fIN = 40 MHz
12.8
fIN = 70 MHz
12.3
fIN = 1.1 MHz
THD
Total Harmonic Distortion (First five
harmonics)
Spur free dynamic range including
second and third harmonic distortion
Non HD2,3
IMD3
Spur free dynamic range (excluding
HD2 and HD3)
Two tone inter-modulation distortion
dBFS
bit
89
87
fIN = 20 MHz
82
fIN = 40 MHz
82
fIN = 70 MHz
81
fIN = 1.1 MHz
82
82
90
fIN = 20 MHz
83
fIN = 40 MHz
84
fIN = 70 MHz
83
fIN = 1.1 MHz
100
91
dBc
90
fIN = 10 MHz
fIN = 5 MHz
dBFS
81
81
fIN = 10 MHz
fIN = 5 MHz
SFDR
82.0
fIN = 10 MHz
fIN = 5 MHz
dBFS/Hz
dBc
100
fIN = 10 MHz
98
fIN = 20 MHz
97
fIN = 40 MHz
92
fIN = 70 MHz
86
f1 = 1 MHz, f2 = 2 MHz, AIN = -7 dBFS/
tone
97
f1 = 10 MHz, f2 = 12 MHz, AIN = -7
dBFS/tone
96
dBFS
dBc
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6.8 Timing Requirements
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ADC Timing Specifications
tAD
Aperture Delay
0.85
tA
Aperture Jitter
tJ
Jitter on DCLKIN
tACQ
Signal acquisition period, referenced to
sampling clock falling edge
square wave clock with fast edges
Time to valid data after coming out of power
down. Internal reference.
Wake up
time
Time to valid data after coming out of power
down. External 1.6V reference.
tS,SYNC
Setup time for SYNC input signal
tH,SYNC
Hold time for SYNC input signal
ADC
Latency
Add.
Latency
180
fs
± 50
Signal conversion period, referenced to
sampling clock falling edge
tCONV
ns
Signal input to data output
FS = 65 Msps
-TS/4
FS = 25 Msps
-TS/2
FS = 10 Msps
-TS/2
FS = 65 Msps
+TS ×
5/8
FS = 25 Msps
+TS ×
3/8
FS = 10 Msps
+TS ×
1/5
Sampling
Clock
Period
Sampling
Clock
Period
Bandgap reference enabled, single ended
clock
17.6
Bandgap reference enabled, differential clock
12.9
Bandgap reference disabled, single ended
clock
2.2
Bandgap reference disabled, differential clock
2.2
Bandgap reference enabled, single ended
clock
15.9
Bandgap reference enabled, differential clock
12.9
Bandgap reference disabled, single ended
clock
1.7
Bandgap reference disabled, differential clock
1.7
Referenced to sampling clock rising edge
ps
500
us
ms
us
ms
ps
600
2-wire SLVDS
2
1-wire SLVDS
1
1/2-wire SLVDS
1
Real decimation by 2
21
Complex decimation by 2
22
Real or complex decimation by 4, 8, 16, 32
23
Clock
cycles
Output
clock
cycles
Interface Timing: Serial LVDS Interface
tPD
12
Propagation delay: sampling clock falling
edge to DCLK rising edge
Delay between sampling clock falling edge to
2+
3+
4+
DCLKIN falling edge < 2.5ns.
TDCLK TDCLK TDCLK
TDCLK = DCLK period
+
+
+
tCDCLK = Sampling clock falling edge to
tCDCLK tCDCLK tCDCLK
DCLKIN falling edge
Delay between sampling clock falling edge to
DCLKIN falling edge >= 2.5ns.
2+
3+
4+
TDCLK = DCLK period
tCDCLK tCDCLK tCDCLK
tCDCLK = Sampling clock falling edge to
DCLKIN falling edge
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ns
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6.8 Timing Requirements (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and
–1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
DCLK rising edge to output data delay,
2-wire SLVDS
tCD
DCLK rising edge to output data delay,
1-wire SLVDS
MIN
NOM
Fout = 10 MSPS, DA/B0,1 = 80 MBPS
0.0
0.1
Fout = 25 MSPS, DA/B0,1 = 200 MBPS
0.0
0.1
Fout = 65 MSPS, DA/B0,1 = 520 MBPS
0.0
0.1
Fout = 10 MSPS, DA/B0 = 160 MBPS
0.0
0.1
Fout = 25 MSPS, DA/B0 = 400 MBPS
0.0
0.1
-0.6
0.1
Fout = 5 MSPS, DA0 = 160 MBPS
0.0
0.1
Fout = 10 MSPS, DA0 = 320 MBPS
0.0
0.1
Fout = 62.5 MSPS, DA/B0= 1000 MBPS
DCLK rising edge to output data delay,
1/2-wire SLVDS
Fout = 25 MSPS, DA0 = 800 MBPS
Data valid, 2-wire SLVDS
tDV
Data valid, 1-wire SLVDS
Data valid, 1/2-wire SLVDS
0.0
0.1
Fout = 10 MSPS, DA/B0,1 = 80 MBPS
11.9
12.1
Fout = 25 MSPS, DA/B0,1 = 200 MBPS
4.5
4.6
Fout = 65 MSPS, DA/B0,1 = 520 MBPS
1.4
1.5
Fout = 10 MSPS, DA/B0 = 160 MBPS
5.7
5.8
Fout = 25 MSPS, DA/B0 = 400 MBPS
2.0
2.1
Fout = 62.5 MSPS, DA/B0= 1000 MBPS
0.5
0.6
Fout = 5 MSPS, DA0 = 160 MBPS
5.7
5.8
Fout = 10 MSPS, DA0 = 320 MBPS
2.7
2.8
Fout = 25 MSPS, DA0 = 800 MBPS
0.8
0.9
MAX
UNIT
ns
ns
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency
tSU(SEN)
SEN to rising edge of SCLK
tH(SEN)
SEN from rising edge of SCLK
tSU(SDIO)
SDIO to rising edge of SCLK
tH(SDIO)
SDIO from rising edge of SCLK
20
MHz
10
ns
9
ns
17
ns
9
ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD)
SDIO tri-state to driven
3.9
10.8
ns
t(ODZ)
SDIO data to tri-state
3.4
14
ns
t(OD)
SDIO valid from falling edge of SCLK
3.9
10.8
ns
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.9 Typical Characteristics - ADC3561
0
0
-20
-20
-40
-40
Amplitude (dBFS)
Amplitude (dBFS)
Typical values at TA = 25 °C, ADC sampling rate = 10 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
-60
-80
-80
-100
-100
-120
-120
-140
-140
0
1
2
3
Input Frequency (MHz)
4
5
0
SNR = 82.1 dBFS, SFDR = 87 dBc, Non HD23 = 102 dBFS
Figure 6-1. Single Tone FFT at FIN = 1.1 MHz
0
-20
-20
-40
-40
-60
-80
4
5
-60
-80
-100
-100
-120
-120
-140
-140
0
1
2
3
Input Frequency (MHz)
4
5
0
AIN = -7 dBFS/tone, IMD3 = 88 dBc
4
5
Figure 6-4. Two Tone FFT at FIN = 3,4 MHz
Ext REF
Int REF
105
100
83
95
82
90
81
85
14
ENOB (bit)
84
SFDR, Non HD23 (dBc)
SNR, int REF
SFDR, int REF
Non HD23, int REF
2
3
Input Frequency (MHz)
14.5
110
SNR, ext REF
SFDR, ext REF
Non HD23, ext REF
1
AIN = -20 dBFS/tone, IMD3 = 89 dBc
Figure 6-3. Two Tone FFT at FIN = 3,4 MHz
86
SNR (dBFS)
2
3
Input Frequency (MHz)
SNR = 82.5 dBFS, SFDR = 82 dBc, Non HD23 = 103 dBFS
0
85
1
Figure 6-2. Single Tone FFT at FIN = 1.1 MHz, AIN = -20 dBFS
Amplitude (dBFS)
Amplitude (dBFS)
-60
13.5
13
80
0
10
20
Input Frequency (MHz)
30
80
40
Figure 6-5. AC Performance vs Input Frequency
14
12.5
0
10
20
Input Frequency (MHz)
30
40
Figure 6-6. ENOB vs Input Frequency
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.9 Typical Characteristics - ADC3561 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 10 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
84
110
SNR
SFDR
115
SNR
SFDR
82.5
80
82
70
81.5
60
81
50
80.5
40
80
30
79.5
20
10
-60
-50
-40
-30
-20
Input Amplitude (dBFS)
-10
110
83
105
82
100
81
95
80
90
79
85
78
0
5
6
7
8
Sampling Rate (MSPS)
FIN = 1.1 MHz
84
85
SFDR
105
82
100
81
95
80
1.5
2
Clock Amplitude (Vpp)
2.5
SFDR
105
83
100
82
95
90
81
90
85
80
1.7
3
1.75
FIN = 1.1 MHz
1.8
AVDD (V)
1.85
85
1.9
FIN = 1.1 MHz
Figure 6-9. AC Performance vs Clock Amplitude
83.5
Figure 6-10. AC Performance vs AVDD
5
105
SNR (dBFS), -40°C
SNR (dBFS), 25°C
SNR (dBFS), 105°C
Non HD23
84
SNR (dBFS)
83
1
110
SNR
SFDR (dBc)
SNR (dBFS)
Figure 6-8. AC Performance vs Sampling Rate
110
79
0.5
80
10
FIN = 1.1 MHz
Figure 6-7. AC Performance vs Input Amplitude
SNR
9
SFDR, Non HD23 (dBc)
-70
84
SFDR, Non HD23 (dBc)
90
SNR (dBFS)
83
79
-80
SFDR (dBc), -40°C
SFDR (dBc), 25°C
SFDR (dBc), 105°C
4
100
95
82
90
81.5
85
Integral Nonlinearity (LSB)
82.5
3
SFDR (dBc)
83
SNR (dBFS)
Non HD23
100
SFDR, Non HD23 (dBc)
SNR (dBFS)
85
Non HD23
83.5
2
1
0
-1
-2
-3
-4
81
0.9
80
0.925
0.95
VCM (V)
0.975
1
-5
0
8192
16384 24576 32768 40960 49152 57344 65536
Code
FIN = 1.1 MHz
Figure 6-11. AC Performance vs VCM vs Temperature
FIN = 1.1 MHz
Figure 6-12. INL vs Code
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.9 Typical Characteristics - ADC3561 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 10 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
1
30%
25%
0.5
20%
0.25
Count (%)
Differential Nonlinearity (LSB)
0.75
0
15%
-0.25
10%
-0.5
5%
-0.75
-1
0
0
8192
16384 24576 32768 40960 49152 57344 65536
Code
32759 32760 32761 32762 32763 32764 32765 32766 32767
Output Code
FIN = 1.1 MHz
Figure 6-14. DC Offset Histogram
28
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
IAVDD , ext REF
IAVDD , int REF
Bypass
/4 real
/8 real
/32 real
IIOVDD, 2-w
IIOVDD, 1-w
/2 real
/4 complex
/8 complex
/32 complex
27
Current (mA)
Current (mA)
Figure 6-13. DNL vs Code
26
25
24
0
1
2
3
4
5
6
7
Sampling Rate (MSPS)
8
9
10
0
1
2
3
4
5
6
7
Sampling Rate (MSPS)
8
9
10
FIN = 1.1 MHz, 1-wire
FIN = 1.1 MHz, DDC Bypass
Figure 6-16. IIOVDD Current vs Decimation
Figure 6-15. Current vs Sampling Rate
35
IIOVDD, 2-w
IIOVDD, 1-w
IIOVDD, 2-w (half swing)
IIOVDD, 1-w (half swing)
Current (mA)
30
25
20
15
0
1
2
3
4
5
6
7
Sampling Rate (MSPS)
8
9
10
FIN = 1.1 MHz, Complex Decimation by 32
Figure 6-17. IIOVDD Current vs Interface
16
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.10 Typical Characteristics - ADC3562
0
0
-20
-20
-40
-40
Amplitude (dBFS)
Amplitude (dBFS)
Typical values at TA = 25 °C, ADC sampling rate = 25 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
Input Frequency (MHz)
10
12.5
0
SNR = 82.1 dBFS, SFDR = 87 dBc, Non HD23 = 102 dBFS
12.5
Figure 6-19. Single Tone FFT at FIN = 5 MHz
0
0
-20
-20
-40
-40
Amplitude (dBFS)
Amplitude (dBFS)
10
SNR = 82.0 dBFS, SFDR = 92 dBc, Non HD23 = 101 dBFS
Figure 6-18. Single Tone FFT at FIN = 1 MHz
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
Input Frequency (MHz)
10
12.5
0
SNR = 82.5 dBFS, SFDR = 82 dBc, Non HD23 = 101 dBFS
-20
-20
-40
-40
Amplitude (dBFS)
0
-80
12.5
-60
-80
-100
-100
-120
-120
-140
10
Figure 6-21. Single Tone FFT at FIN = 10 MHz
0
-60
5
Input Frequency (MHz)
SNR = 81.9 dBFS, SFDR = 85 dBc, Non HD23 = 101 dBFS
Figure 6-20. Single Tone FFT at FIN = 5 MHz, AIN = -20 dBFS
Amplitude (dBFS)
5
Input Frequency (MHz)
-140
0
5
Input Frequency (MHz)
10
12.5
SNR = 81.7 dBFS, SFDR = 83 dBc, Non HD23 = 98 dBFS
Figure 6-22. Single Tone FFT at FIN = 20 MHz
0
5
Input Frequency (MHz)
10
12.5
SNR = 78.8 dBFS, SFDR = 87 dBc, Non HD23 = 98 dBFS
Figure 6-23. Single Tone FFT at FIN = 40 MHz
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.10 Typical Characteristics - ADC3562 (continued)
0
0
-20
-20
-40
-40
Amplitude (dBFS)
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
Input Frequency (MHz)
10
12.5
0
5
Input Frequency (MHz)
AIN = -7 dBFS/tone, IMD3 = 84 dBc
10
12.5
AIN = -7 dBFS/tone, IMD3 = 87 dBc
Figure 6-24. Two Tone FFT at FIN = 3/4 MHz
Figure 6-25. Two Tone FFT at FIN = 10/12 MHz
0
86
-20
110
SNR, ext REF
SFDR, ext REF
Non HD23, ext REF
85
SNR, int REF
SFDR, int REF
Non HD23, int REF
105
SNR (dBFS)
Amplitude (dBFS)
-40
-60
-80
84
100
83
95
82
90
81
85
-100
-120
80
-140
0
5
Input Frequency (MHz)
10
0
12.5
10
20
Input Frequency (MHz)
SFDR, Non HD23 (dBc)
Amplitude (dBFS)
Typical values at TA = 25 °C, ADC sampling rate = 25 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
80
40
30
Figure 6-27. AC Performance vs Input Frequency
AIN = -20 dBFS/tone, IMD3 = 88 dBc
Figure 6-26. Two Tone FFT at FIN = 10/12 MHz
84
110
SNR
Ext REF
Int REF
SFDR
Non HD23
83.5
100
83
90
82.5
80
82
70
81.5
60
81
50
80.5
40
SNR (dBFS)
ENOB (bit)
14
13.5
13
12.5
0
10
20
Input Frequency (MHz)
30
40
80
30
79.5
20
79
-80
SFDR, Non HD23 (dBc)
14.5
10
-70
-60
-50
-40
-30
-20
Input Amplitude (dBFS)
-10
0
FIN = 1.1 MHz
Figure 6-28. ENOB vs Input Frequency
Figure 6-29. AC Performance vs Input Amplitude
18
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.10 Typical Characteristics - ADC3562 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 25 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
115
110
83
105
82
100
81
95
80
90
79
85
78
15
Sampling Rate (MSPS)
20
83
105
82
100
81
95
80
90
79
0.5
80
25
SFDR
85
1
1.5
2
Clock Amplitude (Vpp)
FIN = 1.1 MHz
85
83
100
82
95
81
90
1.8
AVDD (V)
1.85
85
1.9
100
82.5
95
82
90
81.5
85
81
0.9
80
0.925
FIN = 1.1 MHz
0.95
VCM (V)
0.975
1
FIN = 1.1 MHz
Figure 6-32. AC Performance vs AVDD
Figure 6-33. AC Performance vs VCM vs Temperature
5
1
4
0.75
Differential Nonlinearity (LSB)
3
Integral Nonlinearity (LSB)
SFDR (dBc), -40°C
SFDR (dBc), 25°C
SFDR (dBc), 105°C
83
SNR (dBFS)
105
1.75
105
SNR (dBFS), -40°C
SNR (dBFS), 25°C
SNR (dBFS), 105°C
84
80
1.7
83.5
Non HD23
SFDR, Non HD23 (dBc)
SNR (dBFS)
Figure 6-31. AC Performance vs Clock Amplitude
110
SFDR
3
FIN = 1.1 MHz
Figure 6-30. AC Performance vs Sampling Rate
SNR
2.5
SFDR (dBc)
10
110
SNR
84
5
84
Non HD23
SNR (dBFS)
SFDR
SFDR, Non HD23 (dBc)
SNR (dBFS)
SNR
SFDR (dBc)
85
2
1
0
-1
-2
-3
0.5
0.25
0
-0.25
-0.5
-0.75
-4
-1
-5
0
8192
16384 24576 32768 40960 49152 57344 65536
Code
0
8192
16384 24576 32768 40960 49152 57344 65536
Code
FIN = 1.1 MHz
Figure 6-34. INL vs Code
FIN = 1.1 MHz
Figure 6-35. DNL vs Code
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SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
6.10 Typical Characteristics - ADC3562 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 25 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
40%
35%
25%
Current (mA)
Count (%)
30%
20%
15%
10%
5%
0
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
IAVDD , ext REF
IAVDD , int REF
0
32766 32767 32768 32769 32770 32771 32772 32773 32774 32775
Output Code
5
Figure 6-36. DC Offset Histogram
IIOVDD, 2-w
IIOVDD, 1-w
10
15
Sampling Rate (MSPS)
20
25
FIN = 1.1 MHz, DDC Bypass
Figure 6-37. Current vs Sampling Rate
30
40
Bypass
/4 real
/8 real
/32 real
29
/2 real
/4 complex
/8 complex
/32 complex
IIOVDD, 2-w
IIOVDD, 1-w
IIOVDD, 2-w (half swing)
IIOVDD, 1-w (half swing)
35
Current (mA)
Current (mA)
28
27
30
25
26
20
25
24
15
0
5
10
15
Sampling Rate (MSPS)
20
FIN = 1.1 MHz, 1-wire
Figure 6-38. IIOVDD Current vs Decimation
20
25
0
5
10
15
Sampling Rate (MSPS)
20
25
FIN = 1.1 MHz, Complex Decimation by 32
Figure 6-39. IIOVDD Current vs Interface
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6.11 Typical Characteristics - ADC3563
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
SNR = 82.2 dBFS, SFDR = 81 dBc, Non HD23 = 103 dBFS
Figure 6-40. Single Tone FFT at FIN = 1 MHz
SNR = 82.4 dBFS, SFDR = 86 dBc, Non HD23 = 103 dBFS
Figure 6-42. Single Tone FFT at FIN = 5 MHz, AIN = -20 dBFS
SNR = 80.0 dBFS, SFDR = 83 dBc, Non HD23 = 93 dBFS
Figure 6-44. Single Tone FFT at FIN = 40 MHz
SNR = 82.2 dBFS, SFDR = 90 dBc, Non HD23 = 102 dBFS
Figure 6-41. Single Tone FFT at FIN = 5 MHz
SNR = 81.9 dBFS, SFDR = 89 dBc, Non HD23 = 98 dBFS
Figure 6-43. Single Tone FFT at FIN = 10 MHz
SNR = 77.7 dBFS, SFDR = 86 dBc, Non HD23 = 89 dBFS
Figure 6-45. Single Tone FFT at FIN = 64 MHz
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6.11 Typical Characteristics - ADC3563 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
SNR = 74.1 dBFS, SFDR = 75 dBc, Non HD23 = 88 dBFS
Figure 6-46. Single Tone FFT at FIN = 100 MHz
AIN = -20 dBFS/tone, IMD3 = 98 dBc
22
AIN = -7 dBFS/tone, IMD3 = 88 dBc
Figure 6-47. Two Tone FFT at FIN = 10/12 MHz
AIN = -7 dBFS/tone, IMD3 = 89 dBc
Figure 6-48. Two Tone FFT at FIN = 10/12 MHz
Figure 6-49. Two Tone FFT at FIN = 40/45 MHz
Figure 6-50. AC Performance vs Input Frequency
Figure 6-51. ENOB vs Input Frequency
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6.11 Typical Characteristics - ADC3563 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
FIN = 5 MHz
FIN = 5 MHz
Figure 6-52. AC Performance vs Input Amplitude
Figure 6-54. AC Performance vs Clock Amplitude
Figure 6-53. AC Performance vs Sampling Rate
Single Ended Clock Input
Figure 6-55. AC Performance vs Clock Amplitude
FIN = 5 MHz
FIN = 5 MHz
Figure 6-56. AC Performance vs AVDD
Figure 6-57. AC Performance vs VCM vs Temperature
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6.11 Typical Characteristics - ADC3563 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
FIN = 5 MHz
FIN = 5 MHz
Figure 6-58. AC Performance vs Clock Duty Cycle
FIN = 5 MHz
Figure 6-59. INL vs Code
Figure 6-61. DC Offset Histogram
Figure 6-60. DNL vs Code
FIN = 5 MHz, 2-wire
FIN = 5 MHz, DDC Bypass
Figure 6-62. Current vs Sampling Rate
24
Figure 6-63. Current vs Decimation
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6.11 Typical Characteristics - ADC3563 (continued)
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V,
external 1.6 V voltage reference, unless otherwise noted.
FIN = 5 MHz, Complex Decimation by 32
Figure 6-64. Current vs Output Interface
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7 Parameter Measurement Information
Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tConversion
tCDCLK
DCLKIN
DCLK
TDCLK
tCD
FCLK
tDV
DA1/DB1
(MSB)
D15 D13 D11
D9
D7
D5
D3
D1
D15 D13 D11
D9
D7
D5
D3
D1
DA0/DB0
(LSB)
D14 D12 D10
D8
D6
D4
D2
D0
D14 D12 D10
D8
D6
D4
D2
D0
Sample N-1
Sample N-2
Figure 7-1. Timing diagram: 2-wire SLVDS (default output bit mapper)
Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tConversion
tCDCLK
DCLKIN
DCLK
tCD
TDCLK
FCLK
tDV
DA0
D2
DB0
D2
D1
D0
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sample N-2
Sample N-1
Figure 7-2. Timing diagram: 1-wire SLVDS (default output bit mapper)
26
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Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tConversion
tCDCLK
DCLKIN
DCLK
tCD
FCLK
TDCLK
tDV
Channel A
Channel B
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DA0
Sample N-2
Sample N-1
Figure 7-3. Timing diagram:1/2-wire SLVDS (default output bit mapper)
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8 Detailed Description
8.1 Overview
The ADC356x is a low noise, ultra-low power 16-bit high-speed single channel ADC supporting sampling rates
up to 65 Msps. It offers very good DC precision together with IF sampling support which makes it ideally suited
for a wide range of applications. The ADC356x is equipped with an on-chip internal reference option but it also
supports the use of an external, high precision 1.6 V voltage reference or an external 1.2V reference which is
buffered and gained up internally. Because of the inherent low latency architecture, the digital output result is
available after only one to two clock cycles. Single ended as well as differential input signaling is supported.
An optional programmable digital down converter enables external anti-alias filter relaxation as well as output
data rate reduction. An internal mux enables dual band complex decimation with independent NCO frequency
tuning. The digital filter provides a 32-bit programmable NCO and supports both real or complex decimation.
The ADC356x family uses a serial LVDS (SLVDS) interface to output the data which minimizes the number
of digital interconnects. The device supports a two-lane (2-wire), a one-lane (1-wire) and a half-lane (1/2-wire)
option. The ADC356x includes a digital output formatter which supports output resolutions from 14 to 20-bit.
The device features and control options can be set up either through pin configurations or via SPI register writes.
8.2 Functional Block Diagram
REFBUF
1.2V REF
NCO
NCO
ADC
16bit
AIN
VCM
Digital Downconverter
Crosspoint
Switch
VREF
N
N
DCLKIN
Dig I/F
SLVDS
0.95V
DCLK
FCLK
DA0/1
DB0/1
CLK
SCLK
SEN
SDIO
RESET
28
PDN/SYNC
Control
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8.3 Feature Description
8.3.1 Analog Input
The analog inputs of ADC356x are intended to be driven differentially. Both AC coupling and DC coupling of the
analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which
must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that
meets the device input common mode voltage range.
The equivalent input network diagram is shown in Figure 8-1. All four sampling switches, on-resistance shown in
red are in same position (open or closed) simultaneously.
AVDD
Sampling Switch
xINP/
xINM
1
2 nH
0.32 pF
125
24
1.4 pF
0.15 pF
0.6 pF
0.6 pF
GND
GND
GND
6.4 pF
7
GND
GND
GND
5
0.7 pF
GND
1.6 pF
GND
GND
Figure 8-1. Equivalent Input Network
8.3.1.1 Analog Input Bandwidth
Figure 8-2 shows the analog full power input bandwidth of the ADC356x with a 50 Ω differential termination.
The -3 dB bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is
approximately 120 MHz.
The equivalent differential input resistance RIN and input capacitance CIN vs frequency are shown in Figure 8-3.
Normalized Gain Response (dB)
0
-1
-2
-3
-4
-5
-6
10
100
Input Frequency (MHz)
1000
ADC3
Figure 8-2. ADC Analog Input bandwidth response
Figure 8-3. Equivant RIN, CIN vs Input Frequency
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8.3.1.2 Analog Front End Design
The ADC356x is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch
from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low
output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in
AC-coupled applications which can be combined with the termination network.
8.3.1.2.1 Sampling Glitch Filter Design
The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter
performance is dependent on input frequency and therefore the following filter designs are recommended for
different input frequency ranges as shown in Figure 8-4 and Figure 8-5.
33
10
180nH
100 pF
Termination
33
180nH
10
Figure 8-4. Sampling glitch filter example for input frequencies from DC to 30 MHz
33
10
120nH
100pF
82 pF
Termination
33
10
120nH
100pF
Figure 8-5. Sampling glitch filter example for input frequencies from 30 to 70 MHz
30
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8.3.1.2.2 Analog Input Termination and DC Bias
Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.
8.3.1.2.2.1 AC-Coupling
The ADC356x requires external DC bias using the common mode output voltage (VCM) of the ADC together
with the termination network as shown in Figure 8-6. The termination is located within the glitch filter network.
When using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of
the transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier
performance.
Glitch Filter
Termination
33
1 uF
10
180nH
25
100 pF
VCM
0.1 …F
33
25
1 uF
VCM
180nH
10
Figure 8-6. AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)
8.3.1.2.2.2 DC-Coupling
In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using
VCM output of the ADC as shown in Figure 8-7. The glitch filter in this case is located between the anti-alias filter
and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part
of the anti-alias filter.
Glitch Filter
33
10
180nH
AAF (Anti
Alias Filter)
100 pF
33
VCM
180nH
10
Figure 8-7. DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 30 MHz)
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8.3.1.3 Auto-Zero Feature
The ADC356x includes an internal auto-zero front end amplifier circuit which improves the 1/f flicker noise. This
auto-zero feature is enabled by default for the ADC3561/2 and can be enabled using SPI register writes for the
ADC3563 (register 0x11, D0). The 4M point FFTs below show the autozero feature enabled vs disabled.
0
-80
Auto-zero DIS
Auto-zero EN
Auto-zero DIS
Auto-zero EN
-90
-20
-100
Amplitude (dBFS)
Amplitude (dBFS)
-40
-60
-80
-100
-110
-120
-130
-140
-120
-150
-140
0
1
2
3
Input Frequency (MHz)
4
-160
0.01
5
1
10
100
Frequency (kHz)
Figure 8-8. FS = 10 MSPS, FIN = 1.1 MHz
0
0.1
Figure 8-9. FS = 10 MSPS, FIN = 1.1 MHz
-80
Auto-zero DIS
Auto-zero EN
Auto-zero DIS
Auto-zero EN
-90
-20
-100
Amplitude (dBFS)
Amplitude (dBFS)
-40
-60
-80
-100
-110
-120
-130
-140
-120
-150
-140
0
32
2.5
5
7.5
Input Frequency (MHz)
10
12.5
-160
0.01
0.1
1
10
100
Frequency (kHz)
Figure 8-10. FS = 25 MSPS, FIN = 1.1 MHz
Figure 8-11. FS = 25 MSPS, FIN = 1.1 MHz
Figure 8-12. FS = 65 MSPS, FIN = 5 MHz
Figure 8-13. FS = 65 MSPS, FIN = 5 MHz
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8.3.2 Clock Input
In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential
signaling with a high slew rate. This is especially important in IF sampling applications (Figure 8-14 and Figure
8-15). For less jitter sensitive applications, the ADC356x provides the option to operate with single ended
signaling which saves additional power consumption.
Figure 8-14. AC Performance vs Clock Amplitude
(Differential Clock Input)
Figure 8-15. AC Performance vs Clock Amplitude
(Single Ended Clock Input)
8.3.2.1 Single Ended vs Differential Clock Input
The ADC356x can be operated using a differential or a single ended clock input where the single ended clock
consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently
the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.
•
•
Differential Clock Input: The clock input can be AC coupled externally. The ADC356x provides internal bias.
Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with
the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC
coupled around a 0.9V center. The unused input needs to be AC coupled to ground.
1.8V
CLKP
CLKP
+
0.9V
5kO
0V
VCM
0.9V
CLKM
5kO
CLKM
-
Figure 8-16. External and internal connection using differential (left) and single ended (right) clock input
8.3.2.2 Signal Acquisition Time Adjust
The ADC356x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for
clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer
time for the driving amplifier to settle out the signal which can improve the SNR performance of the system. This
register should only be used for the 65 MSPS speed grade (ADC3563) For the 10 and 25 MSPS device speed
grades the sampling time is already set to TS/2. When powering down the DLL, the acquisition time will track the
clock duty cycle (50% is recommended).
Table 8-1. Acquisition time vs DLL PDN setting
SAMPLING CLOCK FS (MSPS)
DLL PDN (0x11, D2)
ACQUISITION TIME (tACQ)
65
0
TS / 4
≤ 40
1
TS / 2
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8.3.3 Voltage Reference
The ADC356x provides three different options for supplying the voltage reference to the ADC. An external 1.6V
reference can be directly connected to the VREF input; a voltage 1.2V reference can be connected to the
REFBUF input using the internal gain buffer or the internal 1.2V reference can be enabled to generate a 1.6V
reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1
uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC356x is shown in Figure
8-17.
Note
The voltage reference mode can be selected using SPI writes or by using the REFBUF pin (default)
as a control pin (Configuration using PINs only). If the REFBUF pin is not used for configuration, the
REFBUF pin should be connected to AVDD (even though the REFBUF pin has a weak internal pullup
to AVDD) and the voltage reference option has to be selected using the SPI interface.
AINP
AINM
VCM
0.95V
VREF
(1.6V)
x1.33
REFBUF
(1.2V)
VREF1.2
REFGND
Figure 8-17. Different voltage reference options for ADC356x
8.3.3.1 Internal voltage reference
The 1.6V reference for the ADC can be generated internal using the on-chip 1.2V reference along with the
internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) should be connected between the
VREF and REFGND pins as close to the pins as possible.
xINP
xINM
VCM
0.95V
VREF
(1.6V)
x1.33
CVREF
REFBUF
(1.6V)
VREF1.2
REFGND
Figure 8-18. Internal reference
34
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8.3.3.2 External voltage reference (VREF)
For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6V
reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) connected between the VREF and REFGND
pins and placed as close to the pins as possible is recommended. The load current from the external reference
is about 1mA.
Note: The internal reference is also used for other functions inside the device, therefore the reference amplifier
should only be powered down in power down state but not during normal operation.
xINP
xINM
VCM
0.95V
VREF
(1.6V)
Reference
1.6V
CVREF
REFBUF
(1.2V)
x1.33
VREF1.2
REFGND
Figure 8-19. External 1.6V reference
8.3.3.3 External voltage reference with internal buffer (REFBUF)
The ADC356x is equipped with an on-chip reference buffer that also includes gain to generate the 1.6V
reference voltage from an external 1.2V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF)
between the VREF and REFGND pins and a 10 uF and a 0.1 uF ceramic bypass capacitor between the
REFBUF and REFGND pins are recommended. Both capacitors should be placed as close to the pins as
possible. The load current from the external reference is less than 100uA.
xINP
xINM
VCM
0.95V
VREF
(1.6V)
Reference
1.2V
REFBUF
(1.2V)
x1.33
VREF1.2
CREFBUF
CVREF
REFGND
Figure 8-20. External 1.2V reference using internal reference buffer
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8.3.4 Digital Down Converter
The ADC356x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled
via SPI register settings. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a
32-bit numerically controlled oscillator (NCO) as shown in Figure 8-21. Furthermore it supports a mode with real
decimation where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and
the digital filter acts as a low pass filter.
Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR
degradation due to quantization noise. The Output Formatter truncates to the selected resolution prior to
outputting the data on the digital interface.
NCO
32bit
Filter
I
Q
ADC
I
Q
N
Digital
Interface
SYNC
Figure 8-21. Internal Digital Decimation Filter
8.3.4.1 DDC MUX for Dual Band Decimation
The ADC356x contains a MUX in front of the digital decimation filter which allows the ADC to be connected to
two digital down converters (see Figure 8-22). This enables dual band complex decimation. The NCO of each
digital down converter can be tuned to an independent frequency across the Nyquist zone as illustrated in the
example in Figure 8-23. The second DDC is output using the DB0/1 SLVDS interface.
Digital Downconverter
DDC MUX
NCO
ADC
14bit
N
NCO
N
Figure 8-22. DDC MUX
Input Signal B
Decimation
by 8
Input Signal A
Shifted Input Signal A
Negative Image
Shifted Input Signal B
Negative Image
0
FNCO B
FNCO A
FS/2
-FS/16
0
FS/16
-FS/16
0
FS/16
Figure 8-23. Complex Decimation (by 8) with dual band illustration
36
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8.3.4.2 Digital Filter Operation
The complex decimation operation is illustrated with an example in Figure 8-24. First the input signal (and the
negative image) are frequency shifted by the NCO frequency as shown on the left. Next a digital filter is applied
(centered around 0 Hz) and the output data rate is decimated - in this example the output data rate FS,OUT =
FS/8 with a Nyquist zone of FS/16. During the complex mixing the spectrum (signal and noise) is split into real
and complex parts and thus the amplitude is reduced by 6-dB. In order to compensate this loss, there is a 6-dB
digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
(Alias)
-FIN + FNCO
Shifted Input
Signal (Alias)
Shifted Input Signal
Negative Image
Input Signal
Negative Image
Decimation
by 8
FIN + FNCO
-FS/2
0
FS/2
FNCO
-FS/2
-FS/16
0
FS/16
FS/2
NCO Tuning Range
Figure 8-24. Complex decimation illustration
The real decimation operation is illustrated with an example in Figure 8-25. There is no frequency shift
happening and only the real portion of the complex digital filter is exercised. The output data rate is decimated a decimation of 8 would result in an output data rate FS,OUT = FS/8 with a Nyquist zone of FS/16.
During the real mixing the spectrum (signal and noise) amplitude is reduced by 3-dB. In order to compensate this
loss, there is a 3-dB digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
Decimation by
32
Decimation by
16
Decimation by 2
Decimation by 4
Decimation by 8
FS/32
FS/16
FS/8
FS/4
FS/2
FS/64
Figure 8-25. Real decimation illustration
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8.3.4.3 FS/4 Mixing with Real Output
In this mode, the output after complex decimation gets mixed with FS/4 (FS = output data rate in this case).
Instead of a complex output with the input signal centered around 0 Hz, the output is transmitted as a real output
at twice the data rate and the signal is centered around FS/4 (Fout/4) as illustrated in Figure 8-26.
In this example, complex decimation by 8 is used. The output data is transmitted as a real output with an output
rate of Fout = FS'/4 (FS' = ADC sampling rate). The input signal is now centered around FS/4 (Fout/4) or FS'/16.
FIN
FNCO
- FIN + FNCO
-FIN + FNCO + FS/4
/8
FS/4 mix
Fout/4 mix
Complex
Decimation /8
0
0
FS/2
0
)6¶/2
FS/16
)6¶/2
FS/8
Figure 8-26. FS/4 Mixing with real output
8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
The decimation block is equipped with a 32-bit NCO and a digital mixer to fine tune the frequency placement
prior to the digital filtering. The oscillator generates a complex exponential sequence of:
ejωn (default) or e–jωn
(1)
where: frequency (ω) is specified as a signed number by the 32-bit register setting
The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to
a frequency equal to fIN + fNCO. The NCO frequency can be tuned from –FS/2 to +FS/2 and is processed as a
signed, 2s complement number. After programming a new NCO frequency, the MIXER RESTART register bit or
SYNC pin has to be toggled for the new frequency to get active. Additionally the ADC356x provides the option
via SPI to invert the mixer phase.
The NCO frequency setting is set by the 32-bit register value given and calculated as:
NCO frequency = 0 to + FS/2: NCO = fNCO × 232 / FS
NCO frequency = -FS/2 to 0: NCO = (fNCO + FS) × 232 / FS
where:
• NCO = NCO register setting (decimal value)
• fNCO = Desired NCO frequency (MHz)
• FS = ADC sampling rate (MSPS)
The NCO programming is further illustrated with this example:
•
•
•
ADC sampling rate FS = 65 MSPS
Input signal fIN = 10 MHz
Desired output frequency fOUT = 0 MHz
For this example there are actually four ways to program the NCO and achieve the desired output frequency as
shown in Table 8-2.
Table 8-2. NCO value calculations example
Alias or negative image
fNCO
NCO Value
fIN = –10 MHz
fNCO = 10 MHz
660764199
fIN = 10 MHz
fNCO = –10 MHz
3634203097
fIN = 10 MHz
fNCO = 10 MHz
660764199
fIN = –10 MHz
fNCO = –10 MHz
3634203097
38
Mixer Phase
as is
inverted
Frequency translation for fOUT
fOUT = fIN + fNCO = –10 MHz +10 MHz = 0 MHz
fOUT = fIN + fNCO = 10 MHz + (–10 MHz) = 0 MHz
fOUT = fIN – fNCO = 10 MHz – 10 MHz = 0 MHz
fOUT = fIN – fNCO = –10 MHz – (–10 MHz) = 0 MHz
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8.3.4.5 Decimation Filter
The ADC356x supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and
a stopband rejection of at least 85 dB. Table 8-3 gives an overview of the pass-band bandwidth of the different
decimation settings with respect to ADC sampling rate FS. In real decimation mode the output bandwidth is half
of the complex bandwidth.
Table 8-3. Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX
DECIMATION
Complex
Real
DECIMATION
SETTING N
OUTPUT RATE
OUTPUT
BANDWIDTH
OUTPUT RATE
(FS = 65 MSPS)
OUTPUT BANDWIDTH
(FS = 65 MSPS)
2
FS / 2 complex
4
FS / 4 complex
0.8 × FS / 2
32.5 MSPS complex
26 MHz
0.8 × FS / 4
16.25 MSPS complex
8
13 MHz
FS / 8 complex
0.8 × FS / 8
8.125 MSPS complex
6.5 MHz
16
FS / 16 complex
0.8 × FS / 16
4.0625 MSPS complex
3.25 MHz
32
FS / 32 complex
0.8 × FS / 32
2.03125 MSPS complex
1.625 MHz
2
FS / 2 real
0.4 × FS / 2
32.5 MSPS
13 MHz
4
FS / 4 real
0.4 × FS / 4
16.25 MSPS
6.5 MHz
8
FS / 8 real
0.4 × FS / 8
8.125 MSPS
3.25 MHz
16
FS / 16 real
0.4 × FS / 16
4.0625 MSPS
1.625 MHz
32
FS / 32 real
0.4 × FS / 32
2.03125 MSPS
0.8125 MHz
The decimation filter responses are normalized to the ADC sampling clock frequency FS and illustrated in Figure
8-28 to Figure 8-37. They are interpreted as follows:
Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 8-27.
The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.
For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS /
8 or 0.125 × F S. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band
is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at
0.25 × FS and 0.5 × FS. The stop-band attenuation is greater than 85 dB.
0
Passband
Transition Band
Alias Band
Attn Spec
-20
Filter
Transition
Bands
Amplitude (dB)
-40
Bands that alias on top
of signal band
Pass Band
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (Fs)
Figure 8-27. Interpretation of the Decimation Filter Plots
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0
Passband
Transition Band
Alias Band
Attn Spec
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
Passband
Transition Band
Alias Band
Attn Spec
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
0.25
Normalized Frequency (Fs)
Decb
Figure 8-28. Decimation by 2 complex frequency
response
Decb
Figure 8-29. Decimation by 2 complex passband
ripple response
0
0
Passband
Transition Band
Alias Band
Attn Spec
-20
Passband
Transition Band
Alias Band
Attn Spec
-0.01
-0.02
-0.03
-40
Amplitude (dB)
Amplitude (dB)
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-60
-80
-0.04
-0.05
-0.06
-0.07
-0.08
-100
-0.09
-120
-0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
0
Figure 8-30. Decimation by 4 complex frequency
response
Amplitude (dB)
Amplitude (dB)
-40
-60
-80
-100
-120
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Frequency (Fs)
0.4
0.45
0.5
0.04
0.05
0.06
0.07
0.08
0.09
-0.08
-0.081
-0.082
-0.083
-0.084
-0.085
-0.086
-0.087
-0.088
-0.089
-0.09
-0.091
-0.092
-0.093
-0.094
-0.095
-0.096
-0.097
-0.098
-0.099
-0.1
0.1
0.11
0.12
Decb
Passband
Transition Band
Alias Band
Attn Spec
0
0.006
0.012
0.018
0.024
0.03
0.036
0.042
Normalized Frequency (Fs)
Decb
Figure 8-32. Decimation by 8 complex frequency
response
40
0.03
Figure 8-31. Decimation by 4 complex passband
ripple response
Passband
Transition Band
Alias Band
Attn Spec
0
0.02
Normalized Frequency (Fs)
0
-20
0.01
Decb
0.048
0.054
0.06
Decb
Figure 8-33. Decimation by 8 complex passband
ripple response
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-0.1
0
Passband
Transition Band
Alias Band
Attn Spec
-0.12
-0.13
-40
Amplitude (dB)
Amplitude (dB)
-20
Passband
Transition Band
Alias Band
Attn Spec
-0.11
-60
-80
-0.14
-0.15
-0.16
-0.17
-0.18
-100
-0.19
-120
-0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
0
0.006
0.009
0.012
0.015
0.018
0.021
0.024
0.027
0.03
Normalized Frequency (Fs)
Figure 8-34. Decimation by 16 complex frequency
response
Decb
Figure 8-35. Decimation by 16 complex passband
ripple response
-0.2
0
Passband
Transition Band
Alias Band
Attn Spec
-20
Passband
Transition Band
Alias Band
Attn Spec
-0.205
-0.21
-0.215
-40
Amplitude (dB)
Amplitude (dB)
0.003
Decb
-60
-80
-0.22
-0.225
-0.23
-0.235
-0.24
-100
-0.245
-120
-0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Normalized Frequency (Fs)
0.45
0.5
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
Normalized Frequency (Fs)
Decb
Figure 8-36. Decimation by 32 complex frequency
response
0.016
0.018
0.02
Decb
Figure 8-37. Decimation by 32 complex passband
ripple response
8.3.4.6 SYNC
The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/
SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is
latched in by the rising edge of the sampling clock as shown in Figure 8-38.
CLK
tS,SYNC
tH,SYNC
SYNC
Figure 8-38. External SYNC timing diagram
The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register
or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks
as well as I and Q data within the same sample. If no SYNC signal is given the internal clock dividers will not
be synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the
NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit).
When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is
an integer. This ensures phase continuity of the clock divider.
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8.3.4.7 Output Formatting with Decimation
When using decimation, the output data is formatted as shown in Figure 8-39 (complex decimation) and Figure
8-40 (real decimation).
FCLK
Used in
Single
Band
Serial LVDS
2-Wire
(8x Serialization)
DA1
AI
D15
AI
D13
AI
D11
AI
D9
AI
D7
AI
D5
AI
D3
AI
D1
AQ
D15
AQ
D13
AQ
D11
AQ
D9
AQ
D7
AQ
D5
AQ
D3
AQ
D1
DA0
AI
D14
AI
D12
AI
D10
AI
D8
AI
D6
AI
D4
AI
D2
AI
D0
AQ
D14
AQ
D12
AQ
D10
AQ
D8
AQ
D6
AQ
D4
AQ
D2
AQ
D0
DB1
BI
D15
BI
D13
BI
D11
BI
D9
BI
D7
BI
D5
BI
D3
BI
D1
BQ
D15
BQ
D13
BQ
D11
BQ
D9
BQ
D7
BQ
D5
BQ
D3
BQ
D1
DB0
BI
D14
BI
D12
BI
D10
BI
D8
BI
D6
BI
D4
BI
D2
BI
D0
BQ
D14
BQ
D12
BQ
D10
BQ
D8
BQ
D6
BQ
D4
BQ
D2
BQ
D0
Only used for
Dual Band
DCLK
FCLK
Serial LVDS
1-Wire
(16x Serialization)
Used in
Single Band
DA0
AI
AQ
Only used for
Dual Band
DB0
BI
BQ
DCLK
FCLK
Serial LVDS
1/2-Wire
(32x Serialization)
Only used for
Dual Band
AI
DA0
BI
AQ
BQ
DCLK
Figure 8-39. Output Data Format in Complex Decimation
Table 8-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output
resolution and complex decimation by 4.
Table 8-4. Serial LVDS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
N
FS
R
L
FS / N
[DA/B0,1] / 2
FS x 2 x R / L / N
130 MHz
260 MHz
4
65 MSPS
62.5 MSPS
42
2
16
1
1/2
16.25 MHz
15.625 MHz
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260 MHz
520 MHz
500 MHz
1000 MHz
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FCLK
DA1
A0
D15
A0
D13
A0
D11
A0
D9
A0
D7
A0
D5
A0
D3
A0
D1
A1
D15
A1
D13
A1
D11
A1
D9
A1
D7
A1
D5
A1
D3
A1
D1
DA0
A0
D14
A0
D12
A0
D10
A0
D8
A0
D6
A0
D4
A0
D2
A0
D0
A1
D14
A1
D12
A1
D10
A1
D8
A1
D6
A1
D4
A1
D2
A1
D0
2-Wire
8x Serialization
DCLK
FCLK
1-Wire
16x Serialization
DA0
A0
A1
DCLK
Figure 8-40. Output Data Format in Real Decimation
Table 8-5 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output
resolution and real decimation by 4.
Table 8-5. Serial LVDS Lane Rate Examples with Real Decimation and 16-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
M
FS
R
L
FS / M / 2 (L = 2)
FS / M (L = 1, 1/2)
[DA/B0,1] / 2
FS x R / L / M
4
65 MSPS
16
2
8.125 MHz
65 MHz
130 MHz
1
16.25 MHz
130 MHz
260 MHz
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8.3.5 Digital Interface
The serial LVDS interface supports the data output with 2-wire, 1-wire and 1/2-wire operation. The actual data
output rate depends on the output resolution and number of lanes used.
The ADC356x requires an external serial LVDS clock input (DCLKIN), which is used to transmit the data out of
the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the sampling clock is
irrelevant but both clocks need to be frequency locked. The SLVDS interface is configured using SPI register
writes.
8.3.5.1 Output Formatter
The digital output interface utilizes a flexible output bit mapper as shown in Figure 8-41. The bit mapper takes
the 16bit output directly from the ADC or from digital filter block and reformats it to a resolution of 14, 16, 18 or
20-bit. With parallel output format the maximum output resolution supported is 16-bit. With serial LVDS output
the output serialization factor gets adjusted accordingly for 2-, 1- and 1/2-wire interface mode. The maximum
output data rate can not be exceeded independently of output resolution and serialization factor.
With 14-bit output resolution the 2 LSBs are truncated.
TEST
PATTERN
N
DIG
I/F
Output
Formatter
14/16/18/
20-bit
NCO
Output
Scrambler
Output
Bit Mapper
Figure 8-41. Interface output bit mapper
Table 8-6 provides an overview for the resulting serialization factor depending on output resolution and output
modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output
resolution to 14-bit, 2-wire mode for example would result in DCLKIN = FS * 3.5 instead of * 4.
The output bit mapper can be used for bypass and decimation filter.
Table 8-6. Serialization Factor vs Output Resolution for Different Output Modes
OUTPUT
RESOLUTION
14-bit
16-bit (default)
18-bit
20-bit
Interface
SERIALIZATION
FCLK
DCLKIN
DCLK
D0/D1
2-Wire
7x
FS/2
FS* 3.5
FS* 3.5
FS* 7
1-Wire
14x
FS
FS* 7
FS* 7
FS* 14
1/2-Wire
28x
FS
FS* 14
FS* 14
FS* 28
2-Wire
8x
FS/2
FS* 4
FS* 4
FS* 8
1-Wire
16x
FS
FS* 8
FS* 8
FS* 16
1/2-Wire
32x
FS
FS* 16
FS* 16
FS* 32
2-Wire
9x
FS/2
FS* 4.5
FS* 4.5
FS* 9
1-Wire
18x
FS
FS* 9
FS* 9
FS* 18
1/2-Wire
36x
FS
FS* 18
FS* 18
FS* 36
2-Wire
10x
FS/2
FS* 5
FS* 5
FS* 10
1-Wire
20x
FS
FS* 10
FS* 10
FS* 20
1/2-Wire
40x
FS
FS* 20
FS* 20
FS* 40
The programming sequence to change the output interface and/or resolution from default settings is shown in
Output Interface/Mode Configuration.
44
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8.3.5.2 Output Bit Mapper
The output bit mapper allows change to the output bit order for any selected interface mode.
NCO
TEST
PATTERN
N
Output
Formatter
14/16/18/
20-bit
DIG
I/F
Output
Scrambler
Output
Bit Mapper
Figure 8-42. Output Bit Mapper
There is a two step process to change the output bit mapping and assemble the output data bus:
1. Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier
bit as shown in Table 8-7. The MSB starts with bit D19 – depending on output resolution chosen the LSB
would be D6 (14-bit) to D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap the
serial output format.
Table 8-7. Unique identifier of each data bit
Bit
Channel A
Channel B
Previous sample (2w only)
Current sample
Previous sample (2w only)
Current sample
D19 (MSB)
0x2D
0x6D
0x29
0x69
D18
0x2C
0x6C
0x28
0x68
D17
0x27
0x67
0x23
0x63
D16
0x26
0x66
0x22
0x62
D15
0x25
0x65
0x21
0x61
D14
0x24
0x64
0x20
0x60
D13
0x1F
0x5F
0x1B
0x5B
D12
0x1E
0x5E
0x1A
0x5A
D11
0x1D
0x5D
0x19
0x59
D10
0x1C
0x5C
0x18
0x58
D9
0x17
0x57
0x13
0x53
D8
0x16
0x56
0x12
0x52
D7
0x15
0x55
0x11
0x51
D6
0x14
0x54
0x10
0x50
D5
0x0F
0x4F
0x0B
0x4B
D4
0x0E
0x4E
0x0A
0x4A
D3
0x0D
0x4D
0x09
0x49
D2
0x0C
0x4C
0x08
0x48
D1
0x07
0x47
0x03
0x43
D0 (LSB)
0x06
0x46
0x02
0x42
In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the
serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address
0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper
is applied to both the “I” and the “Q” sample.
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2-wire mode: in this mode both the current and the previous sample have to be used in the address space
as shown in Figure 8-43. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused
addresses between samples for resolution less than 20-bit (gray back ground), which can be ignored if not used.
14-bit
16-bit 18-bit 20-bit
14-bit
16-bit 18-bit 20-bit
0x5F 0x60 0x5D 0x5E 0x5B 0x5C 0x59 0x5A 0x57 0x58 0x55 0x56 0x53 0x54 0x51 0x52 0x4F 0x50 0x4D 0x4E
0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57 0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
DA1
14/18-bit
16/20-bit
DA0
14/18-bit 0x4B 0x4C 0x49 0x4A 0x47 0x48 0x45 0x46 0x43 0x44 0x41 0x42 0x3F 0x40 0x3D 0x3E 0x3B 0x3C 0x39 0x3A
16/20-bit 0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39
DB1
14/18-bit
16/20-bit
DB0
14/18-bit 0x73 0x74 0x71 0x72 0x6F 0x70 0x6D 0x6E 0x6B 0x6C 0x69 0x6A 0x67 0x68 0x65
16/20-bit 0x74 0x73 0x72 0x71 0x70 0x6F 0x6E 0x6D 0x6C 0x6B 0x6A 0x69 0x68 0x67 0x66
0x87 0x88 0x85 0x85 0x83 0x83 0x81 0x81 0x7F 0x7F 0x7D 0x7E 0x7B 0x7C 0x79 0x7A 0x77 0x78 0x75 0x76
0x88 0x87 0x86 0x86 0x84 0x84 0x82 0x82 0x80 0x80 0x7E 0x7D 0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75
Previous Sample
0x66 0x63 0x64 0x61 0x62
0x65 0x64 0x63 0x62 0x61
Current Sample
Figure 8-43. 2-wire output bit mapper
In the following example (Figure 8-44), the 16-bit 2-wire serial output is reordered to where lane DA1/DB1 carries
the 8 MSB and lane DA0/DB0 carries 8 LSBs.
DA1
DA0
DB1
DB0
D19A
(0x60
0x2D)
D11A
(0x4C
0x1D)
D18A
(0x5F
0x2C)
D10A
(0x4B
0x1C)
D17A
(0x5E
0x27)
D9A
(0x4A
0x17)
Previous Sample
D16A
D15A
(0x5D
(0x5C
0x26)
0x25)
D8A
D7A
(0x49
(0x48
0x16)
0x15)
D14A
(0x5B
0x24)
D6A
(0x47
0x14)
D13A
(0x5A
0x1F)
D5A
(0x46
0x0F)
D12A
(0x59
0x1E)
D4A
(0x45
0x0E)
D19A
(0x56
0x6D)
D11A
(0x42
0x5D)
D18A
(0x55
0x6C)
D10A
(0x41
0x5C)
D17A
(0x54
0x67)
D9A
(0x40
0x57)
Current Sample
D16A
D15A
(0x53
(0x52
0x66)
0x65)
D8A
D7A
(0x39
(0x38
0x56)
0x55)
D14A
(0x51
0x64)
D6A
(0x37
0x54)
D13A
(0x50
0x5F)
D5A
(0x36
0x4F)
D12A
(0x4F
0x5E)
D4A
(0x35
0x4E)
D19B
(0x88
0x29)
D11B
(0x74
0x19)
D18B
(0x87
0x28)
D10B
(0x73
0x18)
D17B
(0x86
0x23)
D9B
(0x72
0x13)
D16B
(0x85
0x22)
D8B
(0x71
0x12)
D14B
(0x83
0x20)
D6B
(0x6F
0x10)
D13B
(0x82
0x1B)
D5B
(0x6E
0x0B)
D12B
(0x81
0x1A)
D4B
(0x6D
0x0A)
D19B
(0x7E
0x69)
D11B
(0x6A
0x59)
D18B
(0x7D
0x68)
D10B
(0x69
0x58)
D17B
(0x7C
0x63)
D9B
(0x68
0x53)
D16B
(0x7B
0x62)
D8B
(0x67
0x52)
D14B
(0x79
0x60)
D6B
(0x65
0x50)
D13B
(0x78
0x5B)
D5B
(0x64
0x4B)
D12B
(0x77
0x5A)
D4B
(0x63
0x4A)
D15B
(0x84
0x21)
D7B
(0x70
0x11)
D15B
(0x7A
0x61)
D7B
(0x66
0x51)
Figure 8-44. Example: 2-wire output bit mapping
1-wire mode: Only the ‘current’ sample needs to programmed in the address space. If desired, it can be
duplicated on DA1/DB1 as well (using addresses shown below) in order to have a redundant output. Lane
DA1/DB1 needs to be powered up in that case.
14-bit
16-bit
18-bit
20-bit
DA0
(default)
0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39
DA1
0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57 0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
DB0
(default)
DB1
0x74 0x73 0x72 0x71 0x70 0x6F 0x6E 0x6D 0x6C 0x6B 0x6A 0x69 0x68 0x67 0x66
0x65 0x64 0x63 0x62 0x61
0x88 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80 0x7F 0x7E 0x7D 0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75
Figure 8-45. 1-wire output bit mapping
½-wire mode: The output is only lane DA0 and the sample order is programmed into the 40 addresses of
chA (from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown below. If desired, it can be
duplicated on DB0 as well (using addresses shown Figure 8-46) in order to have a redundant output. Lane DB0
needs to be powered up in that case.
16-bit
14-bit
18-bit
20-bit
14-bit
16-bit
18-bit
20-bit
DA0
(default)
0x4C 0x4B
...
0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x60 0x5F
...
0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
DB0
0x88 0x87
...
0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75 0x74 0x73
...
0x68 0x67 0x66
0x65 0x64 0x63 0x62 0x61
Figure 8-46. 1/2-wire output bit mapping
46
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8.3.5.3 Output Scrambler
The device includes an optional output scrambler feature. Scrambling is performed on each serial output lane
independently. When enabled, the serial output bit stream is scrambled where each output bit is XOR-ed with
2 previous bits (k-14 and k-15) as shown in Figure 8-47. For descrambling, note that the output bit mapper is
located after the scrambler.
On the external receiver, the incoming serial data stream can be descrambled by XOR-ing each incoming bit
with 2 previous bits (k-14 and k-15).
Scrambler
Bit Mapper
Scrambler
Bit Mapper
Lane 0
Digital
Lane 1
Figure 8-47. Output scrambling per lane
Scrambler
Serial bit stream
x[k]
z-1
XOR
z-1
z-1
y[k-1]
...
z-1
z-1
y[k-2]
y[k-15]
y[k-14]
Serial output bit stream
y[k]
De-Scrambler
y[k-1]
z-1
y[k-2]
z-1
y[k-14]
z-1
...
y[k-15]
z-1
z-1
XOR
Serial bit stream
x[k]
Figure 8-48. Output scrambler and descrambler operation
Scrambling is enabled by disabling digital bypass (register 0x24, D2) and enabling scrambling (register 0x22,
D6).
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8.3.5.4 Output Interface/Mode Configuration
The following sequence summarizes all the relevant registers for changing the output interface and/or enabling
the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining
steps can come in any order.
Table 8-8. Configuration steps for changing interface or decimation
STEP
FEATURE
ADDRESS
DESCRIPTION
Select the output interface bit mapping depending on resolution and output interface.
1
Output Resolution
2-wire
14-bit
0x2B
16-bit
0x4B
18-bit
0x2B
20-bit
0x4B
0x07
2
0x13
1-wire
1/2-wire
0x6C
0x8D
Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to
0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
Configure the FCLK frequency based on bypass/decimation and number of lanes used.
Bypass/Dec
3
0x19
Complex
Decimation
Output
Interface
4
Bypass/ Real
Decimation
0x1B
SLVDS
FCLK SRC
(D7)
FCLK DIV
(D4)
TOG FCLK
(D0)
2-wire
0
1
0
1-wire
0
0
0
1/2-wire
0
0
0
2-wire
1
0
0
1-wire
1
0
0
1/2-wire
0
0
1
Select the output interface resolution using the bit mapper (D5-D3).
Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
Output Resolution
0x20
0x21
0x22
5
Real Decimation
1-wire
14-bit
0xFE000
16-bit
0xFF000
18-bit
0xFF800
20-bit
14-bit
Complex
Decimation
2-wire
use default
16-bit
18-bit
1/2-wire
use default
0xFFC00
0xFFFFF
0xFFFFF
20-bit
0x39..0x60 Change output bit mapping for chA and chB if desired. This works also with the default interface
0x61..0x88 selection.
6
7
0x24
0x22
Enable scrambling
8
0x24
Enable the decimation filter
0x25
Configure the decimation filter
9
0x2A/B/C/D
Program the NCO frequency for complex decimation (can be skipped for real decimation)
0x31/2/3/4
10
Configure the complex output data stream (set both bits to 0 for real decimation)
Decimation
Filter
11
12
48
0x27
0x2E
0x26
SLVDS
OP-Order (D4)
Q-Delay (D3)
2-wire
1
0
1-wire
0
1
1/2-wire
1
1
Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.
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8.3.5.4.1 Configuration Example
The following is a step by step programming example to configure the ADC356x to complex decimation by 8 with
1-wire SLVDS and 16-bit output.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire SLVDS)
0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)
0x19 0x80 (configure FCLK)
0x1B 0x88 (select 16-bit output resolution)
0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)
0x24 0x06 (enable decimation filter)
0x25 0x30 (configure complex decimation by 8)
0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency)
0x27/0x2E 0x08 (configure Q-delay register bit)
0x26 0xAA, 0x26 0x88 (set digital mixer gain to 6-dB and toggle the mixer update)
8.3.5.5 Output Data Format
The output data can be configured to two's complement (default) or offset binary formatting using SPI register
writes (register 0x8F and 0x92). Table 8-9 provides an overview for minimum and maximum output codes for the
two formatting options. The actual output resolution is set by the output bit mapper.
Table 8-9. Overview of minimum and maximum output codes vs output resolution for different formatting
Two's Complement (default)
RESOLUTION (BIT)
14
VIN,MAX
0x1FFF
0
VIN,MIN
16
18
0x7FFF
0x1FFFF
0x0000
0x2000
Offset Binary
20
14
16
18
20
0x7FFFF
0x3FFF
0xFFFF
0x3FFFF
0xFFFFF
0x2000
0x8000
0x20000
0x80000
0x00000
0x8000
0x20000
0x80000
0x0000
0x00000
8.3.6 Test Pattern
In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled
via SPI register writes (0x14/0x15/0x16). The test pattern generator is located after the decimation filter as
shown in Figure 8-49. In decimation mode (real and complex), the test patterns replace the output data of the
DDC - however channel A controls the test patterns for both channels.
NCO
N
TEST
PATTERN
Output
Formatter
14/16/18/
20-bit
DIG
I/F
Output
Scrambler
Output
Bit Mapper
Figure 8-49. Test Pattern Generator
•
•
RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native
resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in
RAMP pattern mode.
– 00001: 18-bit output resolution
– 00100: 16-bit output resolution
– 10000: 14-bit output resolution
Custom Pattern: Configured in the CUSTOM PAT register
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8.4 Device Functional Modes
8.4.1 Normal operation
In normal operating mode, the entire ADC full scale range gets converted to a digital output with 16-bit
resolution. The output is available in as little as 1 clock cycle on the digital SLVDS outputs.
8.4.2 Power Down Options
A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is
an internal pull-down 21kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to
be pulled high externally to enter global power down mode.
The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in
order to trade off power consumption vs wake up time.
REFBUF
1.2V REF
Digital Downconverter
Crosspoint
Switch
VREF
NCO
NCO
N
AIN
N
ADC
Dig I/F
CLK
Figure 8-50. Power Down Configurations
Table 8-10. Overview of Power Down Options
Function/ Register
PDN
via SPI
Mask for
Global PDN
Feature Default
Power
Impact
Wake-up
time
ADC
Yes
-
Enabled
Reference gain amplifier
Yes
Enabled
~ 0.4 mA
~3 us
Internal 1.2V reference
Yes
External ref
~ 1-3.5 mA
~3 ms
Internal/external reference selection is
available through SPI and REFBUF pin.
Differential
clock
~ 1 mA
n/a
Single ended clock input saves ~ 1mA
compared to differential.
Some programmability is available
through the REFBUF pin.
Depending on output interface mode,
unused output drivers can be powered
down for maximum power savings
ADC is included in Global PDN
automatically
Yes
50
Comment
Clock buffer
Yes
Output interface drivers
Yes
-
Enabled
varies
n/a
Decimation filter
Yes
-
Disabled
see electrical
table
n/a
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8.5 Programming
The device is primarily configured and controlled using the serial programming interface (SPI) however it can
operate in a default configuration without requiring the SPI interface. Furthermore the power down function as
well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).
Note
The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.
After initial power up, the default operating configuration for each device is shown in Table 8-11.
Table 8-11. Default device configuration after power up
FEATURE
ADC3561
ADC3562
Signal Input
ADC3563
Differential
Auto-Zero
Enabled
Enabled
Clock Input
Disabled
Differential
Reference
External
Decimation
DDC bypass
Interface
1-wire
1-wire
Output Format
2-wire
2s complement
8.5.1 Configuration using PINs only
The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ
pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating. When using
a voltage divider to set the REFBUF voltage (R1 and R2 in Figure 8-51), resistor values < 5 kΩ should be used.
AVDD
R1
AVDD
REFBUF
100 k
R2
Figure 8-51. Configuration of external voltage on REFBUF pin
Table 8-12. REFBUF voltage levels control voltage reference selection
REFBUF VOLTAGE
VOLTAGE REFERENCE OPTION
CLOCKING OPTION
> 1.7 V (Default)
External reference
Differential clock input
1.2 V (1.15-1.25V)
External 1.2V input on REFBUF pin using internal gain buffer
Differential clock input
0.5 - 0.7V
Internal reference
Differential clock input
< 0.1V
Internal reference
Single ended clock input
8.5.2 Configuration using the SPI interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting
bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when
SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.
When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples
of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz
down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
8.5.2.1 Register Write
The internal registers can be programmed following these steps:
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1.
2.
3.
4.
Drive the SEN pin low
Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.
Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and
Write the 8-bit data that are latched in on the SCLK rising edges
Figure 8-52 show the timing requirements for the serial register write operation.
Register Address
R/W
SDIO
0
0
0
0
A11
A10
A9
A8
A7
A6
A5
A4
Register Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 8-52. Serial Register Write Timing Diagram
8.5.2.2 Register Read
The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address
field to 0.
3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read
4. The device launches the contents (D[7:0]) of the selected register on the SDIO pin on SCLK falling edge
5. The external controller can capture the contents on the SCLK rising edge
Register Address
R/W
SDIO
1
0
0
0
A11
A10
A9
A8
A7
A6
A5
A4
Register Data
tOZD
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tOD
SCLK
tODZ
SEN
Figure 8-53. Serial Register Read Timing Diagram
52
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8.6 Register Maps
Table 8-13. Register Map Summary
REGISTER
ADDRESS
REGISTER DATA
A[11:0]
D7
0x00
0
0x07
D6
D5
D4
0
0
OP IF MAPPER
D3
D2
0
0
0
0
OP IF EN
D1
D0
0
RESET
OP IF SEL
0x08
0
0
PDN CLKBUF
PDN
REFAMP
0
PDN A
1
PDN
GLOBAL
0x09
0
0
PDN
FCLKOUT
PDN
DCLKOUT
PDN DA1
PDN DA0
PDN DB1
PDN DB0
0x0D
0
0
0
0
MASK
CLKBUF
MASK
REFAMP
MASK BG
DIS
0
0x0E
SYNC PIN
EN
SPI SYNC
SPI SYNC EN
0
REF CTRL
0x11
0
0
SE A
0
0
DLL PDN
0
AZ EN
0x13
0
0
0
0
0
0
0
E-FUSE LD
0x14
SE CLK EN
CUSTOM PAT [7:0]
0x15
CUSTOM PAT [15:8]
0x16
0x19
REF SEL
TEST PAT B
TEST PAT A
CUSTOM PAT [17:16]
FCLK SRC
0
0
FCLK DIV
0
0
0
TOG FCLK
0x1A
0
LVDS ½
SWING
0
0
0
0
0
0
0x1B
MAPPER EN
20B EN
0
0
0
0x1E
0
0
BIT MAPPER RES
0
0x20
SCR EN
0x24
0
0
0x25
DDC MUX EN
0x26
0
0
FCLK PAT [19:16]
DDC MUX
DECIMATION
MIX GAIN A
0
0
MIX RES A
0
0
FS/4 MIX A
OP ORDER A
Q-DEL A
NCO A [7:0]
NCO A [15:8]
0x2C
NCO A [23:16]
0x2D
NCO A [31:24]
0
0
DDC EN
0
0
0
MIX PHASE
MIX GAIN B
0x2B
0
DIG BYP
REAL OUT
0x2A
0x2E
LVDS DCLK DEL
FCLK PAT [15:8]
0
0x27
LVDS DATA DEL
FCLK PAT [7:0]
0x21
0x22
0
OP ORDER B
Q-DEL B
0x31
NCO B [7:0]
0x32
NCO B [15:8]
0x33
NCO B [23:16]
0x34
NCO B [31:24]
0x39..0x60
OUTPUT BIT MAPPER CHA
0x61..0x88
OUTPUT BIT MAPPER CHB
MIX RES B
FS/4 MIX B
FS/4 MIX PH
A
0
0
FS/4 MIX PH
B
0
0
0x8F
0
0
0
0
0
0
FORMAT A
0
0x92
0
0
0
0
0
0
FORMAT B
0
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8.6.1 Detailed Register Description
Figure 8-54. Register 0x00
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RESET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-14. Register 0x00 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R/W
0
Must write 0
RESET
R/W
0
This bit resets all internal registers to the default values and self
clears to 0.
0
Figure 8-55. Register 0x07
7
6
5
4
3
0
OP IF EN
R/W-0
R/W-0
R/W-0
OP IF VAR
R/W-0
R/W-0
2
1
0
OP IF SEL
R/W-0
R/W-0
R/W-0
Table 8-15. Register 0x07 Field Descriptions
54
Bit
Field
Type
Reset
Description
7-5
OP IF MAPPER
R/W
000
Output interface mapper. This register contains the proper
output interface bit mapping for the different interfaces. The
interface bit mapping is internally loaded from e-fuses and also
requires a fuse load command to go into effect (0x13, D0).
Register 0x07 along with the E-Fuse Load (0x13, D0) needs to
be loaded first in the programming sequence since the E-Fuse
load resets the SPI writes.
After initial reset the default output interface variant is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
001: 2-wire, 18 and 14-bit
010: 2-wire, 16-bit
011: 1-wire
100: 0.5-wire
others: not used
4
0
R/W
0
Must write 0
3
OP IF EN
R/W
0
Enables changing the default output interface mode (D2-D0).
2-0
OP IF SEL
R/W
000
Selection of the output interface mode. OP IF EN (D3) needs to
be enabled also.
After initial reset the default output interface is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
011: 2-wire
100: 1-wire
101: 0.5-wire
others: not used
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Figure 8-56. Register 0x08
7
6
5
4
3
2
1
0
0
0
PDN CLKBUF
PDN REFAMP
0
PDN A
1
PDN GLOBAL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-16. Register 0x08 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
PDN CLKBUF
R/W
0
Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4
PDN REFAMP
R/W
0
Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
3
0
R/W
0
Must write 0
2
PDN A
R/W
0
Powers down ADC channel A
0: ADC channel A enabled
1: ADC channel A powered down
1
1
R/W
1
Must write 1
0
PDN GLOBAL
R/W
0
Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register
0x0D) determines which internal blocks are powered down.
Figure 8-57. Register 0x09
7
6
0
0
R/W-0
R/W-0
5
4
PDN FCLKOUT PDN DCLKOUT
R/W-0
R/W-0
3
2
1
0
PDN DA0
PDN DA1
PDN DB0
PDN DB1
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-17. Register 0x09 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
PDN FCLKOUT
R/W
0
Powers down frame clock (FCLK) LVDS output buffer
0: FCLK output buffer enabled
1: FCLK output buffer powered down
4
PDN DCLKOUT
R/W
0
Powers down DCLK LVDS output buffer
0: DCLK output buffer enabled
1: DCLK output buffer powered down
3
PDN DA1
R/W
1
Powers down LVDS output buffer for channel A, lane 1.
Powered down automatically in 1-wire and 1/2-wire mode.
0: DA1 LVDS output buffer enabled
1: DA1 LVDS output buffer powered down
2
PDN DA0
R/W
1
Powers down LVDS output buffer for channel A, lane 0.
0: DA0 LVDS output buffer enabled
1: DA0 LVDS output buffer powered down.
1
PDN DB1
R/W
0
Powers down LVDS output buffer for channel B, lane 1.
Powered down by default. Powered down automatically in 1-wire
and 1/2-wire mode.
0: DB1 LVDS output buffer enabled
1: DB1 LVDS output buffer powered down
0
PDN DB0
R/W
0
Powers down LVDS output buffer for channel B, lane 0.
Powered down by default. Powered down automatically in 1/2wire mode.
0: DB0 LVDS output buffer enabled
1: DB0 LVDS output buffer powered down
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Figure 8-58. Register 0x0D (PDN GLOBAL MASK)
7
6
5
4
0
0
0
0
3
R/W-0
R/W-0
R/W-0
R/W-0
2
1
MASK CLKBUF MASK REFAMP MASK BG DIS
R/W-0
R/W-0
R/W-0
0
0
R/W-0
Table 8-18. Register 0x0D Field Descriptions
56
Bit
Field
Type
Reset
Description
7-4
0
R/W
0
Must write 0
3
MASK CLKBUF
R/W
0
Global power down mask control for sampling clock input buffer.
0: Clock buffer will get powered down when global power down
is exercised.
1: Clock buffer will NOT get powered down when global power
down is exercised.
2
MASK REFAMP
R/W
0
Global power down mask control for reference amplifier.
0: Reference amplifier will get powered down when global power
down is exercised.
1: Reference amplifier will NOT get powered down when global
power down is exercised.
1
MASK BG DIS
R/W
0
Global power down mask control for internal 1.2V bandgap
voltage reference. Setting this bit reduces power consumption
in global power down mode but increases the wake up time. See
the power down option overview.
0: Internal 1.2V bandgap voltage reference will NOT get
powered down when global power down is exercised.
1: Internal 1.2V bandgap voltage reference will get powered
down when global power down is exercised.
0
0
R/W
0
Must write 0
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Figure 8-59. Register 0x0E
7
6
5
4
3
SYNC PIN EN
SPI SYNC
SPI SYNC EN
0
REF CTL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
2
1
REF SEL
R/W-0
0
SE CLK EN
R/W-0
R/W-0
Table 8-19. Register 0x0E Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC PIN EN
R/W
0
This bit controls the functionality of the SYNC/PDN pin.
0: SYNC/PDN pin exercises global power down mode when pin
is pulled high.
1: SYNC/PDN pin issues the SYNC command when pin is
pulled high.
6
SPI SYNC
R/W
0
Toggling this bit issues the SYNC command using the SPI
register write. SYNC using SPI must be enabled as well (D5).
This bit doesn't self reset to 0.
0: Normal operation
1: SYNC command issued.
5
SPI SYNC EN
R/W
0
This bit enables synchronization using SPI instead of the
SYNC/PDN pin.
0: Synchronization using SPI register bit disabled.
1: Synchronization using SPI register bit enabled.
4
0
R/W
0
Must write 0
3
REF CTL
R/W
0
This bit determines if the REFBUF pin controls the voltage
reference selection or the SPI register (D2-D1).
0: The REFBUF pin selects the voltage reference option.
1: Voltage reference is selected using SPI (D2-D1) and single
ended clock using D0.
2-1
REF SEL
R/W
00
Selects of the voltage reference option. REF CTRL (D3) must be
set to 1.
00: Internal reference
01: External voltage reference (1.2V) using internal reference
buffer (REFBUF)
10: External voltage reference
11: not used
SE CLK EN
R/W
0
Selects single ended clock input and powers down the
differential sampling clock input buffer. REF CRTL (D3) must be
set to 1.
0: Differential clock input
1: Single ended clock input
0
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Figure 8-60. Register 0x11
7
6
5
4
3
2
1
0
0
0
SE A
0
0
DLL PDN
0
AZ EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-20. Register 0x11 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
SE A
R/W
0
This bit enables single ended analog input, channel A. In this
mode the SNR reduces by 3-dB.
0: Differential input
1: Single ended input
0
R/W
0
Must write 0
2
DLL PDN
R/W
0
This register applies ONLY to the ADC3563. It powers down the
internal DLL, which is used to adjust the sampling time. This
register must only be enabled when operating at sampling rates
below 40 MSPS. When DLL PDN bit is enabled the sampling
time is directly dependent on sampling clock duty cycle (with a
50/50 duty the sampling time is TS/2).
0: Sampling time is TS/ 4
1: Sampling time is TS/2 (only for sampling rates below 40
MSPS).
1
0
R/W
0
Must write 0
0
AZ EN
R/W
0
This bit enables the internal auto-zero circuitry. It is enabled by
default for the ADC3561/62 and disabled for the ADC3563.
ADC3561/62:
0: Auto-zero enabled
1: Auto-zero disabled
ADC3563:
0: Auto-zero disabled
1: Auto-zero enabled
5
4-3
58
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Figure 8-61. Register 0x13
7
6
5
4
3
2
0
0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
1
0
E-FUSE LD
R/W-0
R/W-0
Table 8-21. Register 0x13 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R/W
0
Must write 0
E-FUSE LD
R/W
0
This register bit loads the internal bit mapping for different
interfaces. After setting the interface in register 0x07, this EFUSE LD bit needs to be set to 1 and reset to 0 for loading to go
into effect. Register 0x07 along with the E-Fuse Load (0x13, D0)
needs to be loaded first in the programming sequence since the
E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
0
Figure 8-62. Register 0x14/15/16
7
6
5
4
3
2
1
R/W-0
R/W-0
0
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
TEST PAT B
R/W-0
R/W-0
TEST PAT A
R/W-0
R/W-0
R/W-0
CUSTOM PAT [17:16]
R/W-0
Table 8-22. Register 0x14/15/16 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOM PAT [17:0]
R/W
00000000
This register is used for two purposes:
•
It sets the constant custom pattern starting from MSB
•
It sets the RAMP pattern increment step size.
00001: Ramp pattern for 18-bit ADC
00100: Ramp pattern for 16-bit ADC
10000: Ramp pattern for 14-bit ADC
7-5
TEST PAT B
R/W
000
Enables test pattern output mode for channel B (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
4-2
TEST PAT A
R/W
000
Enables test pattern output mode for channel A (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
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Figure 8-63. Register 0x19
7
6
5
4
3
2
1
0
FCLK SRC
0
0
FCLK DIV
0
0
0
TOG FCLK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-23. Register 0x19 Field Descriptions
Bit
7
6-5
4
3-1
0
Field
Type
Reset
Description
FCLK SRC
R/W
0
User has to select if FCLK signal comes from ADC or from DDC
block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC
bypass, real decimation mode and 1/2-w complex decimation
mode.
1: FCLK generated from DDC block. In complex decimation
mode only this bit needs to be set for 2-w and 1-w output
interface mode but NOT for 1/2-w mode.
0
R/W
0
Must write 0
FCLK DIV
R/W
0
This bit needs to be set to 1 for 2-w output mode in bypass
mode only (non decimation).
0: All output interface modes except 2-w bypass mode.
1: 2-w output interface mode.
0
R/W
0
Must write 0
TOG FCLK
R/W
0
This bit adjusts the FCLK signal appropriately for 1/2-wire mode
where FCLK is stretched to cover channel A and channel B.
This bit ONLY needs to be set in 1/2-wire mode with complex
decimation mode.
0: all other modes.
1: FCLK for 1/2-wire complex decimation mode.
Table 8-24. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATION
Decimation Bypass/ Real Decimation
Complex Decimation
60
SERIAL INTERFACE
FCLK SRC
FCLK DIV
TOG FCLK
2-wire
0
1
0
1-wire
0
0
0
1/2-wire
0
0
0
2-wire
1
0
0
1-wire
1
0
0
1/2-wire
0
0
1
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Figure 8-64. Register 0x1A
7
6
5
4
3
2
1
0
0
LVDS ½
SWING
0
0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-25. Register 0x1A Field Descriptions
Bit
Field
Type
Reset
Description
7
0
R/W
0
Must write 0
6
LVDS ½ SWING
R/W
0
This bit reduces the LVDS output current from 3.5 mA to 1.75
mA which reduces power consumption.
0: Normal output current 3.5 mA
1: Reduced LVDS output current 1.75 mA
0
R/W
0
Must write 0
5-0
Figure 8-65. Register 0x1B
7
6
MAPPER EN
20B EN
R/W-0
R/W-0
5
4
3
2
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
BIT MAPPER RES
R/W-0
R/W-0
1
0
Table 8-26. Register 0x1B Field Descriptions
Bit
Field
Type
Reset
Description
7
MAPPER EN
R/W
0
This bit enables changing the resolution of the output (including
output serialization factor) in bypass mode only. This bit doesn't
need to be set for 20-bit resolution output.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
6
20B EN
R/W
0
This bit enables 20-bit output resolution which can be useful for
very high decimation settings so that quantization noise doesn't
impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3
BIT MAPPER RES
R/W
001
Sets the output resolution using the bit mapper. MAPPER EN bit
(D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2-0
0
R/W
0
Must write 0
Table 8-27. Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/DECIMATION
OUTPUT RESOLUTION
MAPPER EN (D7)
Decimation Bypass
Resolution Change
1
Real Decimation
Complex Decimation
Resolution Change (default 18-bit)
0
0
BIT MAPPER RES (D5-D3)
000: 18-bit
001: 16-bit
010: 14-bit
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Figure 8-66. Register 0x1E
7
6
5
4
0
0
0
0
3
R/W-0
R/W-0
R/W-0
R/W-0
2
1
LVDS DATA DEL
R/W-0
0
LVDS DCLK DEL
R/W-0
R/W-0
R/W-0
Table 8-28. Register 0x1E Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
R/W
0
Must write 0
3-2
LVDS DATA DEL
R/W
00
These bits adjust the output timing of the SLVDS output data.
00: no delay
01: Data advanced by 50 ps
10: Data delayed by 50 ps
11: Data delayed by 100 ps
1-0
LVDS DCLK DEL
R/W
00
These bits adjust the output timing of the SLVDS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
Figure 8-67. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
SCR EN
0
0
R/W-0
R/W-0
R/W-0
R/W-0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-29. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 8-30 shows the proper
FCLK pattern values for 1-wire and 1/2-wire in real/complex
decimation.
SCR EN
R/W
0
This bit enables the output data scrambler. Digital bypass (0x24,
D2) needs to be set as well.
0: Output scrambling disabled
1: Output scrambling enabled
6
Table 8-30. FCLK Pattern for different resolution based on interface
DECIMATION
OUTPUT RESOLUTION
REAL DECIMATION
1-WIRE
14-bit
0xFE000
16-bit
0xFF000
18-bit
0xFF800
20-bit
14-bit
COMPLEX
DECIMATION
2-WIRE
Use Default
16-bit
18-bit
1/2-WIRE
Use Default
0xFFC00
0xFFFFF
0xFFFFF
20-bit
62
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Figure 8-68. Register 0x24
7
6
5
0
0
0
R/W-0
R/W-0
R/W-0
4
3
DDC MUX
R/W-0
R/W-0
2
1
0
DIG BYP
DDC EN
0
R/W-0
R/W-0
R/W-0
Table 8-31. Register 0x24 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
R/W
0
Must write 0
4-3
DDC MUX
R/W
0
Configures DDC MUX in front of the decimation filter.
00: ADC channel A connected to DDC A
01: ADC channel A connected to DDC A and DDC B.
others: not used
2
DIG BYP
R/W
0
This bit needs to be set to enable digital features block which
includes decimation and scrambling.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1
DDC EN
R/W
0
Enables internal decimation filter for both channels
0: DDC disabled.
1: DDC enabled.
0
0
R/W
0
Must write 0
To output
interface
DDC
N
DECIMATION
DIG BYP
DDC
N
DDC MUX
To output
interface
Figure 8-69. Register control for digital features
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Figure 8-70. Register 0x25
7
6
DDC MUX EN
R/W-0
5
4
DECIMATION
R/W-0
R/W-0
R/W-0
3
2
1
0
REAL OUT
0
0
MIX PHASE
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-32. Register 0x25 Field Descriptions
Bit
Field
Type
Reset
Description
7
DDC MUX EN
R/W
0
Enables the digital mux between ADCs and decimation filters.
This bit is required for DDC mux settings in register 0x24 (D4,
D3) to go into effect.
0: DDC mux disabled
1: DDC mux enabled
6-4
DECIMATION
R/W
000
Complex decimation setting. This applies to both channels.
000: Bypass mode (no decimation)
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
100: Decimation by 16
101: Decimation by 32
others: not used
REAL OUT
R/W
0
This bit selects real output decimation. This mode applies to
both channels. In this mode, the decimation filter is a low pass
filter and no complex mixing is performed to reduce power
consumption. For maximum power savings the NCO in this case
should be set to 0.
0: Complex decimation
1: Real decimation
0
R/W
0
Must write 0
MIX PHASE
R/W
0
This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
3
2-1
0
Figure 8-71. Register 0x26
7
6
MIX GAIN A
R/W-0
R/W-0
5
4
3
MIX RES A
FS/4 MIX A
R/W-0
R/W-0
2
MIX GAIN B
R/W-0
R/W-0
1
0
MIX RES B
FS/4 MIX B
R/W-0
R/W-0
Table 8-33. Register 0x26 Field Descriptions
64
Bit
Field
Type
Reset
Description
7-6
MIX GAIN A
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel A.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
5
MIX RES A
R/W
0
Toggling this bit resets the NCO phase of channel A and loads
the new NCO frequency. This bit does not self reset.
4
FS/4 MIX A
R/W
0
Enables FS/4 mixing for DDC A (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
3-2
MIX GAIN B
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel B.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
1
MIX RES B
R/W
0
Toggling this bit resets the NCO phase of channel B and loads
the new NCO frequency. This bit does not self reset.
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Table 8-33. Register 0x26 Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
FS/4 MIX B
R/W
0
Enables FS/4 mixing for DDC B (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
Figure 8-72. Register 0x27
7
6
5
4
3
2
1
0
0
0
0
OP ORDER A
Q-DEL A
FS/4 MIX PH A
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-34. Register 0x27 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
R/W
0
Must write 0
4
OP ORDER A
R/W
0
Swaps the I and Q output order for channel A
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
Q-DEL A
R/W
0
This delays the Q-sample output of channel A by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2
FS/4 MIX PH A
R/W
0
Inverts the mixer phase for channel A when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
0
R/W
0
Must write 0
1-0
Figure 8-73. Register 0x2A/B/C/D
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
R/W-0
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-35. Register 0x2A/2B/2C/2D Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO A [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel A. The
NCO value is fNCO× 232/FS
In real decimation mode these registers are automatically set to
0.
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Figure 8-74. Register 0x2E
7
6
5
4
3
2
1
0
0
0
0
OP ORDER B
Q-DEL B
FS/4 MIX PH B
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-36. Register 0x2E Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
R/W
0
Must write 0
4
OP ORDER B
R/W
0
Swaps the I and Q output order for channel B
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
Q-DEL B
R/W
0
This delays the Q-sample output of channel B by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2
FS/4 MIX PH B
R/W
0
Inverts the mixer phase for channel B when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
0
R/W
0
Must write 0
1-0
Figure 8-75. Register 0x31/32/33/34
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
R/W-0
NCO B [7:0]
NCO B [15:8]
NCO B [23:16]
NCO B [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-37. Register 0x31/32/33/34 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO B [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel B. The
NCO value is fNCO× 232/FS
In real decimation mode these registers are automatically set to
0.
Figure 8-76. Register 0x39..0x60
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
OUTPUT BIT MAPPER CHA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-38. Register 0x39..0x60 Field Descriptions
66
Bit
Field
Type
Reset
Description
7-0
OUTPUT BIT MAPPER CHA
R/W
0
These registers are used to reorder the output data bus. See the
Section 8.3.5.2 on how to program it.
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Figure 8-77. Register 0x61..0x88
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
OUTPUT BIT MAPPER CHB
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-39. Register 0x61..0x88 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OUTPUT BIT MAPPER CHB
R/W
0
These registers are used to reorder the output data bus. See the
Section 8.3.5.2 on how to program it.
Figure 8-78. Register 0x8F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FORMAT A
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-40. Register 0x8F Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
1
FORMAT A
R/W
0
This bit sets the output data format for channel A. Digital bypass
register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
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Figure 8-79. Register 0x92
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FORMAT B
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-41. Register 0x92 Field Descriptions
68
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
1
FORMAT B
R/W
0
This bit sets the output data format for channel B. Digital bypass
register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Typical Application
A spectrum analyzer is a typical frequency domain application for the ADC356x and its front end circuitry is
very similar to several other systems such as software defined radio (SDR), sonar, radar or communications.
Some applications require frequency coverage including DC or near DC (such as. sonar), so it is included in this
example.
0.6V
10 uF
VREF
10 k
REFBUF
Glitch Filter
1.2V REF
NCO
33
Low Pass Filter
100 pF
N
10
180nH
AMP
AIN
33
ADC
DCLKIN
NCO
10
DCLK
N
180nH
Dig I/F
VCM
FCLK
FPGA
DA0/1
0.95V
DB0/1
CVCM
Device Clock
CLK
SCLK
SEN
SDIO
RESET
PDN/
SYNC
Control
Figure 9-1. Typical configuration for a spectrum analyzer with DC support
9.1.1 Design Requirements
Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in
the 1st Nyquist zone to under sampling in higher Nyquist zones. If very low input frequency is supported then the
input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is
not needed, then AC coupling and use of a balun may be more suitable.
The internal reference is used since DC precision is not needed. However the ADC AC performance is highly
dependent on the quality of the external clock source. If in-band interferes can be present, then the ADC SFDR
performance will be a key care about as well. A higher ADC sampling rate is desirable in order to relax the
external anti-aliasing filter – an internal decimation filter can be used to reduce the digital output rate afterwards.
Table 9-1. Design key care-abouts
FEATURE
DESCRIPTION
Signal Bandwidth
DC to 20 MHz
Input Driver
Single ended to differential signal conversion and DC coupling
Clock Source
External clock with low jitter
When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into
consideration. For example, the ADC356x input full-scale is 3.2 Vpp. When factoring in ~ 1 dB for insertion loss
of the filter, then the amplifier needs to deliver close to 3.6 Vpp. The amplifier distortion performance will degrade
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with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able
to deliver the full swing. The ADC356x provides an output common mode voltage of 0.95 V and the THS4541
for example can only swing within 250 mV of its negative supply. A unipolar 3.3 V amplifier power supply will
thus limit the maximum voltage swing to ~ 2.8 Vpp. Hence if a larger output swing is required (factoring in filter
insertion loss) then a negative supply for the amplifier is needed in order to eliminate that limitation. Additionally
input voltage protection diodes may be needed to protect the ADC from over-voltage events.
Table 9-2. Output voltage swing of THS4541 vs power supply
DEVICE
MIN OUTPUT VOLTAGE
MAX SWING WITH 3.3 V/ 0 V SUPPLY
MAX SWING WITH 3.3 V/ -1 V SUPPLY
THS4541
VS- + 250 mV
2.8 Vpp
6.8 Vpp
9.1.2 Detailed Design Procedure
9.1.2.1 Input Signal Path
Depending on desired input signal frequency range the THS4551 and THS4541 provide very good low power
options to drive the ADC inputs. Table 9-3 provides a comparison between the THS4551 and THS4541 and the
power consumption vs usable frequency trade off.
Table 9-3. Fully Differential Amplifier Options
DEVICE
CURRENT (IQ) PER CHANNEL
USABLE FREQUENCY RANGE
THS4561
0.8 mA
< 3 MHz
THS4551
1.4 mA
< 10 MHz
THS4541
10 mA
< 70 MHz
The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the
low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between
the low pass filter and the ADC input the sampling glitch filter needs to added as well as shown in Sampling
Glitch Filter Design. In this example, the DC - 30 MHz glitch filter is selected.
9.1.2.2 Sampling Clock
Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to
performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall
times (i.e. square wave vs sine wave). Table 9-4 provides an overview of the estimated SNR performance of
the ADC356x based on different amounts of jitter of the external clock source. The SNR is estimated based on
ADC356x thermal noise of 84.5dBFS and input signal at -1dBFS.
Table 9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter
INPUT FREQUENCY
TJ,EXT = 100 fs
TJ,EXT = 250 fs
TJ,EXT = 500 fs
TJ,EXT = 1 ps
5 MHz
82.0
81.9
81.8
81.5
10 MHz
81.9
81.8
81.4
80.2
20 MHz
81.6
81.2
80.1
77.2
Termination of the clock input should be considered for long clock traces.
9.1.2.3 Voltage Reference
The ADC356x is configured to internal reference operation by applying 0.6 V to the REFBUF pin.
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9.1.3 Application Curves
The following FFT plots show the performance of THS4541 driving the ADC3563 operated at 65 MSPS with a
full-scale input at -1 dBFS and input frequencies of 5, 10 and 20 MHz.
SNR = 81.0 dBFS, SFDR = 88 dBc, Non HD23 = 95 dBFS
SNR = 80.4 dBFS, SFDR = 91 dBc, Non HD23 = 83 dBFS
Figure 9-2. Single Tone FFT at FIN = 5 MHz
Figure 9-3. Single Tone FFT at FIN = 10 MHz
SNR = 77.2 dBFS, SFDR = 76 dBc, Non HD23 = 93 dBFS
Figure 9-4. Single Tone FFT at FIN = 20 MHz
AIN = -10 dBFS, SNR = 81.0 dBFS, SFDR = 87 dBc,
Non HD23 = 90 dBFS
Figure 9-5. Single Tone FFT at FIN = 20 MHz
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9.2 Initialization Set Up
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in Figure 9-6.
1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap
reference will power up and settle out in ~ 2ms.
2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses
and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock
cycles.
4. Begin programming using SPI interface.
t2
AVDD
IOVDD
t1
REFBUF
Ext VREF
CLK
t4
t3
RESET
SEN
Figure 9-6. Initialization of serial registers after power up
Table 9-5. Power-up timing
MIN
t1
Power-on delay: delay from power up to logic level of REFBUF pin
t2
Delay from REFBUF pin logic level to RESET rising edge
t3
RESET pulse width
t4
Delay from RESET disable to SEN active
TYP
MAX
UNIT
2
ms
100
ns
1
us
~ 200000
clock cycles
9.2.1 Register Initialization During Operation
If required, the serial interface registers can be cleared and reset to default settings during operation either:
•
•
through a hardware reset or
by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be
programmed.
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9.3 Power Supply Recommendations
The ADC356x requires two different power-supplies. The AVDD rail provides power for the internal analog
circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like
decimation filter or output interface mapper. Power sequencing is not required.
The AVDD power supply must be low noise in order to achieve data sheet performance. In applications
operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. The ADC
is designed for very good PSRR which aides with the power supply filter design.
55
PSRR (dB)
50
45
40
35
30
0.05
0.1
1
10
Frequency of Signal on AVDD (MHz)
100
D42_
Figure 9-7. Power supply rejection ratio (PSRR) vs frequency
There are two recommended power-supply architectures:
1. 1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a
low noise LDO to provide switching noise reduction and improved voltage accuracy.
2. 2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent
degraded ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements
needed: see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include the TPS62821, and similar devices.
Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar
devices.
For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with
the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH®
and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure 9-8
and Figure 9-9 illustrate the two approaches.
AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling
into the analog signal chain.
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2.1V
DC/DC
Regulator
5V-12V
FB
FB
1.8V
AVDD
LDO
10uF 10uF 0.1uF
47uF
47uF
GND
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
FB = Ferrite bead filter
GND
Figure 9-8. Example: LDO Linear Regulator Approach
5V-12V
1.8V
DC/DC
Regulator
EMI FILTER
FB
AVDD
10uF 10uF 10uF
10uF 10uF 0.1uF
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
GND
Ripple filter notch frequency to match switching frequency of the DC/DC regulator
FB = Ferrite bead filter
Figure 9-9. Example Switcher-Only Approach
9.4 Layout
9.4.1 Layout Guidelines
There are several critical signals which require specific care during board design:
1. Analog input and clock signals
• Traces should be as short as possible and vias should be avoided where possible to minimize impedance
discontinuities.
• Traces should be routed using loosely coupled 100-Ω differential traces.
• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2
degradation.
2. Digital output interface
• Traces should be routed using tightly coupled 100-Ω differential traces.
3. Voltage reference
• The bypass capacitor should be placed as close to the device pins as possible and connected between
VREF and REFGND – on top layer avoiding vias.
• Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be
recommended and should also be placed as close to pins as possible on top layer.
4. Power and ground connections
• Provide low resistance connection paths to all power and ground pins.
• Use power and ground planes instead of traces.
• Avoid narrow, isolated paths which increase the connection resistance.
• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power
plane.
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9.4.2 Layout Example
The following screen shot shows the top layer of the ADC356x/368x EVM.
•
•
•
Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
SLVDS output interface lanes are routed differential and length matched
Bypass caps are close to the VREF pin on the top layer avoiding vias.
Bypass caps on VREF close
to the pins and no vias
SLVDS routed tightly
coupled and length matched
Clock routing
without vias
Analog inputs on
top layer (no vias)
Figure 9-10. Layout example: top layer of ADC356x/368x EVM
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10 Device and Documentation Support
10.1 Device Support
10.2 Documentation Support
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADC3561IRSBR
ACTIVE
WQFN
RSB
40
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3561
Samples
ADC3561IRSBT
ACTIVE
WQFN
RSB
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3561
Samples
ADC3562IRSBR
ACTIVE
WQFN
RSB
40
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3562
Samples
ADC3562IRSBT
ACTIVE
WQFN
RSB
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3562
Samples
ADC3563IRSBR
ACTIVE
WQFN
RSB
40
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3563
Samples
ADC3563IRSBT
ACTIVE
WQFN
RSB
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3563
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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