ADCS7477AIMF/NOPB

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 ADCS747x 1-MSPS, 12-Bit, 10-Bit, and 8-Bit A/D Converters 1 Features 3 Description • • • • • The ADCS7476, ADCS7477, and ADCS7478 devices are low power, monolithic CMOS 12-, 10-, and 8-bit analog-to-digital converters that operate at 1 MSPS. The ADCS747x devices are a drop-in replacement for Analog Device's AD747x. Each device is based on a successive approximation register architecture with internal track-and-hold. The serial interface is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces. 1 • Variable Power Management Packaged in 6-Pin SOT-23 Power Supply Used as Reference Single 2.7-V to 5.25-V Supply Operation Compatible With SPI™, QSPI™, MICROWIRE™, and DSP Key Specifications – Resolution With No Missing Codes (12-Bit, 10Bit, and 8-Bit) – Conversion Rate: 1 MSPS – DNL: 0.5, –0.3 LSB (Typical) – INL: ±0.4 LSB (Typical) – Power Consumption: – 3-V Supply: 2 mW (Typical) – 5-V Supply: 10 mW (Typical) 2 Applications • • • • • • Automotive Navigation FA or ATM Equipment Portable Systems Medical Instruments Mobile Communications Instrumentation and Control Systems The ADCS747x uses the supply voltage as a reference, enabling the device to operate with a fullscale input range of 0 to VDD. The conversion rate is determined from the serial clock (SCLK) speed. These converters offer a shutdown mode, which can be used to trade throughput for power consumption. The ADCS747x is operated with a single supply that can range from 2.7 V to 5.25 V. Normal power consumption during continuous conversion, using a 3-V or 5-V supply, is 2 mW or 10 mW respectively. The power-down feature, which is enabled by a chip select (CS) pin, reduces the power consumption to under 5 µW using a 5-V supply. All three converters are available in a 6-pin SOT-23 package, which provides an extremely small footprint for applications where space is a critical consideration. These products are designed for operation over the automotive and extended industrial temperature range of −40°C to 125°C. Device Information(1) PART NUMBER ADCS7476 ADCS7477 ADCS7478 PACKAGE SOT-23 (6) BODY SIZE (NOM) 1.60 mm × 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram VIN ADCS7476 ADCS7477 ACDS7478 T/H SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information ................................................. 4 Electrical Characteristics – ADCS7476..................... 5 Electrical Characteristics – ADCS7477..................... 6 Electrical Characteristics – ADCS7478..................... 8 Timing Requirements ................................................ 9 Typical Characteristics ............................................ 12 Detailed Description ............................................ 16 7.1 Overview ................................................................. 16 7.2 Functional Block Diagram ....................................... 16 7.3 Feature Description................................................. 16 7.4 Device Functional Modes........................................ 17 8 Application and Implementation ........................ 21 8.1 Application Information............................................ 21 8.2 Typical Application .................................................. 22 9 Power Supply Recommendations...................... 23 9.1 Power Supply Noise............................................... 23 9.2 Digital Output Effect Upon Noise ........................... 23 9.3 Power Management ................................................ 23 10 Layout................................................................... 24 10.1 Layout Guidelines ................................................. 24 10.2 Layout Example ................................................... 25 11 Device and Documentation Support ................. 26 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 27 27 27 27 12 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2013) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Moved VDD from the Electrical Characteristics tables to the Recommended Operating Conditions table ............................. 5 Changes from Revision E (March 2013) to Revision F • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 5 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View VDD 1 6 CS GND 2 5 SDATA VIN 3 4 SCLK Not to scale Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 VDD P Positive supply pin. These pins must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 0.1-µF and 1-µF monolithic capacitors placed within 1 cm of the power pin. ADCS747x uses this power supply as a reference, so it must be thoroughly bypassed. 2 GND G The ground return for the supply. 3 VIN I Analog input. This signal can range from 0 V to VDD. 4 SCLK I Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with ensured performance at 20 MHz. This clock directly controls the conversion and readout processes. 5 SDATA O Digital data output. The output words are clocked out of this pin by the SCLK pin. 6 CS I Chip select. A conversion process begins on the falling edge of CS. (1) G = Ground, I = Input, O = Output, P = Power Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 3 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Supply voltage, VDD –0.3 6.5 V Voltage on any analog pin to GND –0.3 VDD + 0.3 V Voltage on any digital pin to GND –0.3 6.5 V Input current at any pin (except power supply pins) ±10 mA Soldering temperature, infrared (10 sec) 215 °C Operating temperature, TA 150 °C 150 °C Storage temperature, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±3500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±200 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VDD MIN MAX UNIT 2.7 5.25 V Digital input pins voltage (independent of supply voltage) 2.7 5.25 V Operating temperature –40 125 °C Supply voltage TA 6.4 Thermal Information ADCS7476, ADCS7477, ADCS7478 THERMAL METRIC (1) UNIT DBV (SOT-23) 6 PINS RθJA Junction-to-ambient thermal resistance 184.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 151.2 °C/W RθJB Junction-to-board thermal resistance 29.7 °C/W ψJT Junction-to-top characterization parameter 29.8 °C/W ψJB Junction-to-board characterization parameter 29.1 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 6.5 Electrical Characteristics – ADCS7476 TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CONVERTER CHARACTERISTICS Resolution with no missing codes INL Integral non-linearity VDD = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C VDD = 2.7 V to 3.6 V 12 TA = 25°C ±0.4 –40°C ≤ TA ≤ 85°C ±1 VDD = 2.7 V to 3.6 V, TA = 125°C DNL Differential non-linearity VDD = 2.7 V to 3.6 V –1.1 TA = 25°C –0.3 –40°C ≤ TA ≤ 85°C –0.9 1 0.5 1 VDD = 2.7 V to 3.6 V, TA = 125°C VOFF Offset error VDD = 2.7 V to 3.6 V GE Gain error VDD = 2.7 V to 3.6 V ±1 TA = 25°C ±0.1 −40°C ≤ TA ≤ 125°C ±1.2 TA = 25°C ±0.2 –40°C ≤ TA ≤ 125°C ±1.2 Bits LSB LSB LSB LSB LSB LSB DYNAMIC CONVERTER CHARACTERISTICS TA = 25°C 72 SINAD Signal-to-noise plus distortion ratio fIN = 100 kHz SNR Signal-to-noise ratio THD Total harmonic distortion fIN = 100 kHz –80 dB SFDR Spurious-free dynamic range fIN = 100 kHz 82 dB Intermodulation distortion, second order terms fa = 103.5 kHz, fb = 113.5 kHz –78 dB Intermodulation distortion, third order terms fa = 103.5 kHz, fb = 113.5 kHz –78 dB 5-V supply 11 MHz 3-V supply 8 MHz VDD = 4.75 V to 5.25 V, SCLK On or Off 2 mA VDD = 2.7 V to 3.6 V, SCLK On or Off 1 mA VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS TA = 25°C 2 VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS TA = 25°C fIN = 100 kHz –40°C ≤ TA ≤ 125°C TA = 25°C 72.5 –40°C ≤ TA ≤ 85°C FPBW –3-dB full power bandwidth dB 70.8 fIN = 100 kHz, TA = 125°C IMD dB 70 70.6 dB POWER SUPPLY CHARACTERISTICS Normal mode (static) IDD Normal mode (operational) Shutdown mode Power consumption, normal mode (operational) PD Power consumption, shutdown mode –40°C ≤ TA ≤ 85°C 3.5 0.6 –40°C ≤ TA ≤ 85°C 1.6 VDD = 5 V, SCLK Off VDD = 5 V, SCLK On VDD = 5 V, fSAMPLE = 1 MSPS TA = 25°C VDD = 3 V, fSAMPLE = 1 MSPS TA = 25°C mA mA 0.5 µA 60 µA 10 –40°C ≤ TA ≤ 85°C 17.5 2 –40°C ≤ TA ≤ 85°C 4.8 mW mW VDD = 5 V, SCLK Off 2.5 µW VDD = 3 V, SCLK Off 1.5 µW ANALOG INPUT CHARACTERISTICS VIN Input range IDCL DC leakage current CINA Analog input capacitance 0 to VDD –40°C ≤ TA ≤ 85°C V ±1 30 µA pF DIGITAL INPUT CHARACTERISTICS (1) Data sheet minimum and maximum specification limits are ensured by design, test, or statistical analysis. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 5 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Electrical Characteristics – ADCS7476 (continued) TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted)(1) PARAMETER VIH TEST CONDITIONS –40°C ≤ TA ≤ 85°C Input high voltage VIL Input low voltage IIN Input current CIND Digital input capacitance MIN TYP MAX 2.4 UNIT V VDD = 5 V, –40°C ≤ TA ≤ 85°C 0.8 V VDD = 3 V, –40°C ≤ TA ≤ 85°C 0.4 V ±1 µA VIN = 0 V or VDD TA = 25°C ±10 nA –40°C ≤ TA ≤ 85°C TA = 25°C 2 –40°C ≤ TA ≤ 85°C 4 pF DIGITAL OUTPUT CHARACTERISTICS VOH Output high voltage ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C VOL Output low voltage ISINK = 200 µA, –40°C ≤ TA ≤ 85°C 0.4 V IOL TRI-STATE leakage current –40°C ≤ TA ≤ 85°C ±10 µA COUT TRI-STATE output capacitance VDD – 0.2 TA = 25°C V 2 –40°C ≤ TA ≤ 85°C 4 Output coding pF Straight (natural) binary AC ELECTRICAL CHARACTERISTICS fSCLK Clock frequency –40°C ≤ TA ≤ 125°C DC SCLK duty cycle –40°C ≤ TA ≤ 85°C tTH Track or hold acquisition time –40°C ≤ TA ≤ 85°C 400 fRATE Throughput rate –40°C ≤ TA ≤ 85°C 1 tAD Aperture delay 3 ns tAJ Aperture jitter 30 ps 20 40% MHz 60% ns MSPS 6.6 Electrical Characteristics – ADCS7477 TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CONVERTER CHARACTERISTICS Resolution with no missing codes INL Integral non-linearity DNL Differential non-linearity VOFF Offset error GE Gain error –40°C ≤ TA ≤ 85°C 10 TA = 25°C ±0.2 –40°C ≤ TA ≤ 85°C ±0.7 TA = 25°C –0.2 0.3 T–40°C ≤ TA ≤ 85°C ±0.7 ±0.7 TA = 25°C ±0.1 –40°C ≤ TA ≤ 85°C ±0.7 TA = 25°C ±0.2 –40°C ≤ TA ≤ 85°C ±1 Bits LSB LSB LSB LSB DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-noise plus distortion ratio fIN = 100 kHz SNR Signal-to-noise ratio Total harmonic distortion fIN = 100 kHz SFDR Spurious-free dynamic range fIN = 100 kHz 6 61.7 –40°C ≤ TA ≤ 85°C dBFS 61 fIN = 100 kHz THD (1) TA = 25°C 62 TA = 25°C dB –77 –40°C ≤ TA ≤ 85°C –73 TA = 25°C 78 –40°C ≤ TA ≤ 85°C 74 dB dB Data sheet minimum and maximum specification limits are ensured by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Electrical Characteristics – ADCS7477 (continued) TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted)(1) PARAMETER IMD FPBW TEST CONDITIONS MIN TYP MAX UNIT Intermodulation distortion, second order terms fa = 103.5 kHz, fb = 113.5 kHz –78 dB Intermodulation distortion, third order terms fa = 103.5 kHz, fb = 113.5 kHz –78 dB 5-V supply 11 MHz 3-V supply 8 MHz VDD = 4.75 V to 5.25 V, SCLK On or Off 2 mA VDD = 2.7 V to 3.6 V, SCLK On or Off 1 mA VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS TA = 25°C 2 VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS TA = 25°C –3-dB full power bandwidth POWER SUPPLY CHARACTERISTICS Normal mode (static) IDD Normal mode (operational) Shutdown mode Power consumption, normal mode (operational) PD Power consumption, shutdown mode –40°C ≤ TA ≤ 85°C 0.6 –40°C ≤ TA ≤ 85°C 0.5 VDD = 5 V, SCLK On 60 TA = 25°C VDD = 3 V, fSAMPLE = 1 MSPS TA = 25°C mA 1.6 VDD = 5 V, SCLK Off VDD = 5 V, fSAMPLE = 1 MSPS mA 3.5 µA 10 –40°C ≤ TA ≤ 85°C mW 17.5 2 –40°C ≤ TA ≤ 85°C mW 4.8 VDD = 5 V, SCLK Off 2.5 VDD = 3 V, SCLK Off 1.5 µW ANALOG INPUT CHARACTERISTICS VIN Input range IDCL DC leakage current CINA Analog input capacitance 0 to VDD TA = −40°C to 85°C V ±1 µA 30 pF DIGITAL INPUT CHARACTERISTICS VIH Input high voltage VIL Input low voltage IIN CIND TA = −40°C to 85°C Input current 2.4 VDD = 5 V, –40°C ≤ TA ≤ 85°C 0.8 VDD = 3 V, –40°C ≤ TA ≤ 85°C 0.4 VIN = 0 V or VDD TA = 25°C V V ±10 –40°C ≤ TA ≤ 85°C nA ±1 TA = 25°C Digital input capacitance V µA 2 –40°C ≤ TA ≤ 85°C pF 4 DIGITAL OUTPUT CHARACTERISTICS VOH Output high voltage ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C VOL Output low voltage ISINK = 200 µA, –40°C ≤ TA ≤ 85°C IOL TRI-STATE leakage current –40°C ≤ TA ≤ 85°C COUT TRI-STATE output capacitance VDD – 0.2 TA = 25°C V 0.4 V ±10 µA 2 –40°C ≤ TA ≤ 85°C pF 4 Output coding Straight (natural) binary AC ELECTRICAL CHARACTERISTICS fSCLK Clock frequency –40°C ≤ TA ≤ 85°C DC SCLK duty cycle –40°C ≤ TA ≤ 85°C tTH Track or hold acquisition time –40°C ≤ TA ≤ 85°C 400 fRATE Throughput rate –40°C ≤ TA ≤ 85°C 1 tAD Aperture delay 20 40% MHz 60% ns MSPS 3 Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ns 7 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Electrical Characteristics – ADCS7477 (continued) TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted)(1) PARAMETER tAJ TEST CONDITIONS MIN Aperture jitter TYP MAX 30 UNIT ps 6.7 Electrical Characteristics – ADCS7478 TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CONVERTER CHARACTERISTICS Resolution with no missing codes INL Integral non-linearity DNL Differential non-linearity VOFF Offset error GE Gain error –40°C ≤ TA ≤ 85°C 8 TA = 25°C ±0.05 –40°C ≤ TA ≤ 85°C ±0.3 TA = 25°C ±0.07 –40°C ≤ TA ≤ 85°C ±0.3 TA = 25°C ±0.03 –40°C ≤ TA ≤ 85°C ±0.3 TA = 25°C ±0.08 –40°C ≤ TA ≤ 85°C ±0.4 TA = 25°C Total unadjusted error ±0.07 –40°C ≤ TA ≤ 85°C ±0.3 Bits LSB LSB LSB LSB LSB DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-noise plus distortion ratio fIN = 100 kHz SNR Signal-to-noise ratio TA = 25°C 49.7 –40°C ≤ TA ≤ 85°C dB 49 fIN = 100 kHz 49.7 TA = 25°C dB –77 THD Total harmonic distortion fIN = 100 kHz SFDR Spurious-free dynamic range fIN = 100 kHz Intermodulation distortion, second order terms fa = 103.5 kHz, fb = 113.5 kHz –68 dB Intermodulation distortion, third order terms fa = 103.5 kHz, fb = 113.5 kHz –68 dB 5-V supply 11 MHz 3-V supply 8 MHz VDD = 4.75 V to 5.25 V, SCLK On or Off 2 mA VDD = 2.7 V to 3.6 V, SCLK On or Off 1 mA VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS TA = 25°C 2 VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS TA = 25°C IMD FPBW –3-dB full power bandwidth –40°C ≤ TA ≤ 85°C –65 TA = 25°C 69 –40°C ≤ TA ≤ 85°C dB dB 65 POWER SUPPLY CHARACTERISTICS Normal mode (static) IDD Normal mode (operational) Shutdown mode (1) 8 –40°C ≤ TA ≤ 85°C 3.5 0.6 –40°C ≤ TA ≤ 85°C 1.6 VDD = 5 V, SCLK Off 0.5 VDD = 5 V, SCLK On 60 mA mA µA Data sheet min/max specification limits are ensured by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Electrical Characteristics – ADCS7478 (continued) TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted)(1) PARAMETER TEST CONDITIONS Power consumption, normal mode (operational) PD Power consumption, shutdown mode VDD = 5 V, fSAMPLE = 1 MSPS TA = 25°C VDD = 3 V, fSAMPLE = 1 MSPS TA = 25°C MIN TYP MAX UNIT 10 –40°C ≤ TA ≤ 85°C mW 17.5 2 –40°C ≤ TA ≤ 85°C mW 4.8 VDD = 5 V, SCLK Off 2.5 VDD = 3 V, SCLK Off 1.5 µW ANALOG INPUT CHARACTERISTICS VIN Input range IDCL DC leakage current 0 to VDD CINA Analog input capacitance V –40°C ≤ TA ≤ 85°C ±1 µA 30 pF DIGITAL INPUT CHARACTERISTICS VIH –40°C ≤ TA ≤ 85°C Input high voltage VIL Input low voltage IIN V 0.8 VDD = 3 V, –40°C ≤ TA ≤ 85°C Digital input current CIND 2.4 VDD = 5 V, –40°C ≤ TA ≤ 85°C 0.4 TA = 25°C VIN = 0 V or VDD V ±10 nA –40°C ≤ TA ≤ 85°C ±1 TA = 25°C Input capacitance V µA 2 –40°C ≤ TA ≤ 85°C p 4 DIGITAL OUTPUT CHARACTERISTICS VOH Output high voltage ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C VOL Output low voltage ISINK = 200 µA, –40°C ≤ TA ≤ 85°C 0.4 V IOL TRI-STATE leakage current –40°C ≤ TA ≤ 85°C ±10 µA COUT TRI-STATE output capacitance 4 pF 20 MHz VDD − 0.2 V 2 Output coding Straight (natural) binary AC ELECTRICAL CHARACTERISTICS fSCLK Clock frequency –40°C ≤ TA ≤ 85°C DC SCLK duty cycle –40°C ≤ TA ≤ 85°C tTH Track or hold acquisition time –40°C ≤ TA ≤ 85°C fRATE Throughput rate –40°C ≤ TA ≤ 85°C (see Application Information) tAD Aperture delay 3 ns tAJ Aperture jitter 30 ps 40% 60% 400 1 ns MSPS 6.8 Timing Requirements –40°C ≤ TA ≤ 85°C, VDD = 2.7 V to 5.25 V, and fSCLK = 20 MHz (unless otherwise noted) (1) PARAMETER CONDITIONS tCONVERT MIN TA = 25°C TYP MAX UNIT 16 × tSCLK tQUIET Quiet time (2) 50 ns t1 Minimum CS pulse width 10 ns t2 CS to SCLK setup time 10 ns t3 Delay from CS until SDATA TRI-STATE disabled (3) (1) (2) (3) 20 ns All input signals are specified as tr = tf = 5 ns (10% to 90% VDD) and timed from 1.6 V. Minimum quiet time required between bus relinquish and start of next conversion. Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 9 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Timing Requirements (continued) –40°C ≤ TA ≤ 85°C, VDD = 2.7 V to 5.25 V, and fSCLK = 20 MHz (unless otherwise noted)(1) PARAMETER CONDITIONS t4 Data access time after SCLK falling edge (4) t5 SCLK low pulse width t6 SCLK high pulse width t7 SCLK to data valid hold time TYP MAX UNIT VDD = 2.7 V to 3.6 V 40 ns VDD = 4.75 V to 5.25 V 20 ns 0.4 × tSCLK ns 0.4 × tSCLK ns VDD = 2.7 V to 3.6 V 7 ns VDD = 4.75 V to 5.25 V 5 6 VDD = 4.75 V to 5.25 V 5 t8 SCLK falling edge to SDATA high impedance (5) VDD = 2.7 V to 3.6 V tPOWER-UP Power-up time from full power down TA = 25°C (4) (5) MIN ns 25 25 1 ns ns µs Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V or 2 V. t8 is derived from the time taken by the outputs to change by 0.5 V with the loading circuit (Figure 1). The measured number is then adjusted to remove the effects of charging or discharging the 25-pF capacitor. This means t8 is the true bus relinquish time, independent of the bus loading. Figure 1. Timing Test Circuit Figure 2. ADCS7476 Serial Interface Timing Diagram 10 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Figure 3. ADCS7477 Serial Interface Timing Diagram Figure 4. ADCS7478 Serial Interface Timing Diagram Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 11 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com 6.9 Typical Characteristics TA = 25°C, VDD = 3 V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, and fIN = 100 kHz (unless otherwise noted) 12 Figure 5. ADCS7476 DNL Figure 6. ADCS7476 INL Figure 7. ADCS7476 Spectral Response at 100-kHz Input Figure 8. ADCS7476 THD vs Source Impedance Figure 9. ADCS7476 THD vs Input Frequency, 600 KSPS Figure 10. ADCS7476 THD vs Input Frequency, 1 MSPS Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Typical Characteristics (continued) TA = 25°C, VDD = 3 V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, and fIN = 100 kHz (unless otherwise noted) Figure 11. ADCS7476 SINAD vs Input Frequency, 600 KSPS Figure 12. ADCS7476 SINAD vs Input Frequency, 1 MSPS Figure 13. ADCS7476 SNR vs fSCLK Figure 14. ADCS7476 SINAD vs fSCLK Figure 15. ADCS7477 DNL Figure 16. ADCS7477 INL Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 13 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) TA = 25°C, VDD = 3 V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, and fIN = 100 kHz (unless otherwise noted) 14 Figure 17. ADCS7477 Spectral Response at 100-kHz Input Figure 18. ADCS7477 SNR vs fSCLK Figure 19. ADCS7477 SINAD vs fSCLK Figure 20. ADCS7478 DNL Figure 21. ADCS7478 INL Figure 22. ADCS7478 Spectral Response at 100-kHz Input Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Typical Characteristics (continued) TA = 25°C, VDD = 3 V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, and fIN = 100 kHz (unless otherwise noted) Figure 23. ADCS7478 SNR vs fSCLK Copyright © 2003–2016, Texas Instruments Incorporated Figure 24. ADCS7478 SINAD vs fSCLK Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 15 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com 7 Detailed Description 7.1 Overview The ADCS747x devices are successive-approximation analog-to-digital converters designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADCS747x in both track and hold operation are shown in Figure 25 and Figure 26. In Figure 26, the device is in track mode where the switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to hold mode. 7.2 Functional Block Diagram VIN ADCS7476 ADCS7477 ACDS7478 T/H SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description Serial interface timing diagrams for the ADCS747x are shown in Figure 2, Figure 3, and Figure 4. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found. Basic operation of the ADCS747x begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK will be labeled with reference to the falling edge of CS; for example, the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low. At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion at the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2, Figure 3, or Figure 4). The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read a complete sample from the ADCS747x. The sample bits (including any leading or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. ADCS747x produces four leading zeroes on SDATA, followed by twelve, ten, or eight data bits (the most significant first). After the data bits, the ADCS7477 clocks out two trailing zeros, and the ADCS7478 clocks out four trailing zeros. The ADCS7476 does not clock out any trailing zeros; the least significant data bit is valid on the 16th falling edge of SCLK. Depending upon the application, the first edge on SCLK after CS goes low may be either a falling edge or a rising edge. If the first SCLK edge after CS goes low is a rising edge, all four leading zeroes are valid on the first four falling edges of SCLK. If instead the first SCLK edge after CS goes low is a falling edge, the first leading zero may not be set up in time for a microprocessor or DSP to read it correctly. The remaining data bits are still clocked out on the falling edges of SCLK. 16 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 7.4 Device Functional Modes Figure 25 shows the device in hold mode where the switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode (Figure 26) on the 13th rising edge of SCLK. CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 + - CONTROL LOGIC SW2 GND VDD/2 Figure 25. ADCS747x in Hold Mode CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 + SW2 - CONTROL LOGIC GND VDD/2 Figure 26. ADCS747x in Track Mode 7.4.1 Transfer Function The output format of ADCS747x is straight binary. Code transitions occur midway between successive integer LSB values. The LSB widths for the ADCS7476 is VDD / 4096; for the ADCS7477 the LSB width is VDD / 1024; for the ADCS7478, the LSB width is VDD / 256. The ideal transfer characteristic for the ADCS7476 and ADCS7477 is shown in Figure 27, while the ideal transfer characteristic for the ADCS7478 is shown in Figure 28. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 17 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Device Functional Modes (continued) Figure 27. ADCS7476/77 Ideal Transfer Characteristic Figure 28. ADCS7478 Ideal Transfer Characteristic 7.4.2 Power-Up Timing The ADCS747x typically requires 1 µs to power up, either after first applying VDD, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADCS747x performs conversions properly. NOTE The tQUIET time must still be included between the first dummy conversion and the second valid conversion. 18 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Device Functional Modes (continued) 7.4.3 Modes of Operation The ADCS747x has two possible modes of operation: Normal Mode and Shutdown Mode. ADCS747x enters normal mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains low. Once in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade off throughput for power consumption. 7.4.3.1 Normal Mode The best possible throughput is obtained by leaving the ADCS747x in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low). If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device remains in normal mode, but the current conversion is aborted, and SDATA returns to TRI-STATE (truncating the output word). Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again. 7.4.3.2 Start-Up Mode When the VDD supply is first applied, the ADCS747x may power up in either of the two modes: normal or shutdown. As such, one dummy conversion should be performed after start-up, exactly as described in PowerUp Timing. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode. 7.4.3.3 Shutdown Mode Shutdown mode is appropriate for applications that either do not sample continuously, or are willing to trade throughput for power consumption. When the ADCS747x is in shutdown mode, all of the analog circuitry is turned off. To enter shutdown mode, a conversion must be interrupted by bringing CS back high anytime between the second and tenth falling edges of SCLK, as shown in Figure 29. Once CS has been brought high in this manner, the device enters shutdown mode; the current conversion is aborted and SDATA enters TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device does not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line. Figure 29. Entering Shutdown Mode Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 19 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Device Functional Modes (continued) Figure 30. Entering Normal Mode To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADCS747x begins powering up. Power up typically takes 1 µs. This microsecond of power-up delay results in the first conversion result being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 30. If CS is brought back high before the 10th falling edge of SCLK, the device returns to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADCS747x is fully powered up after 16 SCLK cycles. 20 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information A typical application of ADCS747x is shown in Figure 32. The combined analog and digital supplies are provided in this example by the TI LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The supply is bypassed with a capacitor network located close to the device. The three-wire interface is also shown connected to a microprocessor or DSP. 8.1.1 Analog Inputs An equivalent circuit for the ADCS747x input channel is shown in Figure 31. The diodes D1 and D2 provide ESD protection for the analog inputs. At no time should an analog input exceed VDD + 300 mV or GND – 300 mV, as these ESD diodes begin conducting current into the substrate or supply line and affect ADC operation. The capacitor C1 in Figure 31 typically has a value of 4 pF, and is mainly due to pin capacitance. The resistor R1 represents the ON resistance of the multiplexer and track or hold switch, and is typically 100 Ω. The capacitor C2 is the ADCS747x sampling capacitor, and is typically 26 pF. The sampling nature of the analog input causes input current pulses that result in voltage spikes at the input. ADCS747x delivers best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. In some applications where dynamic performance is critical, the input must be driven with a low output-impedance amplifier. In addition, when using ADCS747x to sample AC signals, a band-pass or low-pass filter reduces harmonics and noise and thus improve THD and SNR. Figure 31. Equivalent Input Circuit 8.1.2 Digital Inputs and Outputs The ADCS747x digital inputs (SCLK and CS) are not limited by the same absolute maximum ratings as the analog inputs. The digital input pins are instead limited to 6.5 V with respect to GND, regardless of VDD, the supply voltage. This allows ADCS747x to be interfaced with a wide range of logic levels, independent of the supply voltage. NOTE Even though the digital inputs are tolerant of up to 6.5 V above GND, the digital outputs are only capable of driving VDD out. In addition, the digital input pins are not prone to latch-up; SCLK and CS may be asserted before VDD without any risk. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 21 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com 8.2 Typical Application The ADCS747x are monolithic CMOS 12-, 10-, and 8-bit ADCs that use the supply voltage as a reference, enabling the devices to operate with a full-scale input range of 0 to VDD. An example low-power application with the LMT87, which is a wide range ±0.3°C accurate temperature sensor, is shown in Figure 32. VSUPPLY LP2950 1 µF 1 µF 0.1 µF VDD LMT87 OUT VDD CBP VIN CS ADCS747X SCLK GND GND DSP Microcontroller SDATA Copyright © 2016, Texas Instruments Incorporated Figure 32. Typical Application Circuit 8.2.1 Design Requirements A successful ADCS747x and LMT87 design is constrained by the following factors: • VIN range must be 0 V to VDD where VDD can range from 2.7 V to 5.25 V. 8.2.2 Detailed Design Procedure Designing for an accurate measurement requires careful attention to the timing requirements for the ADCS747x parts. Because the ADC747x parts use the supply voltage as a reference, ensuring that the supply voltage is settled to its final level before exiting the shutdown mode and beginning a conversion is important. After the supply voltage has settled, the CS is brought to a low level (ideally 0 V) to start a conversion. Ensuring that any noise on the power supply is less than ½ LSB in amplitude is also important. The supply voltage must be regarded as a precise voltage reference. After the CS has been brought low, the user must wait for one complete conversion cycle (approximately 1 μs) for meaningful data. The dummy conversion cycle is the start-up time of the ADCS747x. The ADCS747x digital output can then be correlated to the LMT87 output level to get an accurate temperature reading. At VDD = 3.3 V, 1 LSB of ADCS7476 is 0.805 mV. 22 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Typical Application (continued) 8.2.3 Application Curves Figure 33. ADCS7476/77 Ideal Transfer Characteristic Figure 34. ADCS7478 Ideal Transfer Characteristic 9 Power Supply Recommendations There are three concerns relating to the power supply of these products: the effects of Power Supply Noise upon the conversion process, the Digital Output Effect Upon Noise upon the conversion process, and Power Management of the product. 9.1 Power Supply Noise Because the supply voltage of the ADCS747x is the reference voltage, any noise greater than 1/2 LSB in amplitude has some effect upon the converter noise performance. This effect is proportional to the input voltage level. The power supply must receive all the considerations of a reference voltage as far as stability and noise is concerned. Using the same supply voltage for these devices as is used for digital components leads to degraded noise performance. 9.2 Digital Output Effect Upon Noise The charging of any output load capacitance requires current from the digital supply, VDD. The current pulses required from the supply to charge the output capacitance causes voltage variations at the ADC supply line. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, causing ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more current flows through the device power supply line and die substrate and the greater is the noise coupled into the analog path. The first solution to keeping digital noise out of the power supply is to decouple the supply from any other components or use a separate supply for the ADC. To keep noise out of the supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and improve noise performance. Because the series resistor and the load capacitance form a low frequency pole, verify signal integrity when the series resistor is added. 9.3 Power Management When ADCS747x is operated continuously in normal mode, throughput up to 1 MSPS can be achieved. The user may trade throughput for power consumption by simply performing fewer conversions per unit time and putting the ADCS747x into shutdown mode between conversions. This method is not advantageous beyond 350-kSPS throughput. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 23 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com Power Management (continued) A plot of maximum power consumption versus throughput is shown in Figure 35. To calculate the power consumption for a given throughput, remember that each time the part exits shutdown mode and enters normal mode, one dummy conversion is required. Generally, the user puts the part into normal mode, execute one dummy conversion followed by one valid conversion, and then put the part back into shutdown mode. When this is done, the fraction of time spent in normal mode may be calculated by multiplying the throughput (in samples per second) by 2 µs, the time taken to perform one dummy and one valid conversion. The power consumption can then be found by multiplying the fraction of time spent in normal mode by the normal mode power consumption figure. The power dissipated while the part is in shutdown mode is negligible. For example, to calculate the power consumption at 300 kSPS with VDD = 5 V, begin by calculating the fraction of time spent in normal mode: 300,000 samples/second x 2 µs = 0.6, or 60%. The power consumption at 300 kSPS is then 60% of 17.5 mW (the maximum power consumption at VDD = 5 V) or 10.5 mW. Figure 35. Maximum Power Consumption vs Throughput 10 Layout 10.1 Layout Guidelines Capacitive coupling between noisy digital circuitry and sensitive analog circuitry can lead to poor performance. The solution is to keep the analog and digital circuitry separated from each other and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. This digital noise could have significant impact upon system noise performance. To avoid performance degradation of the ADCS747x due to supply noise, do not use the same supply for the ADCS747x that is used for digital logic. Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line must also be treated as a transmission line and be properly terminated. The analog input must be isolated from noisy signal lines to avoid coupling of spurious signals into the input. Any external component (that is, a filter capacitor) connected between the input pins and ground of the converter or to the reference input pin and ground must be connected to a very clean point in the ground plane. TI recommends the use of a single, uniform ground plane and the use of split power planes. The power planes must be placed within the same board layer. All analog circuitry (input amplifiers, filters, reference components, and so on) must be placed over the analog power plane. All digital circuitry and I/O lines must be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground must be connected together with short traces and enter the analog ground plane at a single, quiet point. 24 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 10.2 Layout Example Figure 36. Layout Example Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 25 ADCS7476, ADCS7477, ADCS7478 SNAS192G – APRIL 2003 – REVISED MAY 2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature APERTURE DELAY is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF – 1.5 LSB for ADCS7476 and ADCS7477, VREF – 1 LSB for ADCS7478), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the either the two second order or all four third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dBFS. MISSING CODES are those output codes that never appear at the ADC outputs. ADCS747x is ensured not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (that is, GND + 0.5 LSB for the ADCS7476 and ADCS7477, and GND + 1 LSB for the ADCS7478). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding DC. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic levels at the output to the level of the fundamental at the output. THD is calculated as: where • • 26 f1 is the RMS power of the fundamental (output) frequency f2 through f6 are the RMS power in the first 5 harmonic frequencies Submit Documentation Feedback (1) Copyright © 2003–2016, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Device Support (continued) TOTAL UNADJUSTED ERROR is the worst deviation found from the ideal transfer function. As such, it is a comprehensive specification which includes full scale error, linearity error, and offset error. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks SPI, QSPI, MICROWIRE, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADCS7476 ADCS7477 ADCS7478 27 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADCS7476AIMF NRND SOT-23 DBV 6 1000 TBD Call TI Call TI -40 to 125 X01A ADCS7476AIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01A ADCS7476AIMFE/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01A ADCS7476AIMFX NRND SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 125 X01A ADCS7476AIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01A ADCS7477AIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X02A ADCS7477AIMFE/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X02A ADCS7477AIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X02A ADCS7478AIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X03A ADCS7478AIMFE/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X03A ADCS7478AIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X03A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ ADCS7476AIMF SOT-23 DBV 6 1000 178.0 8.4 ADCS7476AIMF/NOPB SOT-23 DBV 6 1000 178.0 ADCS7476AIMFE/NOPB SOT-23 DBV 6 250 178.0 SOT-23 DBV 6 3000 ADCS7476AIMFX/NOPB SOT-23 DBV 6 ADCS7476AIMFX ADCS7477AIMF/NOPB Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADCS7477AIMFE/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADCS7477AIMFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADCS7478AIMFE/NOPB SOT-23 ADCS7478AIMF/NOPB DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADCS7478AIMFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADCS7476AIMF SOT-23 DBV 6 1000 210.0 185.0 35.0 ADCS7476AIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 ADCS7476AIMFE/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 ADCS7476AIMFX SOT-23 DBV 6 3000 210.0 185.0 35.0 ADCS7476AIMFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 ADCS7477AIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 ADCS7477AIMFE/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 ADCS7477AIMFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 ADCS7478AIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 ADCS7478AIMFE/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 ADCS7478AIMFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated