ADS1018IDGSR

Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 ADS1018 Ultrasmall, Low-Power, SPI™-Compatible, 12-Bit, Analog-to-Digital Converter With Internal Reference and Temperature Sensor 1 Features 3 Description • The ADS1018 is a precision, low-power, 12-bit, noisefree, analog-to-digital converter (ADC) that provides all features necessary to measure the most common sensor signals in an ultrasmall, leadless, X2QFN-10 or VSSOP-10 package. The ADS1018 integrates a programmable gain amplifier (PGA), voltage reference, oscillator and high-accuracy temperature sensor. These features, along with a wide powersupply range from 2 V to 5.5 V, make the ADS1018 ideally suited for power- and space-constrained, sensor-measurement applications. 1 • • • • • • • • • • • Ultrasmall X2QFN Package 2 mm × 1.5 mm × 0.4 mm 12-Bit Noise-Free Resolution Wide Supply Range: 2 V to 5.5 V Low Current Consumption: – Continuous Mode: Only 150 μA – Single-Shot Mode: Automatic Power-Down Programmable Data Rate: 128 SPS to 3300 SPS Single-Cycle Settling Internal Low-Drift Voltage Reference Internal Temperature Sensor: 2°C (max) Error Internal Oscillator Internal PGA Four Single-Ended or Two Differential Inputs Specified Temperature: –40°C to +125°C The ADS1018 performs conversions at data rates up to 3300 samples per second (SPS). The PGA offers input ranges from ±256 mV to ±6.144 V, allowing both large and small signals to be measured with high resolution. An input multiplexer (mux) allows measurement of two differential or four single-ended inputs. The high-accuracy temperature sensor is used for system-level temperature monitoring, or coldjunction compensation for thermocouples. The ADS1018 operates either in continuousconversion mode, or in a single-shot mode that automatically powers down after a conversion. Single-shot mode significantly reduces current consumption during idle periods. Data are transferred through a serial peripheral interface (SPI™). 2 Applications • • • Temperature Measurement: – Thermocouple Measurement – Cold-Junction Compensation – Thermistor Measurement Portable Instrumentation Factory Automation and Process Controls Device Information(1) PART NUMBER ADS1018 PACKAGE BODY SIZE (NOM) X2QFN (10) 1.50 mm × 2.00 mm VSSOP (10) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. K-Type Thermocouple Measurement Using Integrated Temperature Sensor for Cold-Junction Compensation 3.3 V 3.3 V 0.1 F AIN0 VDD Voltage Reference AIN1 ADS1018 SCLK Mux PGA 3.3 V 12-bit û ADC Digital Filter and Interface CS DOUT/DRDY DIN AIN2 Oscillator AIN3 Temperature Sensor GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 5 5 5 5 6 8 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements: Serial Interface...................... Switching Characteristics: Serial Interface................ Typical Characteristics .............................................. Detailed Description ............................................ 10 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 11 15 8.5 Programming........................................................... 16 8.6 Register Maps ......................................................... 19 9 Application and Implementation ........................ 21 9.1 Application Information............................................ 21 9.2 Typical Application ................................................. 26 10 Power Supply Recommendations ..................... 29 10.1 Power-Supply Sequencing.................................... 29 10.2 Power-Supply Decoupling..................................... 29 11 Layout................................................................... 30 11.1 Layout Guidelines ................................................. 30 11.2 Layout Example .................................................... 31 12 Device and Documentation Support ................. 32 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 32 13 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (November 2015) to Revision D Page • Changed maximum VDD voltage from 5.5 V to 7 V in the Absolute Maximum Ratings table............................................... 5 • Changed bit description of Config Register bit 0.................................................................................................................. 20 Changes from Revision B (October 2013) to Revision C Page • Added ESD Ratings table, Feature Description section, Noise Performance section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Changed title, Description section, Features section, and block diagram on front page ....................................................... 1 • Changed title from Product Family to Device Comparison Table and deleted Package Designator column ........................ 4 • Updated descriptions and changed name of I/O column in Pin Configurations and Functions table .................................... 4 • Changed digital input voltage range and added minimum specification for TJ in Absolute Maximum Ratings table............. 5 • Added Differential input impedance specification in Electrical Characteristics ...................................................................... 6 • Changed Condition statement in Timing Requirements: Serial Interface ............................................................................. 8 • Moved tCSDOD, tDOPD, and tCSDOZ parameters from Timing Requirements to Switching Characteristics ................................ 8 • Moved tCSDOD and tCSDOZ values from MIN column to MAX column. ...................................................................................... 8 • Deleted Figure 7, Noise Plot................................................................................................................................................... 9 • Updated Overview section and deleted "Gain = 2/3, 1, 2, 4, 8, or 16" from Functional Block Diagram ............................. 10 • Updated Analog Inputs section............................................................................................................................................. 12 • Updated Full-Scale Range (FSR) and LSB Size section ..................................................................................................... 13 • Updated Reset and Power Up section ................................................................................................................................. 15 • Updated 32-Bit Data Transmission Cycle section ................................................................................................................ 18 • Updated Register Maps section ........................................................................................................................................... 19 • Updated Application Information section .............................................................................................................................. 21 2 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 • Updated Figure 21................................................................................................................................................................ 24 • Deleted Thermocouple Measurement With Cold Junction Temperature section, and moved Figure 23 to Typical Application section................................................................................................................................................................ 26 Changes from Revision A (December 2012) to Revision B Page • Deleted device graphic ........................................................................................................................................................... 1 • Changed bit 1 to NOP0 in Table 5 ....................................................................................................................................... 19 • Changed NOP bit description in Table 5: changed bits[2:0] to bits [2:1] and changed NOP to NOP[1:0]........................... 20 Changes from Original (November 2012) to Revision A • Page Updated page 1 graphic ......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 3 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 5 Device Comparison Table DEVICE RESOLUTION (Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS Differential (Single-Ended) PGA INTERFACE SPECIAL FEATURES ADS1118 16 860 2 (4) Yes SPI Temperature sensor ADS1018 12 3300 2 (4) Yes SPI Temperature sensor ADS1115 16 860 2 (4) Yes I2C Comparator ADS1114 16 860 1 (1) Yes I2C Comparator ADS1113 16 860 1 (1) No I2C None 2 ADS1015 12 3300 2 (4) Yes IC Comparator ADS1014 12 3300 1 (1) Yes I2C Comparator ADS1013 12 3300 1 (1) No I2C None 6 Pin Configuration and Functions RUG Package 10-Pin X2QFN Top View DGS Package 10-Pin VSSOP Top View DIN DIN 10 SCLK 1 9 DOUT/ DRDY CS 2 8 VDD GND 3 7 AIN3 AIN0 4 6 AIN2 5 SCLK 1 10 DIN CS 2 9 DOUT/ DRDY GND 3 8 VDD AIN0 4 7 AIN3 AIN1 5 6 AIN2 AIN1 AIN1 Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 SCLK Digital input Serial clock input 2 CS Digital input Chip select; active low. Connect to GND if not used. 3 GND Supply 4 AIN0 Analog input Analog input 0. Leave unconnected or tie to VDD if not used. 5 AIN1 Analog input Analog input 1. Leave unconnected or tie to VDD if not used. 6 AIN2 Analog input Analog input 2. Leave unconnected or tie to VDD if not used. 7 AIN3 Analog input Analog input 3. Leave unconnected or tie to VDD if not used. 8 VDD Supply 9 DOUT/DRDY Digital output 10 DIN Digital input 4 Ground Power supply. Connect a 0.1-µF power-supply decoupling capacitor to GND. Serial data output combined with data ready; active low Serial data input Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.3 7 V AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 V DIN, DOUT/DRDY, SCLK, CS GND – 0.3 VDD + 0.3 V Any pin except power supply pins –10 10 mA Junction, TJ –40 150 Storage, Tstg –60 150 Power-supply voltage VDD to GND Analog input voltage Digital input voltage Input current, continuous Temperature (1) °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VDD Power supply VDD to GND 2 5.5 V GND VDD V GND VDD V –40 125 °C ANALOG INPUTS (1) FSR Full-scale input voltage (2) V(AINx) Absolute input voltage VIN = V(AINP) – V(AINN) See Table 1 DIGITAL INPUTS Input voltage TEMPERATURE TA (1) (2) Operating ambient temperature AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs. This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. 7.4 Thermal Information ADS1018 THERMAL METRIC (1) DGS (VSSOP) RUG (X2QFN) 10 PINS 10 PINS UNIT RθJA Junction-to-ambient thermal resistance 186.8 245.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.5 69.3 °C/W RθJB Junction-to-board thermal resistance 108.4 172 °C/W ψJT Junction-to-top characterization parameter 2.7 8.2 °C/W ψJB Junction-to-board characterization parameter 106.5 170.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 5 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 7.5 Electrical Characteristics Maximum and minimum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All specifications are at VDD = 3.3 V and FSR = ±2.048 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Common-mode input impedance FSR = ±6.144 V (1) 8 FSR = ±4.096 V (1), FSR = ±2.048 V 6 FSR = ±1.024 V 3 FSR = ±0.512 V, FSR = ±0.256 V FSR = ±6.144 V Differential input impedance MΩ 100 (1) 22 FSR = ±4.096 V (1) 15 FSR = ±2.048 V 4.9 FSR = ±1.024 V 2.4 FSR = ±0.512 V, FSR = ±0.256 V 710 MΩ kΩ SYSTEM PERFORMANCE Resolution (no missing codes) DR INL 12 Data rate Bits 128, 250, 490, 920, 1600, 2400, 3300 Data rate variation All data rates Integral nonlinearity DR = 128 SPS, FSR = ±2.048 V (2) Offset error –10% 10% 0.5 FSR = ±2.048 V, differential inputs 0 FSR = ±2.048 V, single-ended inputs ±0.25 Offset drift FSR = ±2.048 V 0.002 Offset channel match Match between any two inputs Gain error (3) FSR = ±2.048 V, TA = 25°C Gain drift (3) (4) SPS ±0.5 FSR = ±0.256 V 7 FSR = ±2.048 V 5 FSR = ±6.144 V (1) 5 LSB LSB/°C 0.25 0.05% LSB LSB 0.25% 40 Gain match (3) Match between any two gains 0.02% 0.1% Gain channel match Match between any two inputs 0.05% 0.1% ppm/°C TEMPERATURE SENSOR Temperature range –40 Temperature resolution TA = 0°C to 70°C Accuracy TA = –40°C to +125°C versus supply (1) (2) (3) (4) 6 125 0.125 °C °C/LSB 0.25 ±1 0.5 ±2 0.125 ±1 °C °C/V This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. Best-fit INL; covers 99% of full-scale. Includes all errors from onboard PGA and voltage reference. Maximum value specified by characterization. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 Electrical Characteristics (continued) Maximum and minimum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All specifications are at VDD = 3.3 V and FSR = ±2.048 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS/OUTPUTS VIH High-level input voltage 0.7 VDD VDD V VIL Low-level input voltage GND 0.2 VDD V VOH High-level output voltage IOH = 1 mA 0.8 VDD VOL Low-level output voltage IOL = 1 mA GND 0.2 VDD V IH Input leakage, high VIH = 5.5 V –10 10 μA IL Input leakage, low VIL = GND –10 10 μA V POWER SUPPLY Power-down, TA = 25°C IVDD Supply current 0.5 2 150 200 Power-down Operating, TA = 25°C 5 Operating PD Power dissipation μA 300 VDD = 5 V 0.9 VDD = 3.3 V 0.5 VDD = 2 V 0.3 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 mW 7 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 7.6 Timing Requirements: Serial Interface over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted) MIN (1) MAX UNIT tCSSC Delay time, CS falling edge to first SCLK rising edge 100 ns tSCCS Delay time, final SCLK falling edge to CS rising edge 100 ns tCSH Pulse duration, CS high 200 ns tSCLK SCLK period 250 ns tSPWH Pulse duration, SCLK high 100 ns 100 ns tSPWL Pulse duration, SCLK low (2) tDIST Setup time, DIN valid before SCLK falling edge 50 ns tDIHD Hold time, DIN valid after SCLK falling edge 50 ns tDOHD Hold time, SCLK rising edge to DOUT invalid 0 ns (1) (2) 28 ms CS can be tied low permanently in case the serial bus is not shared with any other device. Holding SCLK low longer than 28 ms resets the SPI interface. 7.7 Switching Characteristics: Serial Interface over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tCSDOD Propagation delay time, CS falling edge to DOUT driven DOUT load = 20 pF || 100 kΩ to GND tDOPD Propagation delay time, SCLK rising edge to valid new DOUT DOUT load = 20 pF || 100 kΩ to GND tCSDOZ Propagation delay time, CS rising edge to DOUT high impedance DOUT load = 20 pF || 100 kΩ to GND TYP 0 MAX UNIT 100 ns 50 ns 100 ns tCSH CS tSCLK tCSSC tSPWH tSCCS SCLK tDIHD tDIST tSPWL tSCSC DIN tCSDOD tDOHD tDOPD Hi-Z tCSDOZ Hi-Z DOUT Figure 1. Serial Interface Timing 8 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 7.8 Typical Characteristics at TA = 25°C, VDD = 3.3 V, and FSR = ±2.048 V (unless otherwise noted) 5 300 4.5 Power-Down Current (mA) Operating Current (mA) 250 VDD = 5 V 200 150 VDD = 3.3 V VDD = 2 V 100 50 4 3.5 VDD = 2 V 3 2.5 2 VDD = 3.3 V 1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 120 140 -20 0 20 100 120 140 Figure 3. Power-Down Current vs Temperature 60 FSR = ±4.096 V FSR = ±2.048 V (1) FSR = ±1.024 V FSR = ±0.512 V 50 VDD = 2 V 40 VDD = 5 V Offset Voltage (mV) 0 -50 -100 -150 -200 VDD = 5 V -300 -40 30 VDD = 4 V 20 VDD = 3 V 10 0 VDD = 2 V -10 -250 -20 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 Temperature (°C) Figure 4. Single-Ended Offset Voltage vs Temperature 1 80 100 120 140 Average Temperature Error Average “ 3 sigma Average “ 6 sigma Temperature Error (ƒC) 0.8 FSR = ±0.512 V 0.02 0.01 FSR = ±1.024 V, ±2.048 V, (1) (1) ±4.096 V , and ±6.144 V 0 60 Figure 5. Differential Offset Voltage vs Temperature FSR = ±0.256 V 0.04 40 Temperature (°C) 0.05 Gain Error (%) 80 Figure 2. Operating Current vs Temperature 50 -0.01 -0.02 -0.03 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.04 -1 -40 -20 0 20 40 60 80 100 120 140 -40 Temperature (°C) -20 0 20 40 60 80 100 Temperature (ƒC) Figure 6. Gain Error vs Temperature (1) 60 Temperature (°C) 100 0.03 40 Temperature (°C) 150 Offset Voltage (mV) VDD = 5 V 0 -40 120 C001 Figure 7. Temperature Sensor Error vs Temperature This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3 V be applied to this device. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 9 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 8 Detailed Description 8.1 Overview The ADS1018 is a very small, low-power, noise-free, 12-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The ADS1018 consists of a ΔΣ ADC core with adjustable gain, an internal voltage reference, a clock oscillator, and an SPI. This device is also a highly linear and accurate temperature sensor. All of these features are intended to reduce required external circuitry and improve performance. The Functional Block Diagram section shows the ADS1018 functional block diagram. The ADS1018 ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN). The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation in any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS1018 has two available conversion modes: single-shot and continuous-conversion. In single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an internal conversion register. The device then enters a power-down state. This mode is intended to provide significant power savings in systems that require only periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recently completed conversion. 8.2 Functional Block Diagram VDD Device Voltage Reference Mux CS AIN0 SCLK AIN1 PGA 12-Bit ΔΣ ADC Serial Peripheral Interface DIN DOUT/DRDY AIN2 Oscillator AIN3 Temperature Sensor GND 10 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 8.3 Feature Description 8.3.1 Multiplexer The ADS1018 contains an input multiplexer (mux), as shown in Figure 8. Either four single-ended or two differential signals can be measured. Additionally, AIN0, AIN1, and AIN2 can be measured differentially to AIN3. The multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. VDD Device AIN0 VDD GND AINP AIN1 AINN VDD GND AIN2 VDD GND AIN3 GND GND Figure 8. Input Multiplexer When measuring single-ended inputs, the device does not output negative codes. These negative codes indicate negative differential signals; that is, (V(AINP) – V(AINN)) < 0. Electrostatic discharge (ESD) diodes to VDD and GND protect the ADS1018 inputs. To prevent the ESD diodes from turning on, keep the absolute voltage on any input within the range given in Equation 1: GND – 0.3 V < V(AINx) < VDD + 0.3 V (1) If the voltages on the input pins can possibly violate these conditions, use external Schottky diodes and series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table). Also, overdriving one unused input on the ADS1018 may affect conversions currently taking place on other input pins. If overdriving unused inputs is possible, clamp the signal with external Schottky diodes. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 11 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Feature Description (continued) 8.3.2 Analog Inputs The ADS1018 uses a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. This frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (f(MOD)). The ADS1018 has a 1-MHz internal oscillator which is further divided by a factor of 4 to generate the modulator frequency at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. This structure is shown in Figure 9. The resistance is set by the capacitor values and the rate at which they are switched. Figure 10 shows the setting of the switches illustrated in Figure 9. During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN), and CB to (V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the source driving the ADS1018 analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE. 0.7 V CA1 AINP S1 ZCM S2 0.7 V Equivalent Circuit AINP CB S1 ZDIFF S2 AINN AINN 0.7 V CA2 ZCM f(MOD) = 250 kHz 0.7 V Figure 9. Simplified Analog Input Circuit tSAMPLE ON S1 OFF ON S2 OFF Figure 10. S1 and S2 Switch Timing Common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 9, the common-mode input impedance is ZCM. The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 9, the differential input impedance is ZDIFF. Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS1018 input impedance may affect the measurement accuracy. For sources with high output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications. The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored. 12 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 Feature Description (continued) 8.3.3 Full-Scale Range (FSR) and LSB Size A programmable gain amplifier (PGA) is implemented in front of the ADS1018 ΔΣ ADC core. The full-scale range is configured by bits PGA[2:0] in the Config register, and can be set to ±6.144 V, ±4.096 V, ±2.048 V, ±1.024 V, ±0.512 V, or ±0.256 V. Table 1 shows the FSR together with the corresponding LSB size. Calculate the LSB size from the full-scale voltage by the formula shown in Equation 2. However, make sure that the analog input voltage never exceeds the analog input voltage range limit given in the Electrical Characteristics. If VDD greater than 4 V is used, the ±6.144-V full-scale range allows input voltages to extend up to the supply. Note though that in this case, or whenever the supply voltage is less than the full-scale range (for example, VDD = 3.3 V and full-scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. This inability means that some dynamic range is lost. LSB = FSR / 212 (2) Table 1. Full-Scale Range and Corresponding LSB Size (1) FSR LSB SIZE ±6.144 V (1) 3 mV ±4.096 V (1) 2 mV ±2.048 V 1 mV ±1.024 V 0.5 mV ±0.512 V 0.25 mV ±0.256 V 0.125 mV This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device. 8.3.4 Voltage Reference The ADS1018 has an integrated voltage reference. An external reference cannot be used with this device. Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included in the gain error and gain drift specifications in the Electrical Characteristics. 8.3.5 Oscillator The ADS1018 has an integrated oscillator running at 1 MHz. No external clock is required to operate the device. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with the oscillator frequency. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 13 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 8.3.6 Temperature Sensor The ADS1018 offers an integrated precision temperature sensor. To enable the temperature sensor mode, set bit TS_MODE = 1 in the Config register. Temperature data are represented as a 12-bit result that is left-justified within the 16-bit conversion result. Data are output starting with the most significant byte (MSB). When reading the two data bytes, the first 12 bits are used to indicate the temperature measurement result. One 12-bit LSB equals 0.125°C. Negative numbers are represented in binary twos complement format, as shown in Table 2. Table 2. 12-Bit Temperature Data Format TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) 128 0 100 0000 0000 HEX 400 127.875 0 011 1111 1111 3FF 100 0 011 0010 0000 320 80 0 010 1000 0000 280 75 0 010 0101 1000 258 50 0 001 1001 0000 190 25 0 000 1100 1000 0C8 0.25 0 000 0000 0010 002 0 0 000 0000 0000 000 –0.25 1 111 1111 1110 FFE –25 1 111 0011 1000 F38 –40 1 110 1100 0000 EC0 8.3.6.1 Converting from Temperature to Digital Codes For positive temperatures: Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code in a 12-bit, left justified format with the MSB = 0 to denote the positive sign. Example: 50°C / (0.125°C/count) = 400 = 190h = 0001 1001 0000 For negative temperatures: Generate the twos complement of a negative number by complementing the absolute binary number and adding 1. Then, denote the negative sign with the MSB = 1. Example: |–25°C| / (0.125/count) = 200 = 0C8h = 0000 1100 1000 Twos complement format: 1111 0011 01111 + 1 = 1111 0011 1000 8.3.6.2 Converting from Digital Codes to Temperature To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0, simply multiply the decimal code by 0.125°C to obtain the result. If the MSB = 1, subtract 1 from the result and complement all of the bits. Then, multiply the result by –0.125°C. Example: The device reads back 258h: 258h has an MSB = 0. 258h × 0.125°C = 600 × 0.125°C = +75°C Example: The device reads back F38h: F38h has an MSB = 1. Subtract 1 and complement the result: F38h → C8h C8h × (–0.125°C) = 200 × (–0.125°C) = –25°C 14 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 8.4 Device Functional Modes 8.4.1 Reset and Power-Up When the ADS1018 powers up, the device resets. As part of the reset process, the ADS1018 sets all bits in the Config register to the respective default settings. By default, the ADS1018 enters a power-down state at start-up. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS1018 relieves systems with tight power-supply requirements from encountering a surge during power-up. 8.4.2 Operating Modes The ADS1018 operates in one of two modes: continuous-conversion or single-shot. The MODE bit in the Config register selects the respective operating mode. 8.4.2.1 Single-Shot Mode and Power-Down When the MODE bit in the Config register is set to 1, the ADS1018 enters a power-down state, and operates in single-shot mode. This power-down state is the default state for the ADS1018 when power is first applied. Although powered down, the device still responds to commands. The ADS1018 remains in this power-down state until a 1 is written to the single-shot (SS) bit in the Config register. When the SS bit is asserted, the device powers up, resets the SS bit to 0, and starts a single conversion. When conversion data are ready for retrieval, the device powers down again. Writing a 1 to the SS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0 to the MODE bit in the Config register. 8.4.2.2 Continuous-Conversion Mode In continuous-conversion mode (MODE bit set to 0), the ADS1018 continuously performs conversions. When a conversion completes, the ADS1018 places the result in the Conversion register and immediately begins another conversion. To switch to single-shot mode, write a 1 to the MODE bit in the Config register, or reset the device. 8.4.3 Duty Cycling for Low Power The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator are averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the ADS1018 supports duty cycling that can yield significant power savings by periodically requesting high data-rate readings at an effectively lower data rate. For example, an ADS1018 in power-down state with a data rate set to 3300 SPS can be operated by a microcontroller that instructs a single-shot conversion every 7.8 ms (128 SPS). A conversion at 3300 SPS only requires approximately 0.3 ms; therefore, the ADS1018 enters power-down state for the remaining 7.5 ms. In this configuration, the ADS1018 consumes approximately 1/25 the power that is otherwise consumed in continuousconversion mode. The duty cycling rate is completely arbitrary and is defined by the master controller. The ADS1018 offers lower data rates that do not implement duty cycling and also offers improved noise performance, if required. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 15 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 8.5 Programming 8.5.1 Serial Interface The SPI-compatible serial interface consists of either four signals (CS, SCLK, DIN, and DOUT/DRDY), or three signals (SCLK, DIN, and DOUT/DRDY, with CS tied low). The interface is used to read conversion data, read from and write to registers, and control device operation. 8.5.2 Chip Select (CS) The chip select pin (CS) selects the ADS1018 for SPI communication. This feature is useful when multiple devices share the same serial bus. Keep CS low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state, DOUT/DRDY cannot provide data-ready indication. In situations where multiple devices are present and DOUT/DRDY must be monitored, lower CS periodically. At this point, the DOUT/DRDY pin either immediately goes high to indicate that no new data are available, or immediately goes low to indicate that new data are present in the Conversion register and are available for transfer. New data can be transferred at any time without concern of data corruption. When a transmission starts, the current result is locked into the output shift register and does not change until the communication completes. This system avoids any possibility of data corruption. 8.5.3 Serial Clock (SCLK) The serial clock pin (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and DOUT/DRDY pins into and out of the ADS1018. Even though the input has hysteresis, keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. To reset the serial interface, hold SCLK low for 28 ms, and the next SCLK pulse starts a new communication cycle. Use this time-out feature to recover communication when a serial interface transmission is interrupted. When the serial interface is idle, hold SCLK low. 8.5.4 Data Input (DIN) The data input pin (DIN) is used along with SCLK to send data to the ADS1018. The device latches data on DIN at the SCLK falling edge. The ADS1018 never drives the DIN pin. 8.5.5 Data Output and Data Ready (DOUT/DRDY) The data output and data ready pin (DOUT/DRDY) is used with SCLK to read conversion and register data from the ADS1018. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY is also used to indicate that a conversion is complete and new data are available. This pin transitions low when new data are ready for retrieval. DOUT/DRDY is also able to trigger a microcontroller to start reading data from the ADS1018. In continuous-conversion mode, DOUT/DRDY transitions high again 8 µs before the next data ready signal (DOUT/DRDY low) if no data are retrieved from the device. This transition is shown in Figure 11. Complete the data transfer before DOUT/DRDY returns high. CS(1) SCLK 8 µs Hi-Z DOUT/DRDY DIN (1) CS can be held low if the ADS1018 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low indicating new data are available. Figure 11. DOUT/DRDY Behavior Without Data Retrieval in Continuous-Conversion Mode When CS is high, DOUT/DRDY is configured by default with a weak internal pullup resistor. This feature reduces the risk of DOUT/DRDY floating near midsupply and causing leakage current in the master device. To disable this pullup resistor and place the device into a high-impedance state, set the PULL_UP_EN bit to 0 in the Config register. 16 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 Programming (continued) 8.5.6 Data Format The ADS1018 provides 12 bits of data in binary twos complement format that is left justified within the 16-bit data word. A positive full-scale (+FS) input produces an output code of 7FF0h and a negative full-scale (–FS) input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 3 summarizes the ideal output codes for different input signals. Figure 12 shows code transitions versus input voltage. Table 3. Input Signal versus Ideal Output Code (1) INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE (1) ≥ +FS (211 – 1) / 211 7FF0h +FS / 211 0010h 0 0 –FS / 211 FFF0h ≤ –FS 8000h Excludes the effects of noise, INL, offset, and gain errors. 7FF0h 0001h 0000h FFF0h ¼ Output Code ¼ 7FE0h 8010h 8000h ¼ -FS 0 FS ¼ Input Voltage (AINP - AINN) 11 2 -1 -FS 2 11 11 2 -1 FS 2 11 Figure 12. Code Transition Diagram 8.5.7 Data Retrieval Data is written to and read from the ADS1018 in the same manner for both single-shot and continuous conversion modes, without having to issue any commands. The operating mode for the ADS1018 is selected by the MODE bit in the Config register. Set the MODE bit to 0 to put the device in continuous-conversion mode. In continuous-conversion mode, the device is constantly starting new conversions even when CS is high. Set the MODE bit to 1 for single-shot mode. In single-shot mode, a new conversion only starts by writing a 1 to the SS bit. The conversion data are always buffered, and retain the current data until replaced by new conversion data. Therefore, data can be read at any time without concern of data corruption. When DOUT/DRDY asserts low, indicating that new conversion data are ready, the conversion data are read by shifting the data out on DOUT/DRDY. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first SCLK rising edge. At the same time that the conversion result is clocked out of DOUT/DRDY, new Config register data are latched on DIN on the SCLK falling edge. The ADS1018 also offers the possibility of direct readback of the Config register settings in the same data transmission cycle. One complete data transmission cycle consists of either 32 bits (when the Config register data readback is used) or 16 bits (only used when the CS line can be controlled and is not permanently tied low). Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 17 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 8.5.7.1 32-Bit Data Transmission Cycle The data in a 32-bit data transmission cycle consist of four bytes: two bytes for the conversion result, and an additional two bytes for the Config register readback. The device always reads the MSB first. Write the same Config register setting twice during one transmission cycle as shown in Figure 13. If convenient, write the Config register setting once during the first half of the transmission cycle, and then hold the DIN pin either low (as shown in Figure 14) or high during the second half of the cycle. If no update to the Config register is required, hold the DIN pin either low or high during the entire transmission cycle. The Config register setting written in the first two bytes of a 32-bit transmission cycle is read back in the last two bytes of the same cycle. CS(1) 1 9 17 25 SCLK DOUT/DRDY Hi-Z DIN (1) DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Next Data Ready CS can be held low if the ADS1018 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low indicating new data are available. Figure 13. 32-Bit Data Transmission Cycle With Config Register Readback CS(1) 1 9 17 25 SCLK DOUT/DRDY Hi-Z DIN (1) DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Next Data Ready CS can be held low if the ADS1018 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low indicating new data are available. Figure 14. 32-Bit Data Transmission Cycle: DIN Held Low 8.5.7.2 16-Bit Data Transmission Cycle If Config register data are not required to be read back, the ADS1018 conversion data can be clocked out in a short 16-bit data transmission cycle, as shown in Figure 15. Take CS high after the 16th SCLK cycle to reset the SPI interface. The next time CS is taken low, data transmission starts with the currently buffered conversion result on the first SCLK rising edge. If DOUT/DRDY is low when data retrieval starts, the conversion buffer is already updated with a new result. Otherwise, if DOUT/DRDY is high, the same result from the previous data transmission cycle is read. CS 1 9 1 9 SCLK DOUT/DRDY DIN Hi-Z DATA MSB DATA LSB DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Figure 15. 16-Bit Data Transmission Cycle 18 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 8.6 Register Maps The ADS1018 has two registers that are accessible through the SPI. The Conversion register contains the result of the last conversion. The Config register allows the user to change the ADS1018 operating modes and query the status of the devices. 8.6.1 Conversion Register [reset = 0000h] The 16-bit Conversion register contains the result of the last conversion in binary twos complement format. Following power up, the Conversion register is cleared to 0, and remains 0 until the first conversion is complete. The register format is shown in Figure 16. Figure 16. Conversion Register 15 D11 R-0h 7 D3 14 D10 R-0h 6 D2 13 D9 R-0h 5 D1 12 D8 R-0h 4 D0 R-0h R-0h R-0h R-0h 11 D7 R-0h 3 10 D6 R-0h 2 9 D5 R-0h 1 8 D4 R-0h 0 Reserved R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4. Conversion Register Field Descriptions Field Type Reset Description 15:4 Bit D[11:0] R 000h 12-bit conversion result 3:0 Reserved R 0h Always reads back 0h 8.6.2 Config Register [reset = 058Bh] The 16-bit Config register can be used to control the ADS1018 operating mode, input selection, data rate, fullscale range, and temperature sensor mode. The register format is shown in Figure 17. Figure 17. Config Register 15 SS R/W-0h 7 14 13 MUX[2:0] R/W-0h 5 6 DR[2:0] R/W-4h 12 11 4 TS_MODE R/W-0h 3 PULL_UP_EN R/W-1h 10 PGA[2:0] R/W-2h 2 NOP[1:0] R/W-1h 9 1 8 MODE R/W-1h 0 Reserved R-1h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. Config Register Field Descriptions Bit Field Type Reset Description Single-shot conversion start This bit is used to start a single conversion. SS can only be written when in power-down state and has no effect when a conversion is ongoing. 15 SS R/W 0h When writing: 0 = No effect 1 = Start a single conversion (when in power-down state) Always reads back 0 (default). Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 19 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Table 5. Config Register Field Descriptions (continued) Bit Field Type Reset Description Input multiplexer configuration These bits configure the input multiplexer. 14:12 MUX[2:0] R/W 0h 000 = AINP 001 = AINP 010 = AINP 011 = AINP 100 = AINP 101 = AINP 110 = AINP 111 = AINP is is is is is is is is AIN0 AIN0 AIN1 AIN2 AIN0 AIN1 AIN2 AIN3 and AINN is and AINN is and AINN is and AINN is and AINN is and AINN is and AINN is and AINN is AIN1 (default) AIN3 AIN3 AIN3 GND GND GND GND Programmable gain amplifier configuration These bits configure the programmable gain amplifier. 11:9 8 PGA[2:0] MODE R/W R/W 2h 1h 000 = FSR is ±6.144 001 = FSR is ±4.096 010 = FSR is ±2.048 011 = FSR is ±1.024 100 = FSR is ±0.512 101 = FSR is ±0.256 110 = FSR is ±0.256 111 = FSR is ±0.256 V (1) V (1) V (default) V V V V V Device operating mode This bit controls the ADS1018 operating mode. 0 = Continuous-conversion mode 1 = Power-down and single-shot mode (default) Data rate These bits control the data-rate setting. 7:5 4 3 DR[2:0] TS_MODE PULL_UP_EN R/W R/W R/W 4h 0h 1h 000 = 128 SPS 001 = 250 SPS 010 = 490 SPS 011 = 920 SPS 100 = 1600 SPS (default) 101 = 2400 SPS 110 = 3300 SPS 111 = Not Used Temperature sensor mode This bit configures the ADC to convert temperature or input signals. 0 = ADC mode (default) 1 = Temperature sensor mode Pullup enable This bit enables a weak internal pullup resistor on the DOUT/DRDY pin only when CS is high. When enabled, an internal 400-kΩ resistor connects the bus line to supply. When disabled, the DOUT/DRDY pin floats. 0 = Pullup resistor disabled on DOUT/DRDY pin 1 = Pullup resistor enabled on DOUT/DRDY pin (default) 2:1 NOP[1:0] R/W 1h No operation The NOP[1:0] bits control whether data are written to the Config register or not. For data to be written to the Config register, the NOP[1:0] bits must be 01. Any other value results in a NOP command. DIN can be held high or low during SCLK pulses without data being written to the Config register. 00 01 10 11 = Invalid data; do not update the contents of the Config register = Valid data; update the Config register (default) = Invalid data; do not update the contents of the Config register = Invalid data; do not update the contents of the Config register Reserved 0 (1) 20 Reserved R 1h Writing either 0 or 1 to this bit has no effect. Always reads back 1. This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ADS1018 is a precision, 12-bit ΔΣ ADC that offers many integrated features to ease the measurement of the most common sensor types including various type of temperature and bridge sensors. The following sections give example circuits and suggestions for using the ADS1018 in various situations. 9.1.1 Serial Interface Connections The principle serial interface connections for the ADS1018 are shown in Figure 18. Device 10 DIN Microcontroller or Microprocessor with SPI Port 1 SCLK 2 VDD DOUT/DRDY 9 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1 µF AIN1 5 50 W DOUT 50 W DIN 50 W Inputs Selected from Configuration Register CS 50 W SCLK Figure 18. Typical Connections Most microcontroller SPI peripherals operate with the ADS1018. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1, SCLK idles low, and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the ADS1018 can be found in the Timing Requirements: Serial Interface section. It is a good practice to place 50-Ω resistors in the series path to each of the digital pins to provide some shortcircuit protection. Take care to still meet all SPI timing requirements because these additional series resistors along with the bus parasitic capacitances present on the digital signal lines slews the signals. The fully-differential input of the ADS1018 is ideal for connecting to differential sources (such as thermocouples and thermistors) with a moderately low source impedance. Although the ADS1018 can read fully-differential signals, the device cannot accept negative voltages on either of its inputs because of ESD protection diodes on each pin. When an input exceeds supply or drops below ground, these diodes turn on to prevent any ESD damage to the device. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 21 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Application Information (continued) 9.1.2 GPIO Ports for Communication Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or outputs. If an SPI controller is not available, the ADS1018 can be connected to GPIO pins and the SPI bus protocol can be simulated. Using GPIO pins to generate the SPI interface requires only that the pins be configured as push or pull inputs or outputs. Furthermore, if the SCLK line is held low for more than 28 ms, communication times out. This condition means that the GPIO ports must be capable of providing SCLK pulses with no more than 28 ms between pulses. 9.1.3 Analog Input Filtering Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and second, to reduce external noise from being a part of the measurement. As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back and show up in the actual frequency band of interest below half the sampling frequency. The filter response of the digital filter repeats at multiples of the sampling frequency, also known as modulator frequency f(MOD), as shown in Figure 19. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency or multiples thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter. Magnitude Sensor Signal Unwanted Signals Unwanted Signals Output Data Rate f(MOD)/2 f(MOD) Frequency f(MOD) Frequency f(MOD) Frequency Magnitude Digital Filter Aliasing of Unwanted Signals Output Data Rate f(MOD)/2 Magnitude External Antialiasing Filter Roll-Off Output Data Rate f(MOD)/2 Figure 19. Effect of Aliasing 22 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 Application Information (continued) Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of change. In this case the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However, any noise pickup along the sensor wiring or the application circuitry can potentially alias into the pass band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) itself in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result. A first-order, resistor-capacitor (RC) filter is, in most cases, sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond f(MOD) / 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1018 attenuates signals to a certain degree. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or ten times higher is generally a good starting point for a system design. 9.1.4 Single-Ended Inputs Although the ADS1018 has two differential inputs, the device can measure four single-ended signals. Figure 20 shows a single-ended connection scheme. The ADS1018 is configured for single-ended measurement by configuring the mux to measure each channel with respect to ground. Data are then read out of one input based on the selection in the Config register. The single-ended signal can range from 0 V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to this circuit because the ADS1018 can only accept positive voltages with respect to ground. The ADS1018 does not lose linearity within the input range. The ADS1018 offers a differential input voltage range of ±FS. The single-ended circuit shown in Figure 20, however, only uses the positive half of the ADS1018 FS input voltage range because differentially negative inputs are not produced. Because only half of the FS range is used, one bit of resolution is lost. For optimal noise performance, use differential configurations whenever possible. Differential configurations maximize the dynamic range of the ADC and provide strong attenuation of common-mode noise. VDD Device 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1 µF AIN1 5 Inputs Selected from Configuration Register NOTE: Digital pin connections omitted for clarity. Figure 20. Measuring Single-Ended Inputs The ADS1018 also allows AIN3 to serve as a common point for measurements by adjusting the mux configuration. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the ADS1018 operates with inputs where AIN3 serves as the common point. This ability improves the usable range over the single-ended configuration because negative differential voltages are allowed when GND < V(AIN3) < VDD; however, common-mode noise attenuation is not offered. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 23 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Application Information (continued) 9.1.5 Connecting Multiple Devices When connecting multiple ADS1018 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) for each SPI-enabled device. By default, when CS goes high for the ADS1018, DOUT/DRDY is pulled up to VDD by a weak pullup resistor. This feature prevents DOUT/DRDY from floating near midrail and causing excess current leakage on a microcontroller input. If the PULL_UP_EN bit in the Config register is set to 0, the DOUT/DRDY pin enters a 3-state mode when CS transitions high. The ADS1018 cannot issue a data-ready pulse on DOUT/DRDY when CS is high. To evaluate when a new conversion is ready from the ADS1018 when using multiple devices, the master can periodically drop CS to the ADS1018. When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out at any time. If the DOUT/DRDY line drives high, no new data are available and the ADS1018 returns the last read conversion result. Valid data can be retrieved from the ADS1018 at anytime without concern of data corruption. If a new conversion becomes available during data transmission, that conversion is not available for readback until a new SPI transmission is initiated. Microcontroller or Microprocessor Device 10 50 W SCLK DIN 50 W CS1 CS2 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 50 W DOUT 50 W DIN AIN1 5 50 W Device 10 DIN DOUT/DRDY 9 1 SCLK 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 NOTE: Power and input connections omitted for clarity. Figure 21. Connecting Multiple ADS1018s 24 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 Application Information (continued) 9.1.6 Pseudo Code Example The flow chart in Figure 22 shows a pseudo-code sequence with the required steps to set up communication between the device and a microcontroller to take subsequent readings from the ADS1018. As an example, the default Config register settings are changed to set up the device for FSR = ±0.512 V, continuous-conversion mode, and a 920-SPS data rate. INITIALIZE DATA CAPTURE Power-up; Wait for supplies to settle to nominal to ensure power-up reset is complete; Wait for 50 µs POWER DOWN Take CS low Wait for DOUT/ DRDY to transition low NO YES Configure microcontroller SPI interface to SPI mode 1 (CPOL = 0, CPHA = 1); Delay for minimum td(CSSC) Take CS low If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output; Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt input; Set MODE bit in config register to '1' to enter power-down and single-shot mode Delay for minimum td(CSSC) Clear CS to high Read out conversion result and clear CS to high before DOUT/DRDY goes low again Set CS to the device low; Delay for minimum td(CSSC) Write the config register to set the device to FSR = ±0.512 V, continuous conversion mode, data rate = 920 SPS Clear CS to high to reset the serial interface Figure 22. Pseudo-Code Example Flowchart Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 25 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 9.2 Typical Application Figure 23 shows the basic connections for an independent, two-channel thermocouple measurement system when using the internal high-precision temperature sensor for cold-junction compensation. Apart from the thermocouples, the only external circuitry required are biasing resistors; first-order, low-pass, antialiasing filters; and a power-supply decoupling capacitor. 3.3 V GND 3.3 V RPU 1M 0.1 F CCMA 0.1 F RDIFFA 500 AIN0 VDD ADS1018 1 F Voltage Reference AIN1 RDIFFB 500 RPD 1M GND CCMB 0.1 F ±256-mV FSR SCLK GND Mux GND 3.3 V RPU 1M Digital Filter and Interface 12-bit û ADC PGA AIN2 1 F Oscillator AIN3 RPD 1M DOUT/DRDY DIN CCMA 0.1 F RDIFFA 500 CS RDIFFB 500 Temperature Sensor GND CCMB 0.1 F Figure 23. Two-Channel Thermocouple Measurement System 9.2.1 Design Requirements Table 6 lists the design parameters for this application. Table 6. Design Parameters DESIGN PARAMETER (1) VALUE Supply voltage 3.3 V Full-scale range ±0.256 V Update rate ≥ 100 readings per second Thermocouple type K Temperature measurement range –200°C to +1250°C Measurement accuracy at TA = 25°C (1) ±2.7°C With offset calibration, and no gain calibration. Measurement does not account for thermocouple inaccuracy. 9.2.2 Detailed Design Procedure The biasing resistors (RPU and RPD) serve two purposes. The first purpose is to set the common-mode voltage of the thermocouple to within the specified voltage range of the device. The second purpose is to offer a weak pullup and pulldown to detect an open thermocouple lead. When one of the thermocouple leads fails open, the positive input is pulled to VDD and the negative input is pulled to GND. The ADC consequently reads a full-scale value that is outside the normal measurement range of the thermocouple voltage to indicate this failure condition. When choosing the values of the biasing resistors, take care so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ to 50 MΩ. 26 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 Although the device digital filter attenuates high-frequency components of noise, provide a first-order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by RDIFFA, RDIFFB, and the differential capacitor CDIFF offers a cutoff frequency that is calculated using Equation 3. While the digital filter of the ADS1018 strongly attenuates high-frequency components of noise, provide a first-order, passive RC filter to further suppress high-frequency noise and avoid aliasing. Care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. Limit the filter resistor values to below 1 kΩ for best performance. fC = 1 / [2π × (RDIFFA + RDIFFB) × CDIFF] (3) Two common-mode filter capacitors (CCMA and CCMB) are also added to offer attenuation of high-frequency, common-mode noise components. Differential capacitor CDIFF must be at least an order of magnitude (10x) larger than these common-mode capacitors because mismatches in the common-mode capacitors can convert common-mode noise into differential noise. The highest measurement resolution is achieved when the largest potential input signal is slightly lower than the FSR of the ADC. From the design requirement, the maximum thermocouple voltage (VTC) occurs at a thermocouple temperature (TTC) of 1250°C. At this temperature, VTC = 50.644 mV, as defined in the tables published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature (TCJ) of 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at TTC = 1250°C produces an output voltage of VTC = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction temperature of TCJ = –40°C. The device offers a full-scale range of ±0.256 V and that is what is used in this application example. The device integrates a high-precision temperature sensor that can be used to measure the temperature of the cold junction. The temperature sensor mode is enabled by setting bit TS_MODE = 1 in the Config register. The accuracy of the overall temperature sensor depends on how accurately the ADS1018 can measure the cold junction, and hence, careful component placement and PCB layout considerations must be employed for designing an accurate thermocouple system. The ADS1118 Evaluation Module provides a good starting point and offers an example to achieve good cold-junction compensation performance. The ADS1118 Evaluation Module uses the same schematic as shown in Figure 23, except with only one thermocouple channel connected. Refer to the application note, Precision Thermocouple Measurement With the ADS1118, SBAA189, for details on how to optimize your component placement and layout to achieve good cold-junction compensation performance. The calculation procedure to achieve cold-junction compensation can be done in several ways. A typical way is to interleave readings between the thermocouple inputs and the temperature sensor. That is, acquire one on-chip temperature result, TCJ, for every thermocouple ADC voltage measured, VTC. To account for the cold junction, first convert the temperature sensor reading within the ADS1018 to a voltage (VCJ) that is proportional to the thermocouple currently being used. This process is generally accomplished by performing a reverse lookup on the table used for the thermocouple voltage-to-temperature conversion. Adding these two voltages yields the thermocouple-compensated voltage (VActual), where VActual = VCJ + VTC. Then, VActual is converted to a temperature (TActual) using the same NIST lookup table. A block diagram showing this process is given in Figure 24. Refer to application note SBAA189 for a detailed explanation of this method. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 27 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Device MCU Thermocouple Voltage VTC TActual On-chip Temperature TCJ TÆV VCJ VActual VÆT Result Figure 24. Software-Flow Block Diagram Figure 25 and Figure 26 show the expected measurement results. A system offset calibration is performed at TTC = 25°C that equates to VTC = 0 V when TCJ = 25°C. The dashed blue lines in Figure 25 show the maximum error guard band due to ADC gain and nonlinearity error. The dashed blue lines in Figure 26 show the corresponding temperature measurement error guard band calculated from the data in Figure 25 using the NIST tables. The dashed red lines in Figure 26 include the guard band for the temperature sensor inaccuracy (±1°C), in addition to the device gain and nonlinearity error. Note that the results in Figure 25 and Figure 26 do not account for the thermocouple inaccuracy that must also be considered while designing a thermocouple measurement system. 9.2.3 Application Curves 4 0.15 3 Measurement Error (qC) Measurement Error (mV) 0.1 0.05 0 -0.05 -0.1 -0.15 -10 1 0 -1 -2 -3 0 10 20 30 40 Thermocouple Voltage (mV) 50 Figure 25. Voltage Measurement Error vs VTC 28 2 60 -4 -200 0 200 400 600 800 Temperature (qC) 1000 1200 1400 Figure 26. Temperature Measurement Error vs TTC Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 10 Power Supply Recommendations The device requires a single power supply, VDD, to power both the analog and digital circuitry of the device. 10.1 Power-Supply Sequencing Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up reset process to complete. 10.2 Power-Supply Decoupling Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 27. The 0.1-μF bypass capacitor supplies the momentary bursts of extra current required from the supply when the ADS1018 is converting. Place the bypass capacitor as close to the power-supply pin of the device as possible using low-impedance connections. For best performance, use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. VDD Device 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1 µF AIN1 5 Figure 27. Power-Supply Decoupling Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 29 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 11 Layout 11.1 Layout Guidelines Use best design practices when laying out a printed-circuit-board (PCB) for both analog and digital components. This recommendation generally means that the layout separates analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog muxes] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 28. Although Figure 28 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. Microcontroller Device Ground Fill or Ground Plane Supply Generation Optional: Split Ground Cut Signal Conditioning (RC Filters and Amplifiers) Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Interface Transceiver Connector or Antenna Ground Fill or Ground Plane Figure 28. System Component Placement The use of split analog and digital ground planes is not necessary for improved noise performance (although for thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground fill in PCB areas with no components is essential for optimum performance. If the system being used employs a split digital and analog ground plane, TI generally recommends that the ground planes be connected together as close to the device as possible. A two-layer board is possible using common grounds for both analog and digital grounds. Additional layers can be added to simplify PCB trace routing. Ground fill may also reduce EMI and RFI issues. For best system performance, keep digital components, especially RF portions, as far as practically possible from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run through analog areas and avoid placing these traces near sensitive analog components. Digital return currents usually flow through a ground path that is as close to the digital path as possible. If a solid ground connection to a plane is not available, these currents may find paths back to the source that interfere with analog performance. The implications that layout has on the temperature-sensing functions are much more significant than for ADC functions. Bypass supply pins to ground with a low-ESR ceramic capacitor. The optimum placement of the bypass capacitors is as close as possible to the supply pins. The ground-side connections of the bypass capacitors must be low-impedance connections for optimum performance. The supply current flows through the bypass capacitor terminal first and then to the supply pin to make the bypassing most effective. Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Use high-quality differential capacitors. The best ceramic-chip capacitors are C0G (NPO), with stable properties and low-noise characteristics. Thermally isolate a copper region around the thermocouple input connections to create a thermally-stable cold junction. Obtaining acceptable performance with alternate layout schemes is possible as long as the above guidelines are followed. See Figure 29 and Figure 30 for layout examples of the X2QFN and VSSOP packages. 30 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 ADS1018 www.ti.com SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 DOUT/DRDY DIN 11.2 Layout Example Vias connect to either the bottom layer or an internal plane. The bottom layer or internal plane are dedicated GND planes VDD 10 SCLK CS 1 SCLK 2 CS DIN DOUT/ DRDY 9 VDD 8 Device 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 AIN3 AIN2 AIN1 AIN0 5 DOUT/DRDY DIN Figure 29. X2QFN Package SCLK VDD CS AIN0 1 SCLK 2 CS 3 GND 4 5 Device DIN 10 DOUT/ DRDY 9 VDD 8 AIN0 AIN3 7 AIN1 AIN2 6 AIN3 AIN2 AIN1 Figure 30. VSSOP Package Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 31 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Precision Thermocouple Measurement with the ADS1118 application reports • Texas Instruments, ADS1118EVM User Guide and Software Tutorial user guide • Texas Instruments, 430BOOST-ADS1118 BoosterPack user guide • Texas Instruments, ADS1118 Boosterpack quick start • Texas Instruments, A Glossary of Analog-to-Digital Specifications and Performance Characteristics application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ADS1018 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1018IDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BTNQ ADS1018IDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BTNQ ADS1018IRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SDZ ADS1018IRUGT ACTIVE X2QFN RUG 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SDZ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of