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ADS1113, ADS1114, ADS1115
SBAS444D – MAY 2009 – REVISED JANUARY 2018
ADS111x Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
1 Features
3 Description
•
The ADS1113, ADS1114, and ADS1115 devices
(ADS111x) are precision, low-power, 16-bit, I2Ccompatible, analog-to-digital converters (ADCs)
offered in an ultra-small, leadless, X2QFN-10
package, and a VSSOP-10 package. The ADS111x
devices incorporate a low-drift voltage reference and
an oscillator. The ADS1114 and ADS1115 also
incorporate a programmable gain amplifier (PGA) and
a digital comparator. These features, along with a
wide operating supply range, make the ADS111x well
suited for power- and space-constrained, sensor
measurement applications.
1
•
•
•
•
•
•
•
•
•
•
Ultra-Small X2QFN Package:
2 mm × 1.5 mm × 0.4 mm
Wide Supply Range: 2.0 V to 5.5 V
Low Current Consumption: 150 μA
(Continuous-Conversion Mode)
Programmable Data Rate:
8 SPS to 860 SPS
Single-Cycle Settling
Internal Low-Drift Voltage Reference
Internal Oscillator
I2C Interface: Four Pin-Selectable Addresses
Four Single-Ended or Two Differential Inputs
(ADS1115)
Programmable Comparator (ADS1114 and
ADS1115)
Operating Temperature Range:
–40°C to +125°C
The ADS111x perform conversions at data rates up
to 860 samples per second (SPS). The PGA offers
input ranges from ±256 mV to ±6.144 V, allowing
precise large- and small-signal measurements. The
ADS1115 features an input multiplexer (MUX) that
allows two differential or four single-ended input
measurements. Use the digital comparator in the
ADS1114 and ADS1115 for under- and overvoltage
detection.
2 Applications
•
•
•
•
•
The ADS111x operate in either continuousconversion mode or single-shot mode. The devices
are automatically powered down after one conversion
in single-shot mode; therefore, power consumption is
significantly reduced during idle periods.
Portable Instrumentation
Battery Voltage and Current Monitoring
Temperature Measurement Systems
Consumer Electronics
Factory Automation and Process Control
Device Information(1)
PART NUMBER
ADS111x
PACKAGE
BODY SIZE (NOM)
X2QFN (10)
1.50 mm × 2.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Block Diagrams
VDD
VDD
VDD
Comparator
Voltage
Reference
AIN0
AIN1
16-Bit
û¯
ADC
ADDR
I2C
Interface
SDA
Oscillator
AIN0
PGA
SCL
AIN1
16-Bit
û¯
ADC
ADDR
I2C
Interface
GND
SCL
SDA
AIN0
AIN1
AIN2
AIN3
MUX
PGA
16-Bit
û¯
ADC
ADS1114
GND
ALERT/
RDY
Voltage
Reference
ADDR
I2C
Interface
SCL
SDA
Oscillator
Oscillator
ADS1113
Comparator
ALERT/
RDY
Voltage
Reference
ADS1115
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1113, ADS1114, ADS1115
SBAS444D – MAY 2009 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
5
5
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
6
6
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Timing Requirements: I2C.........................................
Typical Characteristics ..............................................
8
Parameter Measurement Information ................ 13
9
Detailed Description ............................................ 14
8.1 Noise Performance ................................................. 13
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
21
9.5 Programming........................................................... 22
9.6 Register Map........................................................... 27
10 Application and Implementation........................ 31
10.1 Application Information.......................................... 31
10.2 Typical Application ............................................... 36
11 Power Supply Recommendations ..................... 40
11.1 Power-Supply Sequencing.................................... 40
11.2 Power-Supply Decoupling..................................... 40
12 Layout................................................................... 41
12.1 Layout Guidelines ................................................. 41
12.2 Layout Example .................................................... 42
13 Device and Documentation Support ................. 43
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
43
43
14 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2016) to Revision D
Page
•
Changed Digital input voltage max value from VDD + 0.3 V to 5.5 V in Absolute Maximum Ratings table .......................... 6
•
Added "over temperature" to Offset drift parameter for clarity ............................................................................................... 7
•
Added Long-term Offset drift parameter in Electrical Characteristics table ........................................................................... 7
•
Added "over temperature" to Gain drift parameter for clarity ................................................................................................. 7
•
Added Long-term gain drift parameter in Electrical Characteristics table .............................................................................. 7
•
Changed VIH parameter max value from VDD to 5.5 V in Electrical Characteristics table .................................................... 7
•
Added Output Data Rate and Conversion Time section for clarity....................................................................................... 17
•
Changed Figure 28, ALERT Pin Timing Diagram, for clarity................................................................................................ 19
•
Changed Figure 39, Typical Connections of the ADS1115, for clarity ................................................................................. 31
•
Changed the resistor values in Figure 43, Basic Hardware Configuration, from 10 Ω to 10 kΩ.......................................... 35
Changes from Revision B (October 2009) to Revision C
Page
•
Added Device Information, ESD Ratings, Recommended Operating Conditions, and Thermal Information tables,
and Parameter Measurement Information, Detailed Description, Application and Implementation, Power Supply
Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections................................................................................................................................................................ 1
•
Changed Title, and Description, Features, and Applications sections for clarity ................................................................... 1
•
Deleted temperature range text from Description section and moved to Features section ................................................... 1
•
Changed Product Family table title to Device Comparison Table and deleted Package Designator column........................ 5
•
Changed Pin Functions table for clarity.................................................................................................................................. 5
•
Changed Power-supply voltage max value from 5.5 V to 7 V in Absolute Maximum Ratings table...................................... 6
•
Changed Analog input voltage min value from –0.3 V to GND – 0.3 V in Absolute Maximum Ratings table ....................... 6
2
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Product Folder Links: ADS1113 ADS1114 ADS1115
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SBAS444D – MAY 2009 – REVISED JANUARY 2018
•
Changed Digital input voltage min value from –0.5 V to GND – 0.3 V in Absolute Maximum Ratings table......................... 6
•
Changed Digital input voltage max value from 5.5 V to VDD + 0.3 V in Absolute Maximum Ratings table .......................... 6
•
Deleted Analog input current rows in Absolute Maximum Ratings table................................................................................ 6
•
Added Input current row in Absolute Maximum Ratings table ............................................................................................... 6
•
Added Operating temperature range of –40°C to +125°C back into Absolute Maximum Ratings table................................ 6
•
Added minimum specification of –40°C for TJ in Absolute Maximum Ratings table ............................................................. 6
•
Changed Electrical Characteristics table conditions line for clarity ........................................................................................ 7
•
Changed all instances of "FS" to "FSR" ................................................................................................................................. 7
•
Deleted FSR from Electrical Characteristics and moved to Recommended Operating Conditions table .............................. 7
•
Added values from Table 2 to Differential input impedance parameter in Electrical Characteristics table............................ 7
•
Changed Output noise parameter link from "see Typical Characteristics" to "see Noise Performance section" in
Electrical Characteristics table ............................................................................................................................................... 7
•
Changed Offset error empty min value to –3, and max value from ±3 to 3 for clarity in Electrical Characteristics table ...... 7
•
Changed VIH parameter max value from 5.5 V to VDD in Electrical Characteristics table .................................................... 7
•
Changed VIL parameter min value from GND – 0.5 V to GND in Electrical Characteristics table ......................................... 7
•
Changed Input leakage current parameters from two rows to one row, changed test conditions from VIH = 5.5V and
VIL = GND to GND < VDIG < VDD, and changed min value from 10 µA to –10 µA in Electrical Characteristics table........... 7
•
Changed text in note 1 of Electrical Characteristics table from "In no event should more than VDD + 0.3 V be
applied to this device" to "No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device.
See Table 3 for more information."......................................................................................................................................... 7
•
Deleted Power-supply voltage parameter from Electrical Characteristics and moved to Recommended Operating
Conditions table ...................................................................................................................................................................... 8
•
Deleted Specified temperature parameter from Electrical Characteristics and moved to Recommended Operating
Conditions table ...................................................................................................................................................................... 8
•
Deleted Storage temperature parameter from Electrical Characteristics and moved to Absolute Maximum Ratings table .. 8
•
Added condition statement in Timing Requirements: I2C table .............................................................................................. 8
•
Added note 1 to Timing Requirements table .......................................................................................................................... 8
•
Changed Figure 22; deleted "Gain = 2/3, 1, 2, 4, 8, or 16" ................................................................................................. 14
•
Added Functional Block Diagrams for ADS1114 and ADS1113 .......................................................................................... 14
•
Changed Analog Inputs section to provide LSB size information instead of PGA setting ................................................... 16
•
Changed Full-Scale Input section title to Full-Scale Range (FSR) and LSB Size, and updated section for clarity ............. 17
•
Added Voltage Reference and Oscillator sections ............................................................................................................... 17
•
Changed Comparator section title to Digital Comparator, and updated section for clarity. ................................................. 17
•
Changed Conversion Ready Pin section for clarity .............................................................................................................. 19
•
Changed Register Map section for clarity ............................................................................................................................ 27
•
Changed Application Information section for clarity ............................................................................................................. 31
•
Added Input Protection section............................................................................................................................................. 32
•
Added Unused Inputs and Outputs section.......................................................................................................................... 32
•
Changed Aliasing section title to Analog Input Filtering and updated section for clarity...................................................... 33
•
Added Typical Application section........................................................................................................................................ 36
Changes from Revision A (August 2009) to Revision B
Page
•
Deleted Operating Temperature bullet from Features section ............................................................................................... 1
•
Deleted Operating temperature range from Absolute Maximum Ratings table...................................................................... 6
•
Deleted Operating temperature parameter from Temperature section of Electrical Characteristics table............................. 8
•
Changed Figure 2, Operating Current vs Temperature, to reflect maximum operating temperature .................................... 9
•
Changed Figure 3, Power-Down Current vs Temperature, to reflect maximum operating temperature................................ 9
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: ADS1113 ADS1114 ADS1115
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SBAS444D – MAY 2009 – REVISED JANUARY 2018
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•
Changed Figure 4, Single-Ended Offset Error vs Temperature, to reflect maximum operating temperature ........................ 9
•
Changed Figure 5, Differential Offset vs Temperature, to reflect maximum operating temperature ..................................... 9
•
Changed Figure 6, Gain Error vs Temperature, to reflect maximum operating temperature................................................. 9
•
Changed 140°C to 125°C in Figure 9, INL vs Input Signal .................................................................................................... 9
•
Changed +140°C to +125°C in Figure 10, INL vs Input Signal .............................................................................................. 9
•
Changed +140°C to +125°C in Figure 11, INL vs Input Signal .............................................................................................. 9
•
Changed +140°C to +125°C in Figure 12, INL vs Input Signal .............................................................................................. 9
•
Changed Figure 13, INL vs Temperature, to reflect maximum operating temperature.......................................................... 9
•
Changed Figure 16, Noise vs Temperature, to reflect maximum operating temperature .................................................... 10
•
Changed Figure 20, Data Rate vs Temperature, to reflect maximum operating temperature ............................................. 11
4
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Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: ADS1113 ADS1114 ADS1115
ADS1113, ADS1114, ADS1115
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SBAS444D – MAY 2009 – REVISED JANUARY 2018
5 Device Comparison Table
DEVICE
RESOLUTION
(Bits)
MAXIMUM SAMPLE
RATE
(SPS)
INPUT CHANNELS
Differential
(Single-Ended)
PGA
INTERFACE
SPECIAL
FEATURES
ADS1115
16
860
2 (4)
Yes
I2C
Comparator
ADS1114
16
860
1 (1)
Yes
I2C
Comparator
ADS1113
16
860
1(1)
No
I2C
ADS1015
12
3300
2 (4)
Yes
IC
Comparator
ADS1014
12
3300
1 (1)
Yes
I2C
Comparator
ADS1013
12
3300
1 (1)
No
I2C
None
ADS1118
16
860
2 (4)
Yes
SPI
Temperature sensor
ADS1018
12
3300
2 (4)
Yes
SPI
Temperature sensor
None
2
6 Pin Configuration and Functions
RUG Package
10-Pin X2QFN
Top View
SCL
DGS Package
10-Pin VSSOP
Top View
ADDR
1
10
SCL
ALERT/RDY
2
9
SDA
GND
3
8
VDD
AIN0
4
7
AIN3
AIN1
5
6
AIN2
10
ADDR
1
9
SDA
ALERT/RDY
2
8
VDD
3
7
AIN3
AIN0
4
6
AIN2
Not to scale
AIN1
5
GND
Not to scale
Pin Functions
PIN (1)
NAME
ADS1113
ADS1114
ADS1115
TYPE
DESCRIPTION
2
ADDR
1
1
1
Digital input
I C slave address select
AIN0
4
4
4
Analog input
Analog input 0
AIN1
5
5
5
Analog input
Analog input 1
AIN2
—
—
6
Analog input
Analog input 2 (ADS1115 only)
AIN3
—
—
7
Analog input
Analog input 3 (ADS1115 only)
ALERT/RDY
—
2
2
Digital output
Comparator output or conversion ready (ADS1114 and ADS1115 only)
GND
3
3
3
Analog
NC
2, 6, 7
6, 7
—
—
SCL
10
10
10
Digital input
SDA
9
9
9
Digital I/O
VDD
8
8
8
Analog
(1)
Ground
Not connected
Serial clock input. locks data on SDA
Serial data. Transmits and receives data
Power supply. Connect a 0.1-μF, power-supply decoupling capacitor to GND.
See the Unused Inputs and Outputs section for unused pin connections.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: ADS1113 ADS1114 ADS1115
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SBAS444D – MAY 2009 – REVISED JANUARY 2018
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
7
V
AIN0, AIN1, AIN2, AIN3
GND – 0.3
VDD + 0.3
V
SDA, SCL, ADDR, ALERT/RDY
GND – 0.3
5.5
V
Any pin except power supply pins
–10
10
mA
Operating ambient, TA
–40
125
Junction, TJ
–40
150
Storage, Tstg
–60
150
Power-supply voltage
VDD to GND
Analog input voltage
Digital input voltage
Input current, continuous
Temperature
(1)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER SUPPLY
Power supply (VDD to GND)
2
5.5
V
±0.256
±6.144
V
GND
VDD
V
GND
5.5
V
–40
125
°C
ANALOG INPUTS (1)
FSR
Full-scale input voltage range (2) (VIN = V(AINP) – V(AINN))
V(AINx)
Absolute input voltage
DIGITAL INPUTS
VDIG
Digital input voltage
TEMPERATURE
TA
(1)
(2)
Operating ambient temperature
AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs.
This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of
the device. See Table 3 more information.
7.4 Thermal Information
ADS111x
THERMAL METRIC (1)
DGS (VSSOP)
RUG (X2QFN)
UNIT
10 PINS
10 PINS
RθJA
Junction-to-ambient thermal resistance
182.7
245.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.2
69.3
°C/W
RθJB
Junction-to-board thermal resistance
103.8
172.0
°C/W
ψJT
Junction-to-top characterization parameter
10.2
8.2
°C/W
ψJB
Junction-to-board characterization parameter
102.1
170.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5
SBAS444D – MAY 2009 – REVISED JANUARY 2018
Electrical Characteristics
At VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted).
Maximum and minimum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
FSR = ±6.144 V (1)
Common-mode input impedance
10
FSR = ±4.096 V (1), FSR = ±2.048 V
6
FSR = ±1.024 V
3
FSR = ±0.512 V, FSR = ±0.256 V
FSR = ±6.144 V
Differential input impedance
MΩ
100
(1)
22
FSR = ±4.096 V (1)
15
FSR = ±2.048 V
4.9
FSR = ±1.024 V
2.4
FSR = ±0.512 V, ±0.256 V
710
MΩ
kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes)
DR
16
Data rate
Data rate variation
All data rates
Output noise
INL
–10%
10%
DR = 8 SPS, FSR = ±2.048 V (2)
FSR = ±2.048 V, differential inputs
Offset error
1
–3
FSR = ±2.048 V, single-ended inputs
Offset drift over temperature
FSR = ±2.048 V
Long-term Offset drift
FSR = ±2.048 V, TA = 125°C,
1000 hrs
Offset power-supply rejection
Offset channel match
Gain error (3)
FSR = ±2.048 V, TA = 25°C
(3)
±1
LSB
±3
0.005
LSB/°C
±1
LSB
FSR = ±2.048 V, DC supply variation
1
LSB/V
Match between any two inputs
3
0.01%
FSR = ±0.256 V
7
FSR = ±2.048 V
5
FSR = ±6.144 V (1)
5
LSB
0.15%
40
±0.05
Gain match (3)
Match between any two gains
0.02%
0.1%
Gain channel match
Match between any two inputs
0.05%
0.1%
Gain power-supply rejection
Common-mode rejection ratio
LSB
3
FSR = ±2.048 V, TA = 125°C,
1000 hrs
Long-term gain drift (3)
CMRR
SPS
See Noise Performance section
Integral nonlinearity
Gain drift over temperature
Bits
8, 16, 32, 64, 128, 250, 475, 860
%
80
At DC, FSR = ±0.256 V
105
At DC, FSR = ±2.048 V
100
At DC, FSR = ±6.144 V (1)
90
fCM = 60 Hz, DR = 8 SPS
105
fCM = 50 Hz, DR = 8 SPS
105
ppm/°C
ppm/V
dB
DIGITAL INPUT/OUTPUT
VIH
High-level input voltage
0.7 VDD
5.5
V
VIL
Low-level input voltage
GND
0.3 VDD
V
VOL
Low-level output voltage
IOL = 3 mA
Input leakage current
GND < VDIG < VDD
(1)
(2)
(3)
GND
–10
0.15
0.4
V
10
µA
This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of
the device. See Table 3 more information.
Best-fit INL; covers 99% of full-scale.
Includes all errors from onboard PGA and voltage reference.
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Electrical Characteristics (continued)
At VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted).
Maximum and minimum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C
0.5
2
TA = 25°C
150
200
UNIT
POWER-SUPPLY
Power-down
IVDD
5
Supply current
Operating
PD
Power dissipation
µA
300
VDD = 5.0 V
0.9
VDD = 3.3 V
0.5
VDD = 2.0 V
0.3
mW
7.6 Timing Requirements: I2C
over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted)
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
UNIT
0.4
0.01
3.4
MHz
fSCL
SCL clock frequency
0.01
tBUF
Bus free time between START and STOP
condition
600
160
ns
tHDSTA
Hold time after repeated START condition.
After this period, the first clock is generated.
600
160
ns
tSUSTA
Setup time for a repeated START condition
600
160
ns
tSUSTO
Setup time for STOP condition
600
160
ns
tHDDAT
Data hold time
tSUDAT
Data setup time
tLOW
0
0
ns
100
10
ns
Low period of the SCL clock pin
1300
160
ns
tHIGH
High period for the SCL clock pin
600
tF
Rise time for both SDA and SCL signals (1)
300
160
ns
tR
Fall time for both SDA and SCL signals (1)
300
160
ns
(1)
60
ns
For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF.
t LOW
tR
tF
t HDSTA
SCL
t HIGH
t HDSTA
t HDDAT
SDA
t SUSTO
t SUSTA
t SUDAT
t BUF
P
S
S
P
Figure 1. I2C Interface Timing
8
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SBAS444D – MAY 2009 – REVISED JANUARY 2018
7.7 Typical Characteristics
at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)
300
5.0
4.5
Power-down Current (µA)
Operating Current (µA)
250
VDD = 5 V
200
150
VDD = 3.3 V
VDD = 2 V
100
50
4.0
3.5
3.0
2.5
2.0
VDD = 5 V
1.5
VDD = 3.3 V
1.0
0.5
0
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
Figure 2. Operating Current vs Temperature
Figure 3. Power-Down Current vs Temperature
150
60
FSR = ±4.096 V
FSR = ±2.048 V
100
FSR = ±1.024 V
FSR = ±0.512 V
50
VDD = 5 V
50
VDD = 2 V
Offset Voltage (µV)
Offset Error (µV)
VDD = 2 V
0
0
-50
-100
-150
-200
VDD = 5 V
40
30
VDD = 4 V
20
VDD = 3 V
10
0
VDD = 2 V
-10
-250
-20
-300
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
Temperature (°C)
40
60
80
100
120
140
Temperature (°C)
Figure 4. Single-Ended Offset Error vs Temperature
Figure 5. Differential Offset vs Temperature
0.05
0.15
FSR = ±0.256 V
0.04
0.10
FSR = ±0.512 V
0.02
Gain Error (%)
Gain Error (%)
0.03
0.01
FSR = ±1.024 V, ±2.048 V,
±4.096 V, and ±6.144 V
0
-0.01
-0.02
0.05
FSR = ±256 mV
0
FSR = ±2.048 V
-0.05
-0.10
-0.03
-0.15
-0.04
-40
-20
0
20
40
60
80
100
120
140
2.0
2.5
Figure 6. Gain Error vs Temperature
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Temperature (°C)
Figure 7. Gain Error vs Supply Voltage
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Typical Characteristics (continued)
60
60
50
40
Integral Nonlinearity (µV)
Integral Nonlinearity (µV)
at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)
40
FSR = ±6.144 V
30
FSR = ±2.048 V
20
FSR = ±0.512 V, ±0.256 V
+125°C
20
-40°C
0
-20
+25°C
-40
10
-60
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-2.0
5.5
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
Input Signal (V)
Supply Voltage (V)
VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS, best fit
Figure 8. INL vs Supply Voltage
Figure 9. INL vs Input Signal
60
40
Integral Nonlinearity (µV)
Integral Nonlinearity (µV)
60
+125°C
20
-40°C
0
+25°C
-20
-40
40
20
TA = -40°C
0
-20
TA = +125°C
TA = +25°C
-40
-60
-60
-0.5 -0.375 -0.250 -0.125
0
0.125 0.250 0.375
0.5
-2.0
-1.5
-1.0
-0.5
Input Signal (V)
VDD = 3.3 V, FSR = ±0.512 V, DR = 8 SPS, best fit
Figure 10. INL vs Input Signal
1.5
2.0
Figure 11. INL vs Input Signal
120
Integral Nonlinearity (µV)
Integral Nonlinearity (µV)
1.0
140
40
TA = +25°C
TA = -40°C
0
-20
0.5
VDD = 5 V, FSR = ±2.048 V, DR = 8 SPS, best fit
60
20
0
Input Voltage (V)
TA = +125°C
100
80
VDD = 2 V
60
VDD = 5 V
40
-40
20
-60
0
VDD = 3.3 V
-0.5 -0.4 -0.3 -0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-60
-40
-20
Input Voltage (V)
0
20
40
60
80
100
120
140
Temperature (°C)
VDD = 5 V, FSR = ±0.512 V, DR = 8 SPS, best fit
Figure 12. INL vs Input Signal
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Figure 13. INL vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)
12
35
10
30
8
RMS Noise (µV)
RMS Noise (µV)
FSR = ±2.048 V
DR = 860 SPS
6
DR = 128 SPS
4
DR = 8 SPS
20
15
128 SPS
10
2
5
0
0
-0.5 -0.4 -0.3
-0.2 -0.1
0
0.1
0.2
0.3
0.4
860 SPS
25
8 SPS
2.0
0.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Input Voltage (V)
FSR = ±0.512 V
FSR = ±2.048 V
Figure 14. Noise vs Input Signal
Figure 15. Noise vs Supply Voltage
30
10
9
25
Number of Occurrences
RMS Noise (µV)
8
7
6
5
4
3
2
20
15
10
5
1
0
-40
-20
0
20
40
60
80
100
120
-0.010
-0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0.055
0.060
0.065
0.070
0.075
0.080
0.085
0.090
0
140
Temperature (°C)
FSR = ±2.048 V, DR = 8 SPS
Gain Error (%)
FSR = ±2.048 V, 185 units
Figure 17. Gain Error Histogram
4
140
3
120
2
Total Error (µV)
Number of Occurrences
Figure 16. Noise vs Temperature
160
100
80
60
1
0
-1
40
-2
20
-3
0
-3
-2
-1
0
1
2
3
-4
-2.048
-1.024
Offset (LSBs)
FSR = ±2.048 V, 185 units
Figure 18. Offset Histogram
0
1.024
2.048
Input Signal (V)
Differential inputs; includes noise, offset and gain error
Figure 19. Total Error vs Input Signal
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Typical Characteristics (continued)
at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 8 SPS (unless otherwise noted)
0
4
-10
VDD = 5 V
-20
2
1
Gain (dB)
Data Rate Error (%)
3
VDD = 3.3 V
0
-1
-30
-40
-50
-60
-2
VDD = 2 V
-3
-70
-80
-4
-40
-20
0
20
40
60
80
100
120
140
1
10
100
1k
10k
Input Frequency (Hz)
Temperature (°C)
DR = 8 SPS
Figure 20. Data Rate vs Temperature
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Figure 21. Digital Filter Frequency Response
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8 Parameter Measurement Information
8.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus
reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the inputreferred noise drops when reducing the output data rate because more samples of the internal modulator are
averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
Table 1 and Table 2 summarize the ADS111x noise performance. Data are representative of typical noise
performance at TA = 25°C with the inputs shorted together externally. Table 1 shows the input-referred noise in
units of μVRMS for the conditions shown. Note that µVPP values are shown in parenthesis. Table 2 shows the
effective resolution calculated from μVRMS values using Equation 1. The noise-free resolution calculated from
peak-to-peak noise values using Equation 2 are shown in parenthesis.
Effective Resolution = ln (FSR / VRMS-Noise) / ln(2)
Noise-Free Resolution = ln (FSR / VPP-Noise) / ln(2)
(1)
(2)
Table 1. Noise in μVRMS (μVPP) at VDD = 3.3 V
FSR (Full-Scale Range)
DATA RATE
(SPS)
±6.144 V
±4.096 V
±2.048 V
±1.024 V
±0.512 V
±0.256 V
8
187.5 (187.5)
125 (125)
62.5 (62.5)
31.25 (31.25)
15.62 (15.62)
7.81 (7.81)
16
187.5 (187.5)
125 (125)
62.5 (62.5)
31.25 (31.25)
15.62 (15.62)
7.81 (7.81)
32
187.5 (187.5)
125 (125)
62.5 (62.5)
31.25 (31.25)
15.62 (15.62)
7.81 (7.81)
64
187.5 (187.5)
125 (125)
62.5 (62.5)
31.25 (31.25)
15.62 (15.62)
7.81 (7.81)
128
187.5 (187.5)
125 (125)
62.5 (62.5)
31.25 (31.25)
15.62 (15.62)
7.81 (12.35)
250
187.5 (252.09)
125 (148.28)
62.5 (84.03)
31.25 (39.54)
15.62 (16.06)
7.81 (18.53)
475
187.5 (266.92)
125 (227.38)
62.5 (79.08)
31.25 (56.84)
15.62 (32.13)
7.81 (25.95)
860
187.5 (430.06)
125 (266.93)
62.5 (118.63)
31.25 (64.26)
15.62 (40.78)
7.81 (35.83)
Table 2. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise) at
VDD = 3.3 V
FSR (Full-Scale Range)
DATA RATE
(SPS)
±6.144 V
±4.096 V
±2.048 V
±1.024 V
±0.512 V
±0.256 V
8
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
32
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
64
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
128
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.33)
250
16 (15.57)
16 (15.75)
16 (15.57)
16 (15.66)
16 (15.96)
16 (14.75)
475
16 (15.49)
16 (15.13)
16 (15.66)
16 (15.13)
16 (14.95)
16 (14.26)
860
16 (14.8)
16 (14.9)
16 (15.07)
16 (14.95)
16 (14.61)
16 (13.8)
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9 Detailed Description
9.1 Overview
The ADS111x are very small, low-power, 16-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The
ADS111x consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator and an I2C interface. The
ADS1114 and ADS1115 also integrate a programmable gain amplifier (PGA) and a programmable digital
comparator. Figure 22, Figure 23, and Figure 24 show the functional block diagrams of ADS1115, ADS1114, and
ADS1113, respectively.
The ADS111x ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN). The
converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This
architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the
internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a
code proportional to the input voltage.
The ADS111x have two available conversion modes: single-shot and continuous-conversion. In single-shot
mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an
internal conversion register, and then enters a power-down state. This mode is intended to provide significant
power savings in systems that only require periodic conversions or when there are long idle periods between
conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as
soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed
data rate. Data can be read at any time and always reflect the most recent completed conversion.
9.2 Functional Block Diagrams
VDD
Comparator
ADS1115
Voltage
Reference
MUX
ALERT/RDY
AIN0
ADDR
AIN1
PGA
16-Bit û¯
ADC
I2C
Interface
SCL
SDA
AIN2
Oscillator
AIN3
GND
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Figure 22. ADS1115 Block Diagram
VDD
VDD
ADS1114
ADS1113
Comparator
Voltage
Reference
ADDR
AIN0
PGA
AIN1
16-Bit û¯
ADC
Voltage
Reference
ALERT/RDY
I 2C
Interface
ADDR
AIN0
SCL
AIN1
16-Bit û¯
ADC
SDA
Oscillator
GND
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Figure 23. ADS1114 Block Diagram
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SCL
SDA
Oscillator
14
I 2C
Interface
GND
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Figure 24. ADS1113 Block Diagram
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9.3 Feature Description
9.3.1 Multiplexer
The ADS1115 contains an input multiplexer (MUX), as shown in Figure 25. Either four single-ended or two
differential signals can be measured. Additionally, AIN0 and AIN1 may be measured differentially to AIN3. The
multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the
negative input of the ADC is internally connected to GND by a switch within the multiplexer.
ADS1115
VDD
AIN0
VDD
GND
AINP
AINN
AIN1
VDD
GND
AIN2
VDD
GND
AIN3
GND
GND
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Figure 25. Input Multiplexer
The ADS1113 and ADS1114 do not have an input multiplexer and can measure either one differential signal or
one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In
subsequent sections of this data sheet, AINP refers to AIN0 and AINN refers to AIN1 for the ADS1113 and
ADS1114.
Electrostatic discharge (ESD) diodes connected to VDD and GND protect the ADS111x analog inputs. Keep the
absolute voltage of any input within the range shown in Equation 3 to prevent the ESD diodes from turning on.
GND – 0.3 V < V(AINX) < VDD + 0.3 V
(3)
If the voltages on the input pins can potentially violate these conditions, use external Schottky diodes and series
resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).
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Feature Description (continued)
9.3.2 Analog Inputs
The ADS111x use a switched-capacitor input stage where capacitors are continuously charged and then
discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled
is called the sampling frequency or the modulator frequency (fMOD). The ADS111x has a 1-MHz internal oscillator
that is further divided by a factor of 4 to generate fMOD at 250 kHz. The capacitors used in this input stage are
small, and to external circuitry, the average loading appears resistive. Figure 26 shows this structure. The
capacitor values set the resistance and switching rate. Figure 27 shows the timing for the switches in Figure 26.
During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN), and CB to
(V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then
discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current
from the source driving the ADS111x analog inputs. The average value of this current can be used to calculate
the effective impedance (Zeff), where Zeff = VIN / IAVERAGE.
0.7 V
CA1
AINP
S1
S2
CB
Equivalent
Circuit
0.7 V
ZCM
AINP
ZDIFF
S2
S1
AINN
0.7 V
AINN
CA2
ZCM
fMOD = 250 kHz
0.7 V
Figure 26. Simplified Analog Input Circuit
tSAMPLE
ON
S1
OFF
ON
S2
OFF
Figure 27. S1 and S2 Switch Timing
The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and
AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance
changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In
Figure 26, the common-mode input impedance is ZCM.
The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one
input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and
scales with the full-scale range. In Figure 26, the differential input impedance is ZDIFF.
Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance,
the ADS111x input impedance may affect the measurement accuracy. For sources with high-output impedance,
buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider
all of these factors in high-accuracy applications.
The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most
applications, this input impedance drift is negligible, and can be ignored.
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Feature Description (continued)
9.3.3 Full-Scale Range (FSR) and LSB Size
A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the ADS1114 and ADS1115. The
full-scale range is configured by bits PGA[2:0] in the Config register and can be set to ±6.144 V, ±4.096 V,
±2.048 V, ±1.024 V, ±0.512 V, ±0.256 V. Table 3 shows the FSR together with the corresponding LSB size.
Equation 4 shows how to calculate the LSB size from the selected full-scale range.
LSB = FSR / 216
(4)
Table 3. Full-Scale Range and Corresponding LSB Size
(1)
FSR
LSB SIZE
±6.144 V (1)
187.5 μV
±4.096 V (1)
125 μV
±2.048 V
62.5 μV
±1.024 V
31.25 μV
±0.512 V
15.625 μV
±0.256 V
7.8125 μV
This parameter expresses the full-scale range of the ADC scaling.
Do not apply more than VDD + 0.3 V to the analog inputs of the
device.
The FSR of the ADS1113 is fixed at ±2.048 V.
Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings.
If a VDD supply voltage greater than 4 V is used, the ±6.144 V full-scale range allows input voltages to extend up
to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range; for example,
VDD = 3.3 V and full-scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. For example,
with VDD = 3.3 V and FSR = ±4.096 V, only signals up to VIN = ±3.3 V can be measured. The code range that
represents voltages |VIN| > 3.3 V is not used in this case.
9.3.4 Voltage Reference
The ADS111x have an integrated voltage reference. An external reference cannot be used with these devices.
Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included
in the gain error and gain drift specifications in the Electrical Characteristics table.
9.3.5 Oscillator
The ADS111x have an integrated oscillator running at 1 MHz. No external clock can be applied to operate these
devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with
the oscillator frequency.
9.3.6 Output Data Rate and Conversion Time
The ADS111x offer programmable output data rates. Use the DR[2:0] bits in the Config register to select output
data rates of 8 SPS, 16 SPS, 32 SPS, 64 SPS, 128 SPS, 250 SPS, 475 SPS, or 860 SPS.
Conversions in the ADS111x settle within a single cycle; thus, the conversion time is equal to 1 / DR.
9.3.7 Digital Comparator (ADS1114 and ADS1115 Only)
The ADS1115 and ADS1114 feature a programmable digital comparator that can issue an alert on the
ALERT/RDY pin. The COMP_MODE bit in the Config register configures the comparator as either a traditional
comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by
default) when conversion data exceeds the limit set in the high-threshold register (Hi_thresh). The comparator
then deasserts only when the conversion data falls below the limit set in the low-threshold register (Lo_thresh). In
window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh register
or fall below the Lo_thresh register value.
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In either window or traditional comparator mode, the comparator can be configured to latch after being asserted
by the COMP_LAT bit in the Config register. This setting causes the assertion to remain even if the input signal
is not beyond the bounds of the threshold registers. This latched assertion can only be cleared by issuing an
SMBus alert response or by reading the Conversion register. The ALERT/RDY pin can be configured as active
high or active low by the COMP_POL bit in the Config register. Operational diagrams for both the comparator
modes are shown in Figure 28.
The comparator can also be configured to activate the ALERT/RDY pin only after a set number of successive
readings exceed the threshold values set in the threshold registers (Hi_thresh and Lo_thresh). The
COMP_QUE[1:0] bits in the Config register configures the comparator to wait for one, two, or four readings
beyond the threshold before activating the ALERT/RDY pin. The COMP_QUE[1:0] bits can also disable the
comparator function, and put the ALERT/RDY pin into a high state.
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9.3.8 Conversion Ready Pin (ADS1114 and ADS1115 Only)
The ALERT/RDY pin can also be configured as a conversion ready pin. Set the most-significant bit of the
Hi_thresh register to 1 and the most-significant bit of Lo_thresh register to 0 to enable the pin as a conversion
ready pin. The COMP_POL bit continues to function as expected. Set the COMP_QUE[1:0] bits to any 2-bit
value other than 11 to keep the ALERT/RDY pin enabled, and allow the conversion ready signal to appear at the
ALERT/RDY pin output. The COMP_MODE and COMP_LAT bits no longer control any function. When
configured as a conversion ready pin, ALERT/RDY continues to require a pullup resistor. The ADS111x provide
an approximately 8-µs conversion ready pulse on the ALERT/RDY pin at the end of each conversion in
continuous-conversion mode, as shown in Figure 29. In single-shot mode, the ALERT/RDY pin asserts low at the
end of a conversion if the COMP_POL bit is set to 0.
TH_H
TH_H
Input Signal
Input Signal
TH_L
TH_L
Time
Time
Successful
SMBus Alert
Response
Latching
Comparator
Output
Latching
Comparator
Output
Successful
SMBus Alert
Response
Successful
SMBus Alert
Response
Time
Time
Non-Latching
Comparator
Output
Non-Latching
Comparator
Output
Time
Time
TRADITIONAL COMPARATOR MODE
WINDOW COMPARATOR MODE
Figure 28. ALERT Pin Timing Diagram
ADS1114/5
Status
Converting
Converting
Conversion Ready
Converting
Conversion Ready
Converting
Conversion Ready
8 µs
ALERT/RDY
(active high)
Figure 29. Conversion Ready Pulse in Continuous-Conversion Mode
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9.3.9 SMbus Alert Response
In latching comparator mode (COMP_LAT = 1), the ALERT/RDY pin asserts when the comparator detects a
conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by
reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I2C
address. If conversion data exceed the upper or lower threshold values after being cleared, the pin reasserts.
This assertion does not affect conversions that are already in progress. The ALERT/RDY pin is an open-drain
output. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a
high state so that the pin does not interfere with other devices on the same bus line.
When the master senses that the ALERT/RDY pin has latched, the master issues an SMBus alert command
(00011001) to the I2C bus. Any ADS1114 and ADS1115 data converters on the I2C bus with the ALERT/RDY
pins asserted respond to the command with the slave address. If more than one ADS111x on the I2C bus assert
the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus alert determines
which device clears assertion. The device with the lowest I2C address always wins arbitration. If a device loses
arbitration, the device does not clear the comparator output pin assertion. The master then repeats the SMBus
alert response until all devices have the respective assertions cleared. In window comparator mode, the SMBus
alert status bit indicates a 1 if signals exceed the high threshold, and a 0 if signals exceed the low threshold.
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9.4 Device Functional Modes
9.4.1 Reset and Power-Up
The ADS111x reset on power-up and set all the bits in the Config register to the respective default settings. The
ADS111x enter a power-down state after completion of the reset process. The device interface and digital blocks
are active, but no data conversions are performed. The initial power-down state of the ADS111x relieves systems
with tight power-supply requirements from encountering a surge during power-up.
The ADS111x respond to the I2C general-call reset commands. When the ADS111x receive a general call reset
command (06h), an internal reset is performed as if the device is powered-up.
9.4.2 Operating Modes
The ADS111x operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the Config
register selects the respective operating mode.
9.4.2.1 Single-Shot Mode
When the MODE bit in the Config register is set to 1, the ADS111x enter a power-down state, and operate in
single-shot mode. This power-down state is the default state for the ADS111x when power is first applied.
Although powered down, the devices still respond to commands. The ADS111x remain in this power-down state
until a 1 is written to the operational status (OS) bit in the Config register. When the OS bit is asserted, the
device powers up in approximately 25 μs, resets the OS bit to 0, and starts a single conversion. When
conversion data are ready for retrieval, the device powers down again. Writing a 1 to the OS bit while a
conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0 to the MODE bit in the
Config register.
9.4.2.2 Continuous-Conversion Mode
In continuous-conversion mode (MODE bit set to 0), the ADS111x perform conversions continuously. When a
conversion is complete, the ADS111x place the result in the Conversion register and immediately begin another
conversion. When writing new configuration settings, the currently ongoing conversion completes with the
previous configuration settings. Thereafter, continuous conversions with the new configuration settings start. To
switch to single-shot conversion mode, write a 1 to the MODE bit in the configuration register or reset the device.
9.4.3 Duty Cycling For Low Power
The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more
samples of the internal modulator are averaged to yield one conversion result. In applications where power
consumption is critical, the improved noise performance at low data rates may not be required. For these
applications, the ADS111x support duty cycling that yield significant power savings by periodically requesting
high data rate readings at an effectively lower data rate. For example, an ADS111x in power-down state with a
data rate set to 860 SPS can be operated by a microcontroller that instructs a single-shot conversion every 125
ms (8 SPS). A conversion at 860 SPS only requires approximately 1.2 ms, so the ADS111x enter power-down
state for the remaining 123.8 ms. In this configuration, the ADS111x consume approximately 1/100th the power
that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely arbitrary and is
defined by the master controller. The ADS111x offer lower data rates that do not implement duty cycling and also
offer improved noise performance if required.
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9.5 Programming
9.5.1 I2C Interface
The ADS111x communicate through an I2C interface. I2C is a two-wire open-drain interface that supports multiple
devices and masters on a single bus. Devices on the I2C bus only drive the bus lines low by connecting them to
ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so
the bus wires are always high when no device is driving them low. As a result of this configuration, two devices
cannot conflict. If two devices drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
as the slave. Both the master and slave can read and write, but the slave can only do so under the direction of
the master. Some I2C devices can act as a master or slave, but the ADS111x can only act as a slave device.
An I2C bus consists of two lines: SDA and SCL. SDA carries data; SCL provides the clock. All data are
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, drive the SDA line to the
appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). After
the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the
receiver shift register. If the I2C bus is held idle for more than 25 ms, the bus times out.
The I2C bus is bidirectional; that is, the SDA line is used for both transmitting and receiving data. When the
master reads from a slave, the slave drives the data line; when the master sends to a slave, the master drives
the data line. The master always drives the clock line. The ADS111x cannot act as a master, and therefore can
never drive SCL.
Most of the time the bus is idle; no communication occurs, and both lines are high. When communication takes
place, the bus is active. Only a master device can start a communication and initiate a START condition on the
bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes
state while the clock line is high, it is either a START condition or a STOP condition. A START condition occurs
when the clock line is high, and the data line goes from high to low. A STOP condition occurs when the clock line
is high, and the data line goes from low to high.
After the master issues a START condition, the master sends a byte that indicates with which slave device to
communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. The master sends an address in the address byte, together with a bit that indicates whether
the master wishes to read from or write to the slave device.
Every byte (address and data) transmitted on the I2C bus is acknowledged with an acknowledge bit. When the
master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave
to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock
pulse to clock the acknowledge bit. Similarly, when the master completes reading a byte, the master pulls SDA
low to acknowledge this completion to the slave. The master then sends a clock pulse to clock the bit. The
master always drives the clock line.
If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge
because no device is present at that address to pull the line low. A not-acknowledge is performed by simply
leaving SDA high during an acknowledge cycle.
When the master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. The master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated start condition.
The Timing Requirements section shows a timing diagram for the ADS111x I2C communication.
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Programming (continued)
9.5.1.1 I2C Address Selection
The ADS111x have one address pin, ADDR, that configures the I2C address of the device. This pin can be
connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin, as
shown in Table 4. The state of address pin ADDR is sampled continuously. Use the GND, VDD and SCL
addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line
goes low to make sure the device decodes the address correctly during I2C communication.
Table 4. ADDR Pin Connection and Corresponding Slave Address
ADDR PIN CONNECTION
SLAVE ADDRESS
GND
1001000
VDD
1001001
SDA
1001010
SCL
1001011
2
9.5.1.2 I C General Call
The ADS111x respond to the I2C general call address (0000000) if the eighth bit is 0. The devices acknowledge
the general call address and respond to commands in the second byte. If the second byte is 00000110 (06h), the
ADS111x reset the internal registers and enter a power-down state.
9.5.1.3 I2C Speed Modes
The I2C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100 kHz; fast
mode permits a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode) allows a clock
frequency of up to 3.4 MHz. The ADS111x are fully compatible with all three modes.
No special action is required to use the ADS111x in standard or fast mode, but high-speed mode must be
activated. To activate high-speed mode, send a special address byte of 00001xxx following the START condition,
where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code, and is different from
normal address bytes; the eighth bit does not indicate read/write status. The ADS111x do not acknowledge this
byte; the I2C specification prohibits acknowledgment of the Hs master code. Upon receiving a master code, the
ADS111x switch on Hs mode filters, and communicate at up to 3.4 MHz. The ADS111x switch out of Hs mode
with the next STOP condition.
For more information on high-speed mode, consult the I2C specification.
9.5.2 Slave Mode Operations
The ADS111x act as slave receivers or slave transmitters. The ADS111x cannot drive the SCL line as slave
devices.
9.5.2.1 Receive Mode
In slave receive mode, the first byte transmitted from the master to the slave consists of the 7-bit device address
followed by a low R/W bit. The next byte transmitted by the master is the Address Pointer register. The ADS111x
then acknowledge receipt of the Address Pointer register byte. The next two bytes are written to the address
given by the register address pointer bits, P[1:0]. The ADS111x acknowledge each byte sent. Register bytes are
sent with the most significant byte first, followed by the least significant byte.
9.5.2.2 Transmit Mode
In slave transmit mode, the first byte transmitted by the master is the 7-bit slave address followed by the high
R/W bit. This byte places the slave into transmit mode and indicates that the ADS111x are being read from. The
next byte transmitted by the slave is the most significant byte of the register that is indicated by the register
address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the master. The remaining least
significant byte is then sent by the slave and is followed by an acknowledgment from the master. The master
may terminate transmission after any byte by not acknowledging or issuing a START or STOP condition.
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9.5.3 Writing To and Reading From the Registers
To access a specific register from the ADS111x, the master must first write an appropriate value to register
address pointer bits P[1:0] in the Address Pointer register. The Address Pointer register is written to directly after
the slave address byte, low R/W bit, and a successful slave acknowledgment. After the Address Pointer register
is written, the slave acknowledges, and the master issues a STOP or a repeated START condition.
When reading from the ADS111x, the previous value written to bits P[1:0] determines the register that is read. To
change which register is read, a new value must be written to P[1:0]. To write a new value to P[1:0], the master
issues a slave address byte with the R/W bit low, followed by the Address Pointer register byte. No additional
data has to be transmitted, and a STOP condition can be issued by the master. The master can now issue a
START condition and send the slave address byte with the R/W bit high to begin the read. Figure 37 details this
sequence. If repeated reads from the same register are desired, there is no need to continually send the Address
Pointer register, because the ADS111x store the value of P[1:0] until it is modified by a write operation. However,
for every write operation, the Address Pointer register must be written with the appropriate values.
1
9
1
9
SCL
¼
SDA
1
0
0
1
0
A1
(1)
(1)
A0
0
R/W
Start By
Master
0
0
0
0
0
P1
ACK By
ADS1113/4/5
P0
ACK By
ADS1113/4/5
Stop By
Master
Frame 2: Address Pointer Register
Frame 1: Slave Address Byte
1
9
1
9
SCL
(Continued)
¼
SDA
(Continued)
1
0
0
0
1
A1
(1)
(1)
A0
R/W
Start By
Master
D15
D14
D13
D12 D11
ACK By
ADS1113/4/5
D10
D9
D8
From
ADS1113/4/5
¼
ACK By
Master
(2)
Frame 4: Data Byte 1 Read Register
Frame 3: Slave Address Byte
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
From
ADS1113/4/5
D1
D0
ACK By
Master
(3)
Stop By
Master
Frame 5: Data Byte 2 Read Register
(1)
The values of A0 and A1 are determined by the ADDR pin.
(2)
Master can leave SDA high to terminate a single-byte read operation.
(3)
Master can leave SDA high to terminate a two-byte read operation.
Figure 30. Timing Diagram for Reading From ADS111x
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1
9
9
1
SCL
¼
1
SDA
0
0
1
A1(1)
0
A0(1)
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
ADS1113/4/5
¼
ACK By
ADS1113/4/5
Frame 2: Address Pointer Register
Frame 1: Slave Address Byte
9
1
1
9
SCL
(Continued)
SDA
(Continued)
D15 D14
D13
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
ACK By
ADS1113/4/5
ACK By
ADS1113/4/5
Stop By
Master
Frame 4: Data Byte 2
Frame 3: Data Byte 1
(1)
D0
The values of A0 and A1 are determined by the ADDR pin.
Figure 31. Timing Diagram for Writing to ADS111x
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
Start By
Master
0
0
R/W
0
0
1
ACK By
ADS1113/4/5
Frame 1: SMBus ALERT Response Address Byte
(1)
1
A1
A0
From
ADS1113/4/5
Status
NACK By
Master
Stop By
Master
Frame 2: Slave Address
The values of A0 and A1 are determined by the ADDR pin.
Figure 32. Timing Diagram for SMBus Alert Response
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9.5.4 Data Format
The ADS111x provide 16 bits of data in binary two's complement format. A positive full-scale (+FS) input
produces an output code of 7FFFh and a negative full-scale (–FS) input produces an output code of 8000h. The
output clips at these codes for signals that exceed full-scale. Table 5 summarizes the ideal output codes for
different input signals. Figure 33 shows code transitions versus input voltage.
Table 5. Input Signal Versus Ideal Output Code
INPUT SIGNAL
VIN = (VAINP – VAINN)
IDEAL OUTPUT CODE(1) (1)
≥ +FS (215 – 1)/215
7FFFh
15
0001h
0
0000h
–FS/215
FFFFh
≤ –FS
8000h
+FS/2
(1)
Excludes the effects of noise, INL, offset, and gain errors.
7FFFh
0001h
0000h
FFFFh
...
Output Code
...
7FFEh
8001h
8000h
...
-FS
2
15
-FS
2
0
...
+FS
Input Voltage VIN
2
-1
15
15
+FS
2
-1
15
Figure 33. Code Transition Diagram
NOTE
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use
the positive code range from 0000h to 7FFFh. However, because of device offset, the
ADS111x can still output negative codes in case VAINP is close to 0 V.
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9.6 Register Map
The ADS111x have four registers that are accessible through the I2C interface using the Address Pointer
register. The Conversion register contains the result of the last conversion. The Config register is used to change
the ADS111x operating modes and query the status of the device. The other two registers, Lo_thresh and
Hi_thresh, set the threshold values used for the comparator function, and are not available in the ADS1113.
9.6.1 Address Pointer Register (address = N/A) [reset = N/A]
All four registers are accessed by writing to the Address Pointer register; see Figure 30.
Figure 34. Address Pointer Register
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
P[1:0]
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 6. Address Pointer Register Field Descriptions
Bit
Field
Type
Reset
Description
7:2
Reserved
W
0h
Always write 0h
1:0
P[1:0]
W
0h
Register address pointer
00
01
10
11
:
:
:
:
Conversion register
Config register
Lo_thresh register
Hi_thresh register
9.6.2 Conversion Register (P[1:0] = 0h) [reset = 0000h]
The 16-bit Conversion register contains the result of the last conversion in binary two's complement format.
Following power-up, the Conversion register is cleared to 0, and remains 0 until the first conversion is completed.
Figure 35. Conversion Register
15
D15
R-0h
7
D7
R-0h
14
D14
R-0h
6
D6
R-0h
13
D13
R-0h
5
D5
R-0h
12
D12
R-0h
4
D4
R-0h
11
D11
R-0h
3
D3
R-0h
10
D10
R-0h
2
D2
R-0h
9
D9
R-0h
1
D1
R-0h
8
D8
R-0h
0
D0
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Conversion Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
D[15:0]
R
0000h
16-bit conversion result
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9.6.3 Config Register (P[1:0] = 1h) [reset = 8583h]
The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and
comparator modes.
Figure 36. Config Register
15
OS
R/W-1h
7
14
6
DR[2:0]
R/W-4h
13
MUX[2:0]
R/W-0h
5
12
11
4
COMP_MODE
R/W-0h
3
COMP_POL
R/W-0h
10
PGA[2:0]
R/W-2h
2
COMP_LAT
R/W-0h
9
8
MODE
R/W-1h
1
0
COMP_QUE[1:0]
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Config Register Field Descriptions
Bit
Field
Type
Reset
Description
Operational status or single-shot conversion start
This bit determines the operational status of the device. OS can only be written
when in power-down state and has no effect when a conversion is ongoing.
15
OS
R/W
1h
When writing:
0 : No effect
1 : Start a single conversion (when in power-down state)
When reading:
0 : Device is currently performing a conversion
1 : Device is not currently performing a conversion
Input multiplexer configuration (ADS1115 only)
These bits configure the input multiplexer. These bits serve no function on the
ADS1113 and ADS1114.
14:12
MUX[2:0]
R/W
0h
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
AINP
AINP
AINP
AINP
AINP
AINP
AINP
AINP
= AIN0
= AIN0
= AIN1
= AIN2
= AIN0
= AIN1
= AIN2
= AIN3
and AINN = AIN1 (default)
and AINN = AIN3
and AINN = AIN3
and AINN = AIN3
and AINN = GND
and AINN = GND
and AINN = GND
and AINN = GND
Programmable gain amplifier configuration
These bits set the FSR of the programmable gain amplifier. These bits serve no
function on the ADS1113.
11:9
8
PGA[2:0]
MODE
R/W
R/W
2h
1h
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
FSR = ±6.144
FSR = ±4.096
FSR = ±2.048
FSR = ±1.024
FSR = ±0.512
FSR = ±0.256
FSR = ±0.256
FSR = ±0.256
V (1)
V (1)
V (default)
V
V
V
V
V
Device operating mode
This bit controls the operating mode.
0 : Continuous-conversion mode
1 : Single-shot mode or power-down state (default)
Data rate
These bits control the data rate setting.
7:5
(1)
28
DR[2:0]
R/W
4h
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
8 SPS
16 SPS
32 SPS
64 SPS
128 SPS (default)
250 SPS
475 SPS
860 SPS
This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the
device.
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Table 8. Config Register Field Descriptions (continued)
Bit
4
Field
COMP_MODE
Type
R/W
Reset
Description
0h
Comparator mode (ADS1114 and ADS1115 only)
This bit configures the comparator operating mode. This bit serves no function on
the ADS1113.
0 : Traditional comparator (default)
1 : Window comparator
3
COMP_POL
R/W
0h
Comparator polarity (ADS1114 and ADS1115 only)
This bit controls the polarity of the ALERT/RDY pin. This bit serves no function on
the ADS1113.
0 : Active low (default)
1 : Active high
Latching comparator (ADS1114 and ADS1115 only)
This bit controls whether the ALERT/RDY pin latches after being asserted or
clears after conversions are within the margin of the upper and lower threshold
values. This bit serves no function on the ADS1113.
2
1:0
COMP_LAT
COMP_QUE[1:0]
R/W
R/W
0h
3h
0 : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted
(default).
1 : Latching comparator. The asserted ALERT/RDY pin remains latched until
conversion data are read by the master or an appropriate SMBus alert response
is sent by the master. The device responds with its address, and it is the lowest
address currently asserting the ALERT/RDY bus line.
Comparator queue and disable (ADS1114 and ADS1115 only)
These bits perform two functions. When set to 11, the comparator is disabled and
the ALERT/RDY pin is set to a high-impedance state. When set to any other
value, the ALERT/RDY pin and the comparator function are enabled, and the set
value determines the number of successive conversions exceeding the upper or
lower threshold required before asserting the ALERT/RDY pin. These bits serve
no function on the ADS1113.
00
01
10
11
:
:
:
:
Assert after one conversion
Assert after two conversions
Assert after four conversions
Disable comparator and set ALERT/RDY pin to high-impedance (default)
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9.6.4 Lo_thresh (P[1:0] = 2h) [reset = 8000h] and Hi_thresh (P[1:0] = 3h) [reset = 7FFFh] Registers
The upper and lower threshold values used by the comparator are stored in two 16-bit registers in two's
complement format. The comparator is implemented as a digital comparator; therefore, the values in these
registers must be updated whenever the PGA settings are changed.
The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1 and
the Lo_thresh register MSB to 0. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register
value must always be greater than the Lo_thresh register value. The threshold register formats are shown in
Figure 37. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and
provides a continuous-conversion ready pulse when in continuous-conversion mode.
Figure 37. Lo_thresh Register
15
Lo_thresh15
R/W-1h
7
Lo_thresh7
R/W-0h
14
Lo_thresh14
R/W-0h
6
Lo_thresh6
R/W-0h
13
Lo_thresh13
R/W-0h
5
Lo_thresh5
R/W-0h
12
Lo_thresh12
R/W-0h
4
Lo_thresh4
R/W-0h
11
Lo_thresh11
R/W-0h
3
Lo_thresh3
R/W-0h
10
Lo_thresh10
R/W-0h
2
Lo_thresh2
R/W-0h
9
Lo_thresh9
R/W-0h
1
Lo_thresh1
R/W-0h
8
Lo_thresh8
R/W-0h
0
Lo_thresh0
R/W-0h
10
Hi_thresh10
R/W-1h
2
Hi_thresh2
R/W-1h
9
Hi_thresh9
R/W-1h
1
Hi_thresh1
R/W-1h
8
Hi_thresh8
R/W-1h
0
Hi_thresh0
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 38. Hi_thresh Register
15
Hi_thresh15
R/W-0h
7
Hi_thresh7
R/W-1h
14
Hi_thresh14
R/W-1h
6
Hi_thresh6
R/W-1h
13
Hi_thresh13
R/W-1h
5
Hi_thresh5
R/W-1h
12
Hi_thresh12
R/W-1h
4
Hi_thresh4
R/W-1h
11
Hi_thresh11
R/W-1h
3
Hi_thresh3
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Lo_thresh and Hi_thresh Register Field Descriptions
Bit
30
Field
Type
Reset
Description
15:0
Lo_thresh[15:0]
R/W
8000h
Low threshold value
15:0
Hi_thresh[15:0]
R/W
7FFFh
High threshold value
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The following sections give example circuits and suggestions for using the ADS111x in various situations.
10.1.1 Basic Connections
The principle I2C connections for the ADS1115 are shown in Figure 39.
10
ADS1115
1-k to 10-k (typ)
Pullup Resistors
VDD
Microcontroller or
Microprocessor
with I2C Port
VDD
SCL
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
0.1 …F (typ)
AIN1
5
SCL
SDA
GPIO
Inputs Selected
from Configuration
Register
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Figure 39. Typical Connections of the ADS1115
The fully-differential voltage input of the ADS111x is ideal for connection to differential sources with moderately
low source impedance, such as thermocouples and thermistors. Although the ADS111x can read bipolar
differential signals, these devices cannot accept negative voltages on either input.
The ADS111x draw transient currents during conversion. A 0.1-μF power-supply bypass capacitor supplies the
momentary bursts of extra current required from the supply.
The ADS111x interface directly to standard mode, fast mode, and high-speed mode I2C controllers. Any
microcontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with the
ADS111x. The ADS111x does not perform clock-stretching (that is, the device never pulls the clock line low), so
it is not necessary to provide for this function unless other clock-stretching devices are on the same I2C bus.
Pullup resistors are required on both the SDA and SCL lines because I2C bus drivers are open drain. The size of
these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors
consume less power, but increase the transition times on the bus, thus limiting the bus speed. Lower-value
resistors allow higher speed, but at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small because
the bus drivers may not be able to pull the bus lines low.
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Application Information (continued)
10.1.2 Single-Ended Inputs
The ADS1113 and ADS1114 can measure one, and the ADS1115 up to four, single-ended signals. The
ADS1113 and ADS1114 can measure single-ended signals by connecting AIN1 to GND externally. The
ADS1115 measures single-ended signals by appropriate configuration of the MUX[2:0] bits in the Config register.
Figure 40 shows a single-ended connection scheme for ADS1115. The single-ended signal ranges from 0 V up
to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to these devices because the
ADS111x can only accept positive voltages with respect to ground. The ADS111x do not lose linearity within the
input range.
The ADS111x offer a differential input voltage range of ±FSR. Single-ended configurations use only one-half of
the full-scale input voltage range. Differential configurations maximize the dynamic range of the ADC, and
provide better common-mode noise rejection than single-ended configurations.
VDD
Output Codes
0-32767
10
ADS1115
SCL
1
ADDR
SDA 9
2
ALERT/RDY
VDD 8
3
GND
AIN3 7
4
AIN0
AIN2 6
0.1 F (typ)
AIN1
5
Inputs Selected
from Configuration
Register
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NOTE: Digital pin connections omitted for clarity.
Figure 40. Measuring Single-Ended Inputs
The ADS1115 also allows AIN3 to serve as a common point for measurements by appropriate setting of the
MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the
ADS1115 operates with inputs, where AIN3 serves as the common point. This ability improves the usable range
over the single-ended configuration because negative differential voltages are allowed when
GND < V(AIN3) < VDD; however, common-mode noise attenuation is not offered.
10.1.3 Input Protection
The ADS111x are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection
diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS111x can
be permanently damaged by analog input voltages that exceed approximately 300 mV beyond the rails for
extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines.
The ADS111x analog inputs can withstand continuous currents as large as 10 mA.
10.1.4 Unused Inputs and Outputs
Either float unused analog inputs, or tie the unused analog inputs to midsupply or VDD. Connecting unused
analog inputs to GND is possible, but may yield higher leakage currents than the previous options.
Either float NC (not-connected) pins, or tie the NC pins to GND. If the ALERT/RDY output pin is not used, leave
the pin unconnected or tie the pin to VDD using a weak pullup resistor.
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Application Information (continued)
10.1.5 Analog Input Filtering
Analog input filtering serves two purposes:
1. Limits the effect of aliasing during the sampling process
2. Reduces external noise from being a part of the measurement
Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling
frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back and show
up in the actual frequency band of interest below half the sampling frequency. The filter response of the digital
filter repeats at multiples of the sampling frequency, also known as the modulator frequency (fMOD), as shown in
Figure 41. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain
amount by the digital filter depending on the filter architecture. Any frequency components present in the input
signal around the modulator frequency, or multiples thereof, are not attenuated and alias back into the band of
interest, unless attenuated by an external analog filter.
Magnitude
Sensor
Signal
Output
Data Rate
Magnitude
Unwanted
Signals
Unwanted
Signals
fMOD / 2
fMOD
Frequency
fMOD
Frequency
fMOD
Frequency
Digital Filter
Aliasing of
Unwanted Signals
Output
Data Rate
fMOD / 2
Magnitude
External
Antialiasing Filter
Roll-Off
Output
Data Rate
fMOD / 2
Figure 41. Effect of Aliasing
Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of
change. In this case, the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However,
any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass-band.
Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated
from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors
and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) itself in the form of
clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the
measurement result.
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to
reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is
attenuated to a level below the noise floor of the ADC. The digital filter of the ADS111x attenuate signals to a
certain degree, as shown in Figure 21. In addition, noise components are usually smaller in magnitude than the
actual sensor signal. Therefore, use a first-order RC filter with a cutoff frequency set at the output data rate or
10x higher as a generally good starting point for a system design.
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Application Information (continued)
10.1.6 Connecting Multiple Devices
It is possible to connect up to four ADS111x devices to a single I2C bus using different address pin configurations
for each device. Use the address pin to set the ADS111x to one of four different I2C addresses. Use the GND,
VDD and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns
after the SCL line goes low to make sure the device decodes the address correctly during I2C communication. An
example showing four ADS111x devices on the same I2C bus is shown in Figure 42. One set of pullup resistors
is required per bus. The pullup resistor values may need to be lowered to compensate for the additional bus
capacitance presented by multiple devices and increased line length.
VDD
GND
10
ADS1115
1-k to 10-k (typ)
I2C Pullup Resistors
Microcontroller or
Microprocessor
With I2C Port
VDD
SCL
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
AIN1
5
SCL
SDA
10
ADS1115
SCL
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
AIN1
5
10
ADS1115
SCL
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
AIN1
5
10
ADS1115
SCL
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
AIN1
5
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NOTE: ADS111x power and input connections omitted for clarity. The ADDR pin selects the I2C address.
Figure 42. Connecting Multiple ADS111x Devices
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Application Information (continued)
10.1.7 Quickstart Guide
This section provides a brief example of ADS111x communications. See subsequent sections of this data sheet
for more detailed explanations. Hardware for this design includes: one ADS111x configured with an I2C address
of 1001000; a microcontroller with an I2C interface; discrete components such as resistors, capacitors, and serial
connectors; and a 2 V to 5 V power supply. Figure 43 shows the basic hardware configuration.
The ADS111x communicate with the master (microcontroller) through an I2C interface. The master provides a
clock signal on the SCL pin and data are transferred using the SDA pin. The ADS111x never drive the SCL pin.
For information on programming and debugging the microcontroller being used, see the device-specific product
data sheet.
The first byte sent by the master is the ADS111x address, followed by the R/W bit that instructs the ADS111x to
listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and fourth bytes
sent from the master are written to the register indicated in register address pointer bits P[1:0]. See Figure 30
and Figure 31 for read and write operation timing diagrams, respectively. All read and write transactions with the
ADS111x must be preceded by a START condition, and followed by a STOP condition.
For example, to write to the configuration register to set the ADS111x to continuous-conversion mode and then
read the conversion result, send the following bytes in this order:
1. Write to Config register:
– First byte: 0b10010000 (first 7-bit I2C address followed by a low R/W bit)
– Second byte: 0b00000001 (points to Config register)
– Third byte: 0b10000100 (MSB of the Config register to be written)
– Fourth byte: 0b10000011 (LSB of the Config register to be written)
2. Write to Address Pointer register:
– First byte: 0b10010000 (first 7-bit I2C address followed by a low R/W bit)
– Second byte: 0b00000000 (points to Conversion register)
3. Read Conversion register:
– First byte: 0b10010001 (first 7-bit I2C address followed by a high R/W bit)
– Second byte: the ADS111x response with the MSB of the Conversion register
– Third byte: the ADS111x response with the LSB of the Conversion register
3.3 V
ADS111x
VDD
0.1 µF
GND
2
3.3 V
I C-Capable Master
(MSP430F2002)
AIN0
AIN1
3.3 V
ADDR
AIN2 (ADS1115 Only)
AIN3 (ADS1115 Only)
10 k
10 k
SCL
SCL (P1.6)
SDA
SDA (P1.7)
VDD
0.1 µF
GND
ALERT
(ADS1114/5 Only)
JTAG
Serial/UART
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Figure 43. Basic Hardware Configuration
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10.2 Typical Application
Shunt-based, current-measurement solutions are widely used to monitor load currents. Low-side, current-shunt
measurements are independent of the bus voltage because the shunt common-mode voltage is near ground.
Figure 44 shows an example circuit for a bidirectional, low-side, current-shunt measurement system. The load
current is determined by measuring the voltage across the shunt resistor that is amplified and level-shifted by a
low-drift operational amplifier, OPA333. The OPA333 output voltage is digitized with ADS1115 and sent to the
microcontroller using the I2C interface. This circuit is capable of measuring bidirectional currents flowing through
the shunt resistor with great accuracy and precision.
High-Voltage Bus
VCM
VDD
VDD
CCM2
LOAD
R6
AINN
ILOAD
VINX
RSHUNT
4-Wire Kelvin
Connection
R3
R4
VSHUNT
+
OPA333
±
VOUT
CDIFF
ADS1115
I2C
R5
AINP
R1
CCM1
R2
Figure 44. Low-Side Current Shunt Monitoring
10.2.1 Design Requirements
Table 10 shows the design parameters for this application.
Table 10. Design Parameters
DESIGN PARAMETER
VALUE
Supply voltage (VDD)
5V
Voltage across Shunt Resistor (VSHUNT)
±50 mV
≥200 readings per second
Output Data Rate (DR)
Typical measurement accuracy at TA = 25°C
(1)
(1)
±0.2%
Does not account for inaccuracy of shunt resistor and the precision resistors used in the application.
10.2.2 Detailed Design Procedure
The first stage of the application circuit consists of an OPA333 in a noninverting summing amplifier configuration
and serves two purposes:
1. To level-shift the ground-referenced signal to allow bidirectional current measurements while running off a
unipolar supply. The voltage across the shunt resistor, VSHUNT, is level-shifted by a common-mode voltage,
VCM, as shown in Figure 44. The level-shifted voltage, VINX, at the noninverting input is given by Equation 5.
VINX = (VCM · R3 + VSHUNT · R4) / (R3 + R4)
(5)
2. To amplify the level-shifted voltage (VINX). The OPA333 is configured in a noninverting gain configuration
with the output voltage, VOUT, given by Equation 6.
VOUT = VINX · (1 + R2 / R1)
(6)
Using Equation 5 and Equation 6, VOUT is given as a function of VSHUNT and VCM by Equation 7.
VOUT = (VCM · R3 + VSHUNT · R4) / (R3 + R4) · (1 + R2 / R1)
(7)
Using Equation 7 the ADC differential input voltage, before the first-order RC filter, is given by Equation 8.
VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) + VCM · (R2 / R1 – R3 / R4) / (1 + R3 / R4)
(8)
If R1 = R3 and R2 = R4, Equation 8 is simplified to Equation 9.
VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3)
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10.2.2.1 Shunt Resistor Considerations
A shunt resistor (RSHUNT) is an accurate resistance inserted in series with the load as shown in Figure 44. If the
absolute voltage drop across the shunt, |VSHUNT|, is a larger percentage of the bus voltage, the voltage drop may
reduce the overall efficiency and system performance. If |VSHUNT| is too low, measuring the small voltage drop
requires careful design attention and proper selection of the ADC, operation amplifier, and precision resistors.
Make sure that the absolute voltage at the shunt terminals does not result in violation of the input common-mode
voltage range requirements of the operational amplifier. The power dissipation on the shunt resistor increases
the temperature because of the current flowing through it. To minimize the measurement errors due to variation
in temperature, select a low-drift shunt resistor. To minimize the measurement gain error, select a shunt resistor
with low tolerance value. To remove the errors due to stray ground resistance, use a four-wire Kelvin-connected
shunt resistor, as shown in Figure 44.
10.2.2.2 Operational Amplifier Considerations
The operational amplifier used for this design example requires the following features:
• Unipolar supply operation (5 V)
• Low input offset voltage (< 10 µV) and input offset voltage drift (< 0.5 µV/°C)
• Rail-to-rail input and output capability
• Low thermal and flicker noise
• High common-mode rejection (> 100 dB)
OPA333 offers all these benefits and is selected for this application.
10.2.2.3 ADC Input Common-Mode Considerations
VCM sets the VOUT common-mode voltage by appropriate selection of precision resistors R1, R2, R3, and R4.
If R1 = R3, R2 = R4, and VSHUNT = 0 V, VOUT is given by Equation 10.
VOUT = VCM
(10)
If VOUT is connected to the ADC positive input (AINP) and VCM is connected to the ADC negative input (AINN),
VCM appears as a common-mode voltage to the ADC. This configuration allows pseudo-differential
measurements and uses the maximum dynamic range of the ADC if VCM is set at midsupply (VDD / 2). A resistor
divider from VDD to GND followed by a buffer amplifier can be used to generate VCM.
10.2.2.4 Resistor (R1, R2, R3, R4) Considerations
Proper selection of resistors R1, R2, R3 and R4 is critical for meeting the overall accuracy requirements.
Using Equation 8, the offset term, VOUT-OS, and the gain term, AOUT, of the differential ADC input are represented
by Equation 11 and Equation 12 respectively. The error contributions from the first-order RC filters are ignored.
VOUT-OS = VCM · (R2 / R1 - R3 / R4) / (1 + R3 / R4)
AOUT = (1 + R2 / R1) / (1 + R4 / R3)
(11)
(12)
The tolerance, drift and linearity performance of these resistors is critical to meeting the overall accuracy
requirements. In Equation 11, if R1 = R3 and R2 = R4, VOUT-OS = 0 V and therefore, the common-mode voltage,
VCM, only contributes to level-shift VSHUNT and does not introduce any error at the differential ADC inputs. Highprecision resistors provide better common-mode rejection from VCM.
10.2.2.5 Noise and Input Impedance Considerations
If vn_res represents the input-referred rms noise from all the resistors, vn_op represents the input-referred rms
noise of OPA333, and vn_ADC represents the input-referred rms noise of ADS1115, the total input-referred noise
of the entire system, vN, can be approximated by Equation 13.
vN2 = vn_res2 + vn_op2 + vn_ADC/ (1 + R2 / R1)2
(13)
It is important to note that the ADC noise contribution, vn_ADC, is attenuated by the non-inverting gain stage.
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If the gain of the noninverting gain stage is high (≥ 5), a good approximation for vn_res2 is given by Equation 14.
The noise contribution from resistors R2, R4, R5, and R6 when referred to the input is smaller in comparison to R1
and R3 and can be neglected for approximation purposes.
vn_res2 = 4 · k · T · (R1 + R3) · Δf
where
•
•
•
where k = Boltzmann constant
T = temperature (in kelvins)
Δf = noise bandwidth
(14)
An approximation for the input impedance, RIN, of the application circuit is given by Equation 15. RIN can be
modeled as a resistor in parallel with the shunt resistor, and can contribute to additional gain error.
RIN = R3 + R4
(15)
From Equation 14 and Equation 15, a trade-off exists between vN and RIN. If R3 increases, vn_res increases, and
therefore, the total input-referred rms system noise, vN, increases. If R3 decreases, the input impedance, RIN,
drops, and causes additional gain error.
10.2.2.6 First-order RC Filter Considerations
Although the device digital filter attenuates high-frequency noise, use a first order low-pass RC filter at the ADC
inputs to further reject out-of-bandwidth noise and avoid aliasing. A differential low-pass RC filter formed by R5,
R6, and the differential capacitor CDIFF sets the –3-dB cutoff frequency, fC, given by Equation 16. These filter
resistors produce a voltage drop because of the input currents flowing into and out of the ADC. This voltage drop
could contribute to an additional gain error. Limit the filter resistor values to below 1 kΩ.
fC = 1 / [2π · (R5 + R6) · CDIFF]
(16)
Two common-mode filter capacitors (CCM1 and CCM2) are also added to offer attenuation of high-frequency,
common-mode noise components. Select a differential capacitor, CDIFF, that is at least an order of magnitude
(10x) larger than these common-mode capacitors because mismatches in these common-mode capacitors can
convert common-mode noise into differential noise.
10.2.2.7 Circuit Implementation
Table 11 shows the chosen values for this design.
Table 11. Parameters
PARAMETER
(1)
VALUE
VCM
2.5 V
FSR of ADC
±0.256 V
Output Data Rate
250 SPS
R1, R3
1 kΩ (1)
R2, R4
5 kΩ (1)
R5, R6
100 Ω (1)
CDIFF
0.22 µF
CCM1, CCM2
0.022 µF
1% precision resistors used
Using Equation 7, if VSHUNT ranges from –50 mV to +50 mV, the application circuit produces a differential voltage
ranging from –0.250 V to +0.250 V across the ADC inputs . The ADC is therefore configured at a FSR of ±0.256
V to maximize the dynamic range of the ADC.
The –3 dB cutoff frequencies of the differential low-pass filter and the common-mode low-pass filters are set at
3.6 kHz and 0.36 kHz, respectively.
RSHUNT typically ranges from 0.01 mΩ to 100 mΩ. Therefore, if R1 = R3 = 1 kΩ, a good trade-off exists between
the circuit input impedance and input referred resistor noise as explained in the Noise and Input Impedance
Considerations section.
A simple resistor divider followed by a buffer amplifier is used to generate VCM of 2.5 V from a 5-V supply.
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10.2.2.8 Results Summary
A precision voltage source is used to sweep VSHUNT from –50 mV to +50 mV. The application circuit produces a
differential voltage of –250 mV to +250 mV across the ADC inputs. Figure 45 and Figure 46 show the
measurement results. The measurements are taken at TA = 25°C. Although 1% tolerance resistors are used, the
exact value of these resistors are measured with a Fluke 4.5 digit multimeter to exclude the errors due to
inaccuracy of these resistors. In Figure 45, the x-axis represents VSHUNT and the black line represents the
measured digital output voltage in mV. In Figure 46, the x-axis represents VSHUNT, the black line represents the
total measurement error in %, the blue line represents the total measurement error in % after excluding the
errors from precision resistors and the green line represents the total measurement error in % after excluding the
errors from precision resistors and performing a system offset calibration with VSHUNT = 0 V. Table 12 shows a
results summary.
Table 12. Results Summary (1)
PARAMETER
VALUE
Total error, including errors from 1% precision resistors
1.89%
Total error, excluding errors from 1% precision resistors
0.17%
Total error, after offset calibration, excluding errors from 1% precision resistors
0.11%
(1)
TA = 25°C, not accounting for inaccuracy of shunt resistor.
10.2.3 Application Curves
250
150
Measurement Error ( )
Measured Output (mV)
200
100
50
0
-50
-100
-150
-200
-250
-60 -50 -40 -30 -20 -10 0 10 20
Shunt Voltage (mV)
30
40
50
60
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-1.25
-1.5
-1.75
-2
-50
Including all errors
Excluding resistor errors
Excluding resistor errors, after offset calibration
-40
-30
-20
D004
Figure 45. Measured Output vs Shunt Voltage (VSHUNT)
-10
0
10
20
Shunt Voltage (mV)
30
40
50
D005
Figure 46. Measurement Error vs Shunt Voltage (VSHUNT)
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11 Power Supply Recommendations
The device requires a single unipolar supply, VDD, to power both the analog and digital circuitry of the device.
11.1 Power-Supply Sequencing
Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up
reset process to complete.
11.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at
least a 0.1-µF capacitor, as shown in Figure 47. The 0.1-μF bypass capacitor supplies the momentary bursts of
extra current required from the supply when the device is converting. Place the bypass capacitor as close to the
power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip
capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for
power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments,
avoid the use of vias for connecting the capacitors to the device pins for better noise immunity. The use of
multiple vias in parallel lowers the overall inductance, and is beneficial for connections to ground planes.
VDD
TI Device
10
DIN
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
0.1 µF
AIN1
5
Figure 47. ADS1115 Power-Supply Decoupling
40
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SBAS444D – MAY 2009 – REVISED JANUARY 2018
12 Layout
12.1 Layout Guidelines
Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital
components. For optimal performance, separate the analog components [such as ADCs, amplifiers, references,
digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers,
complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF)
transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component
placement is shown in Figure 48. Although Figure 48 provides a good example of component placement, the
best placement for each application is unique to the geometries, components, and PCB fabrication capabilities
employed. That is, there is no single layout that is perfect for every design and careful consideration must always
be used when designing with any analog component.
Ground Fill or
Ground Plane
Supply
Generation
Microcontroller
Device
Optional: Split
Ground Cut
Signal
Conditioning
(RC Filters
and
Amplifiers)
Ground Fill or
Ground Plane
Optional: Split
Ground Cut
Ground Fill or
Ground Plane
Interface
Transceiver
Connector
or Antenna
Ground Fill or
Ground Plane
Figure 48. System Component Placement
The following outlines some basic recommendations for the layout of the ADS111x to get the best possible
performance of the ADC. A good design can be ruined with a bad circuit layout.
•
•
•
•
•
•
•
Separate analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Route digital lines away from analog lines. This prevents digital noise from coupling back into
analog signals.
Fill void areas on signal layers with ground fill.
Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, it has to find
another path to return to the source and complete the circuit. If it is forced into a larger path, it increases the
chance that the signal radiates. Sensitive signals are more susceptible to EMI interference.
Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source
signal and the return current in order to reduce the inductance in the path. Reduce the inductance to reduce
the EMI pickup, and reduce the high frequency impedance seen by the device.
Differential inputs must be matched for both the inputs going to the measurement source.
Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines such as AIN0, AIN1 and
AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO), which have stable properties and low-noise characteristics.
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SDA
SCL
ADDR
ALERT/RDY
12.2 Layout Example
VDD
10
SCL
1
ADDR
2
ALERT/RDY
SDA
9
VDD
8
AIN3
TI Device
3
GND
4
AIN0
AIN1
AIN3
7
AIN2
6
5
Vias connect to either bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
AIN1
AIN0
AIN2
SCL
SDA
ADDR
ALERT/RDY
Figure 49. ADS1115 X2QFN Package
VDD
1
ADDR
2
ALERT/RDY
3
GND
4
5
SCL
10
SDA
9
VDD
8
AIN0
AIN3
7
AIN1
AIN2
6
AIN3
AIN0
TI Device
AIN2
AIN1
Vias connect to either bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
Figure 50. ADS1115 VSSOP Package
42
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ADS1113, ADS1114, ADS1115
www.ti.com
SBAS444D – MAY 2009 – REVISED JANUARY 2018
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• OPAx333 1.8-V, microPower, CMOS Operational Amplifiers, Zero-Drift Series (SBOS351)
• MSP430F20x1, MSP430F20x2, MSP430F20x3 Mixed Signal Microcontroller (SLAS491)
• TIDA-00824 Human Skin Temperature Sensing for Wearable Applications Reference Design (TIDUAY7)
13.2 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADS1113
Click here
Click here
Click here
Click here
Click here
ADS1114
Click here
Click here
Click here
Click here
Click here
ADS1115
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
44
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Product Folder Links: ADS1113 ADS1114 ADS1115
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS1113IDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BROI
ADS1113IDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BROI
ADS1113IRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N6J
ADS1113IRUGT
ACTIVE
X2QFN
RUG
10
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N6J
ADS1114IDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BRNI
ADS1114IDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BRNI
ADS1114IRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N5J
ADS1114IRUGT
ACTIVE
X2QFN
RUG
10
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N5J
ADS1115IDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BOGI
ADS1115IDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BOGI
ADS1115IRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N4J
ADS1115IRUGT
ACTIVE
X2QFN
RUG
10
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N4J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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